JPS63132452U - - Google Patents
Info
- Publication number
- JPS63132452U JPS63132452U JP2444187U JP2444187U JPS63132452U JP S63132452 U JPS63132452 U JP S63132452U JP 2444187 U JP2444187 U JP 2444187U JP 2444187 U JP2444187 U JP 2444187U JP S63132452 U JPS63132452 U JP S63132452U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- diffusion layer
- well layer
- conductivity type
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案に係るＭＯＳ型ＩＣの模式的断
面構造図、第２図は従来のＭＯＳ型ＩＣの模式的
断面構造図である。
１０…半導体基板（Ｎ型）、１１…Ｐウエル層
、１３…ＭＯＳトランジスタ、１４…Ｎ＋拡散層
、１５…フローテイングノード、Ｉｓｕｂ…基板
電流。
FIG. 1 is a schematic cross-sectional structural diagram of a MOS type IC according to the present invention, and FIG. 2 is a schematic cross-sectional structural diagram of a conventional MOS type IC. DESCRIPTION OF SYMBOLS 10...Semiconductor substrate (N type), 11...P well layer, 13...MOS transistor, 14...N + diffusion layer, 15...floating node, Isub...substrate current.
Claims (1)
エル層に、ＭＯＳトランジスタと、ウエル層の電
位設定用拡散層と、これらの間に設けられてデー
タを保持するためのフローテイングノードとを備
えてなるＭＯＳ型ＩＣにおいて、 前記ウエル層におけるＭＯＳトランジスタと前
記フローテイングノードとの間に、基板電流によ
り生じる電位変動に追従する電位を得る前記逆導
電型の拡散層を設けて、該拡散層とＭＯＳトラン
ジスタのソースとを導電体で接続したことを特徴
とするＭＯＳ型ＩＣ。[Claim for Utility Model Registration] A well layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, a MOS transistor, a diffusion layer for setting the potential of the well layer, and a diffusion layer provided between these to hold data. A MOS type IC comprising: a floating node for a MOS transistor in the well layer, and a diffusion layer of the opposite conductivity type that obtains a potential that follows potential fluctuations caused by a substrate current between the MOS transistor in the well layer and the floating node. A MOS type IC characterized in that the diffusion layer and the source of the MOS transistor are connected by a conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2444187U JPS63132452U (en) | 1987-02-20 | 1987-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2444187U JPS63132452U (en) | 1987-02-20 | 1987-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63132452U true JPS63132452U (en) | 1988-08-30 |
Family
ID=30823672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2444187U Pending JPS63132452U (en) | 1987-02-20 | 1987-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63132452U (en) |
-
1987
- 1987-02-20 JP JP2444187U patent/JPS63132452U/ja active Pending
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