JPS63114047U

JPS63114047U -

Info

Publication number: JPS63114047U
Application number: JP611587U
Authority: JP
Priority date: 1987-01-20
Filing date: 1987-01-20
Publication date: 1988-07-22

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例であり不揮発性半導
体メモリ装置の断面図、第２図は従来の不揮発性
半導体メモリ装置の断面図である。１は不揮発性半導体メモリ装置、２は基板、３
はソース、４はドレイン、５は凹部、６は第１の
絶縁膜、７は浮遊ゲート電極、８は第２の絶縁膜
、９は第１の制御ゲート電極、１０は第３の絶縁
膜、１１は第２の制御ゲート電極、１２は絶縁膜
、１３はソース電極、１４はドレイン電極である
。 FIG. 1 is a sectional view of a non-volatile semiconductor memory device, which is an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional non-volatile semiconductor memory device. 1 is a nonvolatile semiconductor memory device, 2 is a substrate, 3
is a source, 4 is a drain, 5 is a recess, 6 is a first insulating film, 7 is a floating gate electrode, 8 is a second insulating film, 9 is a first control gate electrode, 10 is a third insulating film, 11 is a second control gate electrode, 12 is an insulating film, 13 is a source electrode, and 14 is a drain electrode.

Claims

[Scope of utility model registration request]

A source and a drain provided spaced apart from each other on a surface of a semiconductor substrate, a recess formed in a channel region between the source and the drain, a first insulating film formed on the recess, and the first insulating film. A floating gate electrode buried in the lower layer of the recess through a film, a second insulating film formed on the floating gate electrode, and a first insulating film formed from the source to above the second insulating film. a control gate electrode formed on the first control gate electrode, and a third control gate electrode formed on the first control gate electrode.
A nonvolatile semiconductor memory device comprising: an insulating film; and a second control gate electrode formed from the drain to above the third insulating film.