JPS63114045U - - Google Patents
Info
- Publication number
- JPS63114045U JPS63114045U JP570587U JP570587U JPS63114045U JP S63114045 U JPS63114045 U JP S63114045U JP 570587 U JP570587 U JP 570587U JP 570587 U JP570587 U JP 570587U JP S63114045 U JPS63114045 U JP S63114045U
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- substrate
- semiconductor memory
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Description
第1図は本考案に依る不揮発性半導体メモリ装
置を説明する上面図、第2図および第3図は第1
図の―線および―線断面図、第4図は従
来のEP・ROMを説明する断面図である。
1は半導体基板、2はフイールド酸化膜、3は
ゲート酸化膜、4は素子形成領域、5はコントロ
ールゲート、6はシリコン酸化膜、7はフローテ
イングゲート、8はドレイン領域、9はソース領
域、10はチヤンネル領域である。
FIG. 1 is a top view illustrating a nonvolatile semiconductor memory device according to the present invention, and FIGS.
FIG. 4 is a sectional view illustrating a conventional EP-ROM. 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is an element formation region, 5 is a control gate, 6 is a silicon oxide film, 7 is a floating gate, 8 is a drain region, 9 is a source region, 10 is a channel area.
Claims (1)
したフイールド酸化膜と前記基板の素子形成領域
に形成したゲート酸化膜と前記ゲート酸化膜上に
配置されるフローテイングゲートとコントロール
ゲートとを有する不揮発性半導体メモリ装置にお
いて、前記フローテイングゲートとコントロール
ゲートを前記ゲート酸化膜上では平面的に配置し
、前記フイールド酸化膜上で積層して容量結合さ
せるように配置する事を特徴とする不揮発性半導
体メモリ装置。 A nonvolatile semiconductor memory comprising a semiconductor substrate, a field oxide film formed in a field region of the substrate, a gate oxide film formed in an element formation region of the substrate, and a floating gate and a control gate arranged on the gate oxide film. A nonvolatile semiconductor memory device characterized in that the floating gate and the control gate are arranged planarly on the gate oxide film, and are stacked and capacitively coupled on the field oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987005705U JPH0720918Y2 (en) | 1987-01-19 | 1987-01-19 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987005705U JPH0720918Y2 (en) | 1987-01-19 | 1987-01-19 | Nonvolatile semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63114045U true JPS63114045U (en) | 1988-07-22 |
JPH0720918Y2 JPH0720918Y2 (en) | 1995-05-15 |
Family
ID=30787540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987005705U Expired - Lifetime JPH0720918Y2 (en) | 1987-01-19 | 1987-01-19 | Nonvolatile semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0720918Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165382A (en) * | 1982-03-09 | 1983-09-30 | ア−ルシ−エ− コ−ポレ−ション | Floating gate memory device |
JPS61225862A (en) * | 1985-03-30 | 1986-10-07 | Toshiba Corp | Semiconductor memory device |
-
1987
- 1987-01-19 JP JP1987005705U patent/JPH0720918Y2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165382A (en) * | 1982-03-09 | 1983-09-30 | ア−ルシ−エ− コ−ポレ−ション | Floating gate memory device |
JPS61225862A (en) * | 1985-03-30 | 1986-10-07 | Toshiba Corp | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPH0720918Y2 (en) | 1995-05-15 |
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