JPH0369256U - - Google Patents
Info
- Publication number
- JPH0369256U JPH0369256U JP1989131166U JP13116689U JPH0369256U JP H0369256 U JPH0369256 U JP H0369256U JP 1989131166 U JP1989131166 U JP 1989131166U JP 13116689 U JP13116689 U JP 13116689U JP H0369256 U JPH0369256 U JP H0369256U
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- floating gate
- semiconductor substrate
- isolation region
- control gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 230000005684 electric field Effects 0.000 claims 1
- 238000000638 solvent extraction Methods 0.000 claims 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
第１図は本考案の不揮発性メモリの要部平面図
、第２図は従来の不揮発性メモリの要部を示す平
面図、第３図は第２図のＸ−Ｙ断面図である。
FIG. 1 is a plan view of essential parts of a non-volatile memory according to the present invention, FIG. 2 is a plan view showing essential parts of a conventional non-volatile memory, and FIG. 3 is a cross-sectional view taken along the line X-Y in FIG.
Claims (1)
配列形成される各メモリセルを区画する島状の分
離領域と、 上記半導体基板から絶縁され隣接する２つの上
記分離領域間に亘つて形成され所定の電荷を蓄積
する浮遊ゲート電極と、 この浮遊ゲート電極から絶縁されると共に浮遊
ゲート電極に沿つて形成され上記浮遊ゲート電極
に所定の電界を与える制御ゲート電極と、 を備えた不揮発性メモリに於いて、 上記分離領域に重畳する上記浮遊ゲート電極及
び制御ゲート電極が上記分離領域に沿つて突出せ
しめられたことを特徴とする不揮発性メモリ。 (2) 上記浮遊ゲート電極及び制御ゲート電極の
突出部のサイズに依つて上記浮遊ゲート電極と上
記半導体基板との間、或いは上記制御ゲート電極
と上記浮遊ゲート電極との間の容量が設定される
ことを特徴とする請求項第１項記載の不揮発性メ
モリ。[Claims for Utility Model Registration] (1) An island-shaped isolation region for partitioning each memory cell arranged and formed at regular intervals on one main surface of a semiconductor substrate, and two adjacent regions insulated from the semiconductor substrate. a floating gate electrode formed between the two isolation regions and accumulating a predetermined charge; and a control gate insulated from the floating gate electrode and formed along the floating gate electrode to apply a predetermined electric field to the floating gate electrode. A nonvolatile memory comprising: an electrode, wherein the floating gate electrode and the control gate electrode that overlap the isolation region are made to protrude along the isolation region. (2) The capacitance between the floating gate electrode and the semiconductor substrate or between the control gate electrode and the floating gate electrode is set depending on the size of the protrusion of the floating gate electrode and the control gate electrode. The nonvolatile memory according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989131166U JPH0369256U (en) | 1989-11-10 | 1989-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989131166U JPH0369256U (en) | 1989-11-10 | 1989-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0369256U true JPH0369256U (en) | 1991-07-09 |
Family
ID=31678689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989131166U Pending JPH0369256U (en) | 1989-11-10 | 1989-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0369256U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63150971A (en) * | 1986-12-13 | 1988-06-23 | Nec Corp | Nonvolatile memory |
-
1989
- 1989-11-10 JP JP1989131166U patent/JPH0369256U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63150971A (en) * | 1986-12-13 | 1988-06-23 | Nec Corp | Nonvolatile memory |
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