GB1460992A - Integrated semiconductor arrangements - Google Patents

Integrated semiconductor arrangements

Info

Publication number
GB1460992A
GB1460992A GB2223974A GB2223974A GB1460992A GB 1460992 A GB1460992 A GB 1460992A GB 2223974 A GB2223974 A GB 2223974A GB 2223974 A GB2223974 A GB 2223974A GB 1460992 A GB1460992 A GB 1460992A
Authority
GB
United Kingdom
Prior art keywords
electrodes
semi
array
conductor
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2223974A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1460992A publication Critical patent/GB1460992A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

1460992 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 17 May 1974 [29 June 1973] 22239/74 Heading H1K In an integrated semi-conductor array comprising at least one pair of spaced elongate semi-conductor surface regions 17/18, 19/20, preferably constituting source and drain regions of an MNOS memory array, first and second sets of elongate control electrodes are located at right angles to the regions 17-20 on an insulating fibre on the semi-conductor body, the electrodes of the two sets alternating with one another and being of different materials. Preferably one set 16a, 16b is made of As-doped polycrystalline Si while the other set 28a, 28b is made of Al, adjacent electrodes being mutually insulated by a layer of SiO 2 formed on the Si electrodes 16a, 16b. This arrangement permits a closer spacing of MNOS cells in a memory array than would be possible using only polycrystalline Si electrodes. A generally conventional process for the manufacture of an array in accordance with the invention is described. In the array shown a relatively thick oxide coating covers the semi-conductor body 11 except at areas T 11 -T 42 where thinner nitride-on-oxide films beneath the control electrode strips 16a, 16b, 28a, 28b define individual memory cells. Further cells may be similarly provided between source/drain strips 18 and 19.
GB2223974A 1973-06-29 1974-05-17 Integrated semiconductor arrangements Expired GB1460992A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US37522173A 1973-06-29 1973-06-29

Publications (1)

Publication Number Publication Date
GB1460992A true GB1460992A (en) 1977-01-06

Family

ID=23480005

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2223974A Expired GB1460992A (en) 1973-06-29 1974-05-17 Integrated semiconductor arrangements

Country Status (4)

Country Link
JP (1) JPS5024085A (en)
DE (2) DE2427271A1 (en)
FR (1) FR2235490B1 (en)
GB (1) GB1460992A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4451905A (en) * 1981-12-28 1984-05-29 Hughes Aircraft Company Electrically erasable programmable read-only memory cell having a single transistor
JPS60101797A (en) * 1983-11-07 1985-06-05 Hitachi Ltd Semiconductor storage circuit device
JP2006176327A (en) * 2004-12-24 2006-07-06 Toshiba Elevator Co Ltd Handrail device of passenger conveyor and operation stopping method in case of handle damage

Also Published As

Publication number Publication date
DE2427271A1 (en) 1975-01-16
DE2430801A1 (en) 1975-01-23
FR2235490B1 (en) 1976-06-25
JPS5024085A (en) 1975-03-14
FR2235490A1 (en) 1975-01-24

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee