DE2430801A1 - MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR MEMORY MATRIX - Google Patents

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BU 972 016

Monolithically integrated semiconductor memory matrix

The invention relates to a monolithically integrated semiconductor memory matrix, in which a semiconductor substrate has highly doped zone pairs running parallel to one another, which over this vertical metallization strips each have one Include capacitively controllable zone.

Semiconductor components that can be used for this purpose are, for. B. energy independent (non-volatile) field effect transistors with variable threshold values such as the so-called MNOS transistors, which insofar as storage are considered to be through the use of a double-layer insulator as a gate, charges at the interface between the insulator are stored, which change the threshold voltage of the semiconductor device such that the state of charge storage by applying a gate voltage to the semiconductor device

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ORIGINAL INSPECTED

is detectable; wherein the semiconductor component is switched to the conductive state _r when such charge is stored and is not switched when there is no charge storage.

Such charge storage in the insulator is based on different Conductivities in the insulating layers on the gate; it is held at the interface between these two insulating layers in such a way that after removal of the applied voltage this charge is retained because the charge densities in the two layers are nonlinear functions of the electric field strength represent.

In US Pat. No. 3,436,623 it is shown that when two gates lie one on top of the other, the gates parallel to the drain and source diffusion Both the gate capacitance and the drain capacitance of the semiconductor component are arranged in a field effect transistor let reduce.

In "IBM Technical Disclosure Bulletin" Volume 14, No. 4, September

1971, page 1234, becomes a charge coupled device shown, the electrodes of which are formed from polysilicon and aluminum.

In ¹¹ IBM Technical Disclosure Bulletin "Volume 15, Mr. 4, September

1972, pages 1163 and 1164 is a field effect transistor arrangement refer to the metal cable runs and polysilicon gates used.

None of these arrangements show an energy-independent storage matrix arrangement, which works with a variable threshold value in order to be able to achieve high packing densities.

The object of the invention is energy-independent, powered with a variable threshold semiconductor components,

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für. to provide a memory matrix which has a high packing density of the individual memory elements and which can be produced with the aid of the method for producing monolithically integrated semiconductor circuits. With arrangements of this type, a memory is to be provided which allows the use of high writing and reading speeds as well as high shifting speeds, so that corresponding requirements are largely taken into account . .., "/ -." ■■. '■ -:, -. ^: .. ■■ _ ■■ - ■ "-:., .., -. ■ -.-- ■■■ ■■ -.--.. ...

According to the invention, this object is achieved in that the metallization strips only separated from each other by a 1000 to 3000 Ä thick silicon dioxide layer, tightly packed next to each other, and that filled with a thin SiO. layer and an overlying Si-jt ^ layer, are elongated parallel to the pairs of zones extending window openings in under the Metallization routes, lying silicon oxide thicknesses, the respective capacitive control is effective.

With the aid of the arrangement according to the invention, there is thus the possibility of to achieve a maximum packing density, with the required parallel lines on the semiconductor surface are closer to each other than corresponds to the optical resolution, to make these cable runs.

In an advantageous development of the invention it is provided that the metallization strips are made alternately from polysilicon and aluminum exist. The polysilicon metallization strips are included advantageously surrounded by the silicon dioxide layer apart from their respective support on the silicon nitride layer. These measures allow a uniform insulating layer to be formed on the surface of the semiconductor during manufacture on which a first set of metallization strips are formed, each in relatively thin layers are covered with an insulating material, so that subsequently a second set of metallization strips can be applied,

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-A-

which is inserted between this first sentence. In this way, there are no difficulties that are optimal for! To master packing densities required extremely small distances in the processes used.

In an advantageous development of the invention it is provided that the distance between adjacent window openings three times is as great as the total thickness of the insulation layers within these window openings.

When designed as MNOS field effect transistors, it is more advantageous Further development of the invention provides that the highly doped zone pairs in the form of source and drain diffusions as Bit lines and the metallization strips in the form of gate electrodes with feed strips as word lines of a memory matrix to serve.

With the aid of the arrangement according to the invention, memory arrangements can be created provide with high packing densities, which meet all the requirements placed on it with reliable operation.

Further advantages and features of the invention emerge from the following descriptions of exemplary embodiments on the basis of FIG drawings listed below and from the claims.

Show it:

1 shows a plan view of the detail of a matrix arrangement according to the invention,

FIG. 2 shows a section of the section shown in FIG Arrangement along lines 2-2,

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Fig. 3 is a partial cross section of the type

order in Fig. 1 along lines 3-3,

4 shows an enlarged section in the arrangement

1 to illustrate a manufacturing step of the arrangement shown in FIG. 1,

Fig. 5 is a schematic circuit diagram of the inven

appropriate matrix, with the necessary peripheral circuits,

Fig. 6 timing charts for explaining the operation

way of the circuit arrangement according to the invention,

Fig. 7 is a schematic circuit diagram of a white

Direct embodiment of the matrix arrangement according to the invention.

In the in FIGS. 1 to 3, finds a monocritical Semiconductor 10 use such. B. N-type silicon, which carries a * »P-conductive epitaxial layer 11, which is preferably has a resistivity of about 2 ohm-cm.

After the upper surface 12, the layer 11, has been appropriately cleaned, a silicon dioxide layer (not shown here) with a thickness of about 5000 S is applied to it. This layer can be produced by what is known as a thermal growth process, in which the semiconductor is ^{heated to approximately 1000 °} C. in a hydrogen atmosphere which contains a small proportion of oxygen.

After applying the silicon dioxide layer and attaching a Photoresist layer on this layer becomes one not shown here Photoresist mask for use over the semiconductor surface brought and the whole of a light exposure

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exposed to well-known methods to make elongated window openings therein to attach, so that a series of stretched bit lines 17, 18, 19 and 20 by appropriate diffusion in the Epitaxial layer 11 are formed. Subsequent to the diffusion these N-type bit lines 17, 18, 19 and 20 are these lines with a layer 13 consisting of silicon dioxide with approximately 5000 8 thick coated. This silica layer 13 can be formed at the same time as the so-called drive-in oxidation, which is similar to the thermal process described above Growing process is. After the silicon dioxide layer 13 has been formed, a coating of photoresist material is again applied to the elongated gate channels through the silicon dioxide layer 13, namely between the diffused bit lines 17, 18, 19 and 20, and so the top surface 12 of the semiconductor 10 to expose between the bit lines in their entire length. The respective area of the layer 13, the one above the bit lines and is located between the bit lines 18 and 19 remains unaffected by this process step. Subsequently to the formation of these channels, the upper surface 12 of the semiconductor 10 is again carefully cleaned and then a Layer 14 consisting of silicon dioxide approximately 20 8 thick in the channel areas of the surface 12 is formed. These Layer can be thicker, e.g. B. 100 S, where a suitable thermal growth process is also used again for their formation will.

Following the application of the silicon dioxide layer 14, a silicon nitride layer 15 with a thickness between about 250 and 1000 8 is applied to the layer 14. A special method to form such a silicon nitride layer consists in a known manner in that in a corresponding process silane and Ammonia gas mixed, and with the help of hydrogen as a carrier gas are introduced into a chamber, which the silicon body at a Temperature of about 800 ° C. At this temperature, a reaction occurs which leads to the formation of the silicon nitride layer 15 on the silicon dioxide layer 14 leads.

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Following the formation of the silicon nitride layer 15, a polycrystalline silicon layer approximately 8000 Å thick is grown on the surface of the layer 15. This polycrystalline silicon layer can be formed by placing the workpiece in a ^{chamber heated to about 800 °} C., and then introducing silicon with the aid of a hydrogen carrier gas. The layer is grown in the presence of a suitable dopant, preferably arsenic. As an alternative, the layer can also subsequently be doped. These dopants are necessary in order to reduce the specific resistance of the polycrystalline silicon layer and to make this layer highly conductive. The silicon nitride layer 15 below serves as a barrier to prevent doping particles from penetrating into the layer below.

A photoresist mask is then applied over the surface of the polycrystalline silicon layer in order to use known methods window openings 22 elongated by exposure and development, as shown in FIG. 4, to be introduced therein, wherein Lines 21a and 21b of the photoresist between the window openings 22 are retained. The underlying polycrystalline The silicon layer is now etched over the window openings in such a way that lines 16a and 16b separated from one another provided herein. As in FIGS. 1, 2 and 3, these lines 16a and 16b are unidirectional arranged extending perpendicular to the diffused bit / sense lines 17, 18, 19 and 20, which in turn previously diffused into the underlying semiconductor body 10 have been. At the present time you can using the existing process techniques known so far neither the window openings 22 nor the photoresist lines 21a and 21a 21b due to optical, chemical and mechanical limitations can be reliably manufactured with dimensions smaller than 20,000 A *.

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The optical and mechanical constraints that apply when deploying of the lines 16a and 16b predominate are primarily Line can be traced back to projection and printing processes for the production of these lines.

In addition to the problem of projection and print resolution, now Furthermore, the nature of the chemical etching process itself must be taken into account. Since that is to remove the unnecessary Etchants serving areas of the polycrystalline silicon layer only through the overlaid photoresist layer 21 in FIG its effect is hindered, the layer areas exposed by window openings 22 can be attacked and unhindered be eroded. However, if the etchant passes through a window opening 22, the polycrystalline silicon layer is in all of them Directions attacked with equal effect. In this way, the polycrystalline silicon layer is not just directly under the Window opening 22 etched away, but also somewhat laterally Direction by, as it were, undercut the photorisist lines 21a and 21b. The one emerging from the illustration according to FIG Undercut is approximately equal to the distance d, which corresponds to the thickness of the polycrystalline silicon layer.

The lines 16a and 16b etched out in this way are then so after the etching it is narrower than the overlying photorisist lines 21a and 21b, since the amount of polyrystalline silicon etched away is greater than the width of the window opening 22 corresponds. For this reason, it is necessary that the width of the photoresist lines 21a and 21b is not made smaller than about five times the thickness of the layer to be etched away.

Common FETs typically have gate electrodes with regard to current and voltage properties thicknesses between 8000 A * and 12000 R. For this example, where the polycrystalline silicon layer to be etched has a thickness of about 8000 R, there is a difference between

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permanent photorisist lines of also 8000 8. From this Basically, the width of the photoresist lines 21a and 21b should not be less than about 40,000 8. A system resolution of about 20,000 & poses no problem with the width of these lines If, however, the system resolution with regard to the width of the windows 22 becomes critical, then it is closed under all circumstances take into account that the distance between the photorisist lines 21a and 21b cannot be less than about 20,000 8 with respect to one another.

Assuming that the window openings 22 are only 20,000 A * are wide, then the total cell width, if nothing else, would be about 60,000 8 for each line 16a and 16b. Of this total cell width, only the Areas T21 and T41 under the respective line 16a and 16b active in the current conduction between the diffusion zones 17 and Be 18. But that means the active cell width is only approx 24,000 S. The remaining 36,000 8 require a space, which contributes to the reduction of the storage density. Of course, these lines 16a and 16b also define additional cells T22 and T42 between diffusion zones 19 and 20.

Once the lines 16a and 16b are defined, the remaining photoresist is removed and lines 16a and 16b are further treated by any of the known processes, so that a suitable insulator 24, such as. B. silicon dioxide with a thickness of preferably 1000 8 to 3000 8 applied thereon will. If the lines 16a and 16b have this insulation layer 24, then an aluminum layer approximately 8000 8 thick is applied over the entire surface area of the pattern. This layer is then etched as described above to produce lines 28a and 28b. The line 28a abuts to line 16a and line 28b is between and abuts lines 16a and 16b. These lines 28a and 28b now put additional cells TIl, T31, Tl2 and T32 in the previously

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unused areas ready, the lines 16a and 16b are adjacent. It follows that in the invention Pattern contains twice as many cells in the same area as has previously been the case.

Fig. 5 shows schematically the pattern of the arrangement shown in Fig. 1, in the form of a word-organized energy-independent Storage system that can be used either as an electronically changeable read-only storage system, or as a large random access memory. The arrangement shown here consists of four words, each of which contains two bits.

For the purpose of explaining the invention and the preferred embodiment, it is assumed that the energy-independent variable threshold semiconductor memory elements TIl, T12, T21, T22, T31, T32, T41 and T42 are all designed for N-channel operation and have an initial threshold voltage of 6 volts when there is no charge on the dielectric interface is stored, and have a threshold voltage of about 1 volt when this boundary layer has a charge. It understands It goes without saying that the arrangement can have any number of word lines with any number of bits contained therein may have, even if the above-specified limitation is present in the exemplary embodiment described.

Each word line 28a, 16a, 28b and 16b is coupled to the gates of the two transistors, each of which has a bit of the 2-bit word stores. The transistors TIl and T12 apply to the word line 28a. The word line 16a are the transistors Assigned to T21 and T22. Transistors T31 and T32 are for word line 28b and transistors T41 and T42 provided for the word line 16b. For purposes of illustration, is the energy independent variable threshold property each member indicated by the dashed line between gate and substrate for each component.

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Each word line is via a correspondingly assigned word line selection transistor coupled to an associated driver, which is used to optionally provide suitable voltages. So the word line 28a is through a word line select transistor 43 coupled to a word driver 44. Similarly, word line 28b is via a word line select transistor 45 with the same word line driver 44 coupled. Word lines 16a and 16b are above corresponding associated word line selection transistors 46 and 47 with a second word line driver 48 coupled. All of these word line drivers are provided with decoding circuits 49 and 50, respectively coupled, in turn with an address register, not shown are connected that have a set of address signals the lines A, B, C and D.

All word line select transistors 43, 45, 46 and 47 are arranged so that their respective gates are coupled to the output of one of a pair of OR gates 51 and 52. So are the gates of transistors 43 and 46 with output 53 of the first OR gate 51 coupled, and the gates of the transistors 45 and 47 with the output 54 of the second OR gate 52. The OR gates 51 and 52 have an input 55 and 56 coupled to bias source 60 and an input 57 and 58 coupled to line D. is on which the last significant bit of the set is supplied Address signals occurs. One of the OR gates, e.g. B. OR gate 51, has an inverter between the OR gate input 57 and the address line D is located.

As already mentioned, all memory cells have a matrix one energy-independent variable threshold transistor each. The first set of memory cells, namely the transistors TIl and Tl2, are coupled to the word line 28a, by connecting this word line 28a to the gate of these transistors connected. The second set of equal tran-

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Transistors T2l and T22 are coupled to word line 16a in the same way. Transistors T31 and T32 are over their gates to word lines 28b, whereas transistors T41 and T42 are coupled to word lines 16b via their gates are.

As can be seen from the illustrations according to FIG. 1 to FIG. 3, / are for all transistors TIl, T21, T31 and T41 between the diffused lines 17 and 18 are formed which serve as sources and drains for each device therebetween. These diffused in Lines 17 and 18 also serve as bit sense lines for the matrix and are at their respective ends with a common bit line driver and sense amplifier 59 connected. Likewise, the diffused lines 19 and 20 serve as bit sense lines and at the same time as Source and drain diffusions for the transistors T12, T22, T32 and T42. These bit / sense lines 19 and 20 are also included one end connected to the bit line driver and sense amplifiers 59. The substrates of the transistors are each connected to a conventional voltage supply 62, the if necessary, a suitable DC voltage pulse output to the Substrates guaranteed.

In order to describe the operation of the memory matrix according to the invention as shown in FIG. 5, reference is also made to FIG Referring to the timing diagrams of Figure 6, it is assumed that, for purposes of illustration, the low threshold condition, d. i.e., the state of charge of an energy-independent transistor is a binary zero and the high threshold state, d. H. , the uncharged state of an energy-independent transistor in matrix represents a binary one. Initially everyone is The word line of the matrix as shown in FIG. 5 is erased so that the dielectric interface of each transistor connected to the erased line is charged and each transistor has a low threshold voltage. After deletion each word line, can be selected components

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write on the word line, d. i.e., they can be in the high voltage state be discharged. Each component can then be read out non-destructively to determine its respective state to investigate.

To erase a specific word line of a matrix, e.g. B. the word line 28a, appropriate signals on the address lines A, B, C and D received. Lines A, B and C make the decoder circuits 49 and 50 respond, so that this in turn turns on the drivers 44 and 48. However, it should be taken into account that due to the word line selection transistors 43, 46, 45 and 47 not all word lines are brought to erase voltages. Instead, only one only special word line brought to the erase voltages. Is so assumed, e.g. B. that the word line 28 is that which is to be erased in order to then be written then the sequence of events listed below must take place.

At the time TO should be on line D, d. i.e., on the least significant bit line, a level of 0 volts may occur. This means that the input 58 of the OR gate 52 also 0 volts, however, under the action of the inverter 61, the input 57 of the OR gate 51 has a positive level, so that whose output 53 is also positive, as shown by curve 71 indicated in FIG. 6. The voltage level of the bit D is preferable low, d. H. about 1 volt, but the output of the OR gates must be large enough to power transistors 43, 45, 46 and 47 to be able to switch to the on-state. The voltage shown here is +20 volts. This is the least at time Tl significant bit D positive, and the output 54 of the OR gate 52 goes high to +20 volts as indicated by pulse 73. At the same time as time Tl, a small 1 volt voltage pulse ' 72 from the voltage source 60 to the inputs 55 and 56 of the OR gates 51 and 52, respectively, so that the output

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53 of OR gate 51 remains at its high positive output level. The output levels of the OR gates 51 and 52 are now positive as indicated by curves 71 and 73. These positive voltages at the output of the two OR gates 51 and 52 become the gates of the word line selection selectors 43, 45, 46 and 47 are supplied so that all of these transistors become on-state. Since the word drivers 44 and 48 are also in the Get on-state and thus +20 volts to the sources of the word line selection transistors 43, 45, 46 and 47 as through the pulses 74 and 75 indicated are applied to all word lines. 28a, 16a, 28b and 16b are each supplied with a positive pulse. The 20 volt pulse applied to word line 28a is indicated as pulse 76 and that of all other word lines 20 volt pulse supplied is denoted by pulse 77. By feeding this voltage becomes the parasitic capacitance of each word line charged to + 20 volts each. Simultaneously, the bit drive conductor 54 and the substrate driver 62 turn on so that all bit lines 17, 18, 19 and 20 and the substrates of each component in the matrix arrangement to + 20.VoIt as by the Pulses 78, 79, 80, 81 and 82 indicated are brought. Both pulse 72 from source 60 and pulse 74 from word driver 44 terminated then the output line picks up 53 of the OR gate 51 to ground potential or 0 volts, whereas line 54 remains at its high voltage level; the transistors 43 and 46 switch off, so that the word lines 28a and 16a also remain at a high voltage level. However, since the output 54 of the OR gate 52 remains in a high positive voltage condition, the Transistors 45 and 47 in their on-state. Since the output driver 48 continues to send a large positive pulse through transistor 47 makes it effective, the word line 16b remains at a high positive voltage level. However, since the transistor 45 keeps the word driver 44, which is now at ground potential, connected to the word line 28b, the parasitic capacitance becomes discharged on line 28b, and line 28b is brought to ground potential via driver 44.

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At time T3, circuit 60 again applies a positive Pulse 83 to inputs 55 and 56 of OR gates 51 and 52. This pulse 83 in turn leaves the output 53 of the OR gate 51 as indicated by pulse 84, increase to a voltage of + 20 volts *

At time T4, word driver 48 is switched off and the Pulse 75 ended, the parasitic capacitances on the the remaining word lines 28a, 16a and 16b are also discharged to ground will. At time T5, all bit lines and the substrate assume ground potential, as indicated by the termination of the pulses 78, 79, 80, 81 and 82 is indicated. This means that only the transistors T31 and T32, which are coupled to the word line 28b are held in a binary zero condition.

Should a binary one, z. B. are written into transistor T31, then the word driver 44 is switched on, and pulse 85 is applied to the sources of transistors 43 and 45, and bit lines 19 and 20 become also raised to + 20 volts (pulses 89 and 90). In addition at this point in time only the output 54 of the OR gate 52 is positive only the transistors 45 and 47 are switched on, and word line 28b has a positive pulse 86, which is supplied by the word driver 44. This has the consequence that the gate of the transistors T3i and T32, the voltage of the word line 28b red. Under these voltage conditions only removes the charge from the charge storage medium in the case of transistor T31 in order to put it in the high threshold state. A binary one is thus set here. The transistor T32, whose source and drain, i. H. Bit lines 19 and 20, are at a high positive voltage and its gate, which is connected to the line 28b, also has a high potential the state of charge remains unchanged; this The memory element is therefore not written into.

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The remaining storage elements in this matrix, however, are also not registered, as z. B. the transistors Tl2, T22 and T42 with their bit / sense lines 19 and 20 with reference to their respective gates are at a high positive potential, or B. the transistors TIl, -T21 and T4l, with their gates Sources and drains are each brought to 0 volts.

After a sufficient period of time to ensure that the selected memory members have been written are, d. H. at time T7, the word driver 44 is also switched off again in order to terminate the pulse 85. Since the Transistor 45 remains in the conductive condition, the word line 28b is at the same time to ground potential by the action of Word driver 44 brought. At time T8, bit lines 19 and 20 also come to ground potential.

After the selected transistor, namely transistor T31, is written has been, d. H. is brought into its high threshold state, the matrix can then be non-destructive read out. For the purpose of illustration, it is assumed that the word line 28b is to be read out, with the State of transistors T31 and T32 is to be determined by a read cycle that is initiated at time T9. This Read cycle begins by applying appropriate +5 volt read signal pulses 91 and 92 on bit lines 17 and 19. At time T10 turn on the word decoder 49 and the word line driver 44 to apply a + 5 volt pulse 88 to the sources of the To transmit word selection transistors 43 and 45. However, since the output 53 of the OR gate 51 remains at ground potential, remains transistor 43 is also turned off. The output 54 of the OR gate 52 is at + 20 volts, as indicated by the pulse 73, and transistors 45 and 47 remain in their on-states. So that the output of the word driver 44 is via transistor 45, as indicated by pulse 93, is transferred to word line 28b. Although the transistor 47 is also affected by the voltage

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voltage at the output 54 of the OR gate 52 is switched on, the word line 16b remains at ground potential, since the word driver 48 also remains at earth potential. The potential on the word line 28b rises, so that the transistors T31 and T32 in the on-state then there will be a 5 volt pulse 94 on the bit line 20 appear. This indicates that transistor T.32 was in the low threshold state and was a binary one Zero saved. The bit line 18 remains at ground potential to indicate that transistor T31 is in the high threshold state was and stored a binary one.

It should be noted that this +5 volt pulse 93, on of word line 28b is lower than the threshold voltage of the memory elements in the high threshold state and so on is not sufficient to bring the transistor T31 into the on-state. However, it is completely sufficient, memory links in the slightest To switch the threshold state to the on state, d. H. Transistor T32.

This +5 volt pulse is also insufficient for any change bring about in the state of charge of the transistors T31 or T32.

If the word line 28b is thus biased to -5 volts, then switch only the stored storage elements connected to it are in the on-state.

Since the transistors TIl, Tl2, T21, T22, T31, T32, T41 and T42 are all energy independent and represent variable threshold value elements, and since the voltage of 5 volts applied to the word line is insufficient to affect the state of charge of any of these elements each storage element has its original state of charge after the end of the pulse 93. Since the decoder 48 has not been turned on, the word lines 16a and 16b remain at ground potential, and the

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Transistors coupled to it are in no way created by applying influenced by any voltages on the bit lines.

At the point in time TIl, the word driver 44 reaches ground potential, thus terminating the word driver pulse 92. This has the consequence that the word line voltage pulse 93 is also at ground potential is brought, so that the transistor T32 is switched off, although the bit line 19 is at a +5 volt level remains.

The described driver is unique in comparison with previously known, similar arrangements, since when using the invention The system's improved packing density of the memory matrix also affects the peripheral driver circuits can expand. It should of course be perfectly clear that far more than just four word lines, if necessary Can find application. Using the arrangement according to the invention, it is now possible, specifically in energy-independent to avoid variable threshold memory arrangements that the minimum word line spacing is limited by the word driver spacing. If necessary for a given matrix configuration, the metallic lines can be opened one side of the matrix, and place the polycrystalline silicon lines on the other side of the matrix so that the corresponding The decoder and driver come to lie on opposite side surfaces of the matrix substrate.

The matrix arrangement shown in FIG. 7 has twice the packing density than that shown in FIG. The matrix arrangement according to FIG. 7 likewise consists of a plurality of word lines 101, 102, 10 3 and 104, which are all connected to the gates of the energy-independent variable threshold value storage elements 100. This matrix arrangement uses the same decoder-driver circuitry and the least

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Most significant bit arrangement such as is shown in FIG. 5, in which a decoder 105 is coupled to a driver 106 is, which in turn via the two word line selection transistors 107 and 108 is fed to word lines 101 and 103, respectively. Similarly, a second decoder 110 is with a Driver 111 coupled and across two word line select transistors 112 and 113 also to word lines 102 and 104. A substrate driver 119 is with the substrates of all of the transistors coupled in the matrix. In the same way, the gates of the word line selection transistors 107, 108, 112 and 113 are connected to the Outputs of the OR gates 114 and 115 coupled, in turn their inputs are connected to a voltage source 116. The OR gate 114 is via an inverter 117 with the least significant bit line D coupled to an appropriate Memory address register, which is not shown here; whereas the OR gate 115 is coupled directly to this bit is. Each matrix transistor lies between a pair of bit lines. These bit lines 120, 121, 122, 123, 124 and 125 are all in turn connected to a bit line driver 126. The alternating bit lines 121, 123 and 125 are via suitable Switch 127 fed to either the bit line driver 126 or to the appropriate sense amplifier 129, 130 and 131 can be connected.

To come back to Fig. 1, it can be seen that additional Transistors between the word lines 18 and 19 can be switched in by only the thick oxide layer 13 between them is removed accordingly. If this is done, there are three transistors in the matrix arrangement of the Fig. 1 is available along each word line. So can in expanding In accordance with the invention, an additional transistor can be provided between each bit line pair, i. H. between the bit lines 18 and 19 where nothing of the kind existed before. The means for reading and writing such transistors serving as intermediate storage elements are described elsewhere.

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It is basically stated here that an energy-independent variable threshold value memory arrangement such as e.g. B. in Fig. 7 described, just a single sense amplifier for reading of any two adjacent rows of the transistors in the matrix together with a corresponding substrate bias, so as to selectively control read, write and erase operations with a single voltage polarity so that it does not it is necessary to apply both positive and negative voltages in the form of corresponding pulses to the gates of the transistors. The matrix arrangement of FIG. 7 can adopt this reading scheme operate that only has a sense amplifier, i. H. the Amplifiers 129, 130 and 131 are required for each two adjacent rows of transistors, so that the transistors are in a semiconductor body can be formed; a single common bit line can therefore each have two adjacent rows of transistors supply.

This can then bring about a further doubling of the packing density.

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Claims (7)

PATENT CLAIMS Monolithically integrated semiconductor memory matrix, in which a semiconductor substrate has highly doped pairs of zones running parallel to one another which each enclose a capacitively controllable zone via metallization strips running perpendicular thereto, characterized in that the metallization strips (16a, 28b, 16b, 28a) only have a 1000 to 3000 A * thick silicon dioxide layer (24) are separated from each other, closely packed next to each other, and that _{filled with a thin SiO2 layer (14) and overlying Si 3} N ₄ layer (15) are elongated parallel to the pairs of zones (17, 18) extending window openings (.22) in silicon oxide thick film (13) lying under the metallization strips (16a, 28b, 16b, 18a) the respective capacitive control is effective. 2. Arrangement according to claim 1, characterized in that that the metallization strips (16a, 28b, 16b, 28a) consist alternately of polysilicon and aluminum. 3. Arrangement according to claim 1 and / or claim 2, characterized characterized in that the polysilicon metallization strips (16a, 16b) of their respective "- ■ support on the silicon nitride layer (15) are surrounded by the silicon dioxide layer (24). 4. Arrangement according to claims 1 to 3, characterized in that that the distance between adjacent window openings (22) is three times as great like the total thickness of the insulation layers (14, 15) within these window openings (22). BU 972 016 40988A / 1318 5. Arrangement at least according to claim 4, characterized in that the lowermost insulation layer (14) in the window opening (22) from a 20 to 100 8 thick silicon dioxide layer and the overlying insulation layer from a 250 to 1000 8 thick silicon nitride layer consists. 6. Arrangement according to claims 1 to 5, characterized in that the highly doped zone pairs (18, 19) in the form of source and drain diffusions as bit lines, and the metallization strips (16a, 28b, 16b, 28a) in the form of gate electrodes with feed strips serve as word lines of the memory matrix. 7. Arrangement according to claim 6, characterized in that the distance between the channels of the field effect transistors so arranged in a column is less than 3000 8. BU 972 016 A 0 9 8 8 U 1 1 3 1 8