GB1409095A - Methods of manufacturing semiconductor devices - Google Patents

Methods of manufacturing semiconductor devices

Info

Publication number
GB1409095A
GB1409095A GB5395172A GB5395172A GB1409095A GB 1409095 A GB1409095 A GB 1409095A GB 5395172 A GB5395172 A GB 5395172A GB 5395172 A GB5395172 A GB 5395172A GB 1409095 A GB1409095 A GB 1409095A
Authority
GB
United Kingdom
Prior art keywords
layer
source
semi
sunken
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5395172A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1409095A publication Critical patent/GB1409095A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1055Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices of the so-called bucket brigade type
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/12Regulating voltage or current wherein the variable actually regulated by the final control device is ac
    • G05F1/24Regulating voltage or current wherein the variable actually regulated by the final control device is ac using bucking or boosting transformers as final control devices
    • G05F1/247Regulating voltage or current wherein the variable actually regulated by the final control device is ac using bucking or boosting transformers as final control devices with motor in control circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

1409095 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 22 Nov 1972 [25 Nov 1971] 53951/72 Heading H1K In the manufacture of a semi-conductor device involving the introduction of impurities into surface zones of a semi-conductor body to provide at least source and drain regions of an IGFET, the semi-conductor surface is subsequently oxidized through a mask to form a sunken insulating oxide layer covering at least part of at least one surface zone, after which part of the sunken layer above a surface zone is partly or wholly removed, a thinner insulating layer being retained or reformed at the same place. As shown, a surface of an N-type silicon body 1 (which may be an epitaxial layer on a low-resistivity substrate) is masked, e.g. by silicon nitride, and thick sunken oxide portions 10 are grown in exposed areas. Using a fresh mask, source and drain regions 2, 3 and a capacitor electrode region 11 are formed by diffusion or boron-ion implantation; then the exposed surface is oxidized to form a sunken oxide layer 7. The mask is removed, and portions of the layer 7 are removed and thin oxide layers such as 12 are grown in their place; gate insulation 6 may be simultaneously provided. Alternatively the layer 7 may be selectively thinned. Thin oxide layers above source and drain regions 2, 3 and part of electrode region 11 are removed, and gate, source and drain electrodes 5, 8, 9, and capacitor counter-electrode 13 and contact 14 are formed by the vapourdeposition or sputtering of aluminium or molybdenum. A further embodiment (Figs. 6a, 6b, not shown) comprises an integrated capacitor memory of the kind described in Specification 1,273,181, in which each of a series of doped surface zones (61) forms the drain region of one device and the source region of the succeeding device. A sunken oxide layer (65) over the surface zones is reduced in thickness except above the source regions adjacent the channel regions (62). Each insulated gate electrode (64) is connected to a conductive layer 71 on the thin oxide (70) above the drain region. Silicon carbide may be the semi-conductor material, and the conductive layers may comprise polycrystalline silicon or successive layers of, e.g., titanium, platinum and gold.
GB5395172A 1971-11-25 1972-11-22 Methods of manufacturing semiconductor devices Expired GB1409095A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7116182A NL7116182A (en) 1971-11-25 1971-11-25

Publications (1)

Publication Number Publication Date
GB1409095A true GB1409095A (en) 1975-10-08

Family

ID=19814543

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5395172A Expired GB1409095A (en) 1971-11-25 1972-11-22 Methods of manufacturing semiconductor devices

Country Status (11)

Country Link
JP (1) JPS4861078A (en)
AR (1) AR194520A1 (en)
AT (1) ATA994272A (en)
AU (1) AU469642B2 (en)
CA (1) CA970077A (en)
DE (1) DE2254821A1 (en)
ES (1) ES408908A1 (en)
FR (1) FR2161003B1 (en)
GB (1) GB1409095A (en)
IT (1) IT975824B (en)
NL (1) NL7116182A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142199A (en) * 1977-06-24 1979-02-27 International Business Machines Corporation Bucket brigade device and process
JPS5534493A (en) * 1978-08-31 1980-03-11 Ibm Bucket brigade cell

Also Published As

Publication number Publication date
IT975824B (en) 1974-08-10
FR2161003A1 (en) 1973-07-06
AR194520A1 (en) 1973-07-23
ATA994272A (en) 1975-08-15
JPS4861078A (en) 1973-08-27
FR2161003B1 (en) 1978-02-03
ES408908A1 (en) 1975-10-16
DE2254821A1 (en) 1973-05-30
NL7116182A (en) 1973-05-29
AU469642B2 (en) 1976-02-19
AU4908072A (en) 1974-05-23
CA970077A (en) 1975-06-24

Similar Documents

Publication Publication Date Title
US3653978A (en) Method of making semiconductor devices
US4763177A (en) Read only memory with improved channel length isolation and method of forming
US4314857A (en) Method of making integrated CMOS and CTD by selective implantation
US5472888A (en) Depletion mode power MOSFET with refractory gate and method of making same
US4975384A (en) Erasable electrically programmable read only memory cell using trench edge tunnelling
GB1425986A (en) Semiconductor devices comprising insulated-gate- field-effect transistors
US4975383A (en) Method for making an electrically erasable programmable read only memory cell having a three dimensional floating gate
GB1408180A (en) Semiconductor device manufacture
US4229756A (en) Ultra high speed complementary MOS device
US4553314A (en) Method for making a semiconductor device
JPS57109367A (en) Semiconductor memory device
US4228447A (en) Submicron channel length MOS inverter with depletion-mode load transistor
GB1228471A (en)
GB1376900A (en) Semiconductor devices
US3892609A (en) Production of mis integrated devices with high inversion voltage to threshold voltage ratios
GB1409095A (en) Methods of manufacturing semiconductor devices
US4216573A (en) Three mask process for making field effect transistors
US3968562A (en) Method of manufacturing a semiconductor device
US3969150A (en) Method of MOS transistor manufacture
EP0017934A2 (en) Method of manufacturing insulated-gate field-effect transistors
JPS5938738B2 (en) Integrated semiconductor device including MIS transistor and its manufacturing method
GB1595543A (en) Memory cell
KR930009592B1 (en) Method for manufacturing a semiconductor memory device
JPS6098666A (en) Semiconductor memory device
JPS62206874A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee