JPH0525251Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] This invention relates to thin film transistor arrays, and is used as a driver or switching circuit in various applications such as various printers, contact image sensors, and liquid crystal display devices. It can be widely used as such.

[Conventional technology]

Conventionally, thin film transistor TFTs include polycrystalline silicon TFTs, amorphous silicon TFTs,
CdSeTFT etc. were known. Thin film transistors that use amorphous semiconductors such as amorphous silicon as the semiconductor active layer, such as amorphous silicon TFTs, are widely used in various types of printers, contact type It is attracting attention as a device for drivers and switching circuits in image sensors, liquid crystal display devices, etc.

As a thin film transistor array in which a large number of such thin film transistors are arranged, for example, those shown in FIGS. 2 and 3 have been known. Figure 2 shows an equivalent circuit diagram of a thin film transistor array, where T _rn1 to _{T rno} are thin film transistors, and one thin film transistor block B _n is composed of n thin film transistors (n≧1). There is. And each thin film transistor
The source electrodes of T _rn1 ~ _{T rno} are connected to the source lines S ₁ ~
connected to S _o , and the drain electrode is connected to the drain line
Connected to D _n1 to D _no , respectively. The gate electrode is also connected to a gate line G _n common to all transistors in the block. Then, a thin film transistor block consisting of n thin film transistors as described above is defined as B _n , B _n+1 , B _n+2
... (B _n+2 ... is not shown), a plurality of them are provided to constitute a thin film transistor array.

When using such a thin film transistor array, for example, the source lines S ₁ to _{S o} are used as signal input terminals, the drain lines D _n1 to _{D no} are used as output terminals, and the gate line G _n is used as a control signal input terminal. It is something. Now, the control signal input terminal G _n ,
When _a control signal is applied to only G _n of _{G n +1 , G n+ 2 .} The signals applied to ~S _o are output as they are to output terminals D _n1 ~D _no to supply signals to the load.
At this time, since no signals are applied to the control signal input terminals G _n+1 and G _n+2 , the blocks B _n+1 and B _n+2
Since all the thin film transistors in the block are in the off state, the signals applied to the signal input terminals S 1 to _{S o} are output only to the output terminal of the block B _n , and the signals applied to the signal input terminals S ₁ to S o are output only to the output terminal of the block B n and the signals applied to the signal input terminals S 1 to S o are output to the output terminals of the block B n and other blocks B _n+1 and B _n+2. It is not output to the output terminal of ....

Also, when a signal is applied to the control signal input terminals G _n and G _n+1 and no signals are applied to the other terminals G _n+2 , G _n+3 ..., the output terminals D _n1 to D _n of block B n are applied. D _no
The signals from the signal input terminals S 1 to S o are output only to the output terminals D (n+ _{1 )1} to D _{(n+1) o of} block B n+1, and the signals from the other blocks B _n+2 and B No signal is output to the output terminal of _n+3 ....

In this way, the control signal input terminals G _n , G _n+1 ,
By controlling the signal applied to G _n+2 ..., the input signal applied to the signal input terminals S ₁ to _{S o} can be output to the output terminal of any thin film transistor block, and the load connected to that output terminal can be output. It is capable of supplying signals. (In the drawing, block B _n+2 ,
B _n+3 ... is omitted. ) FIG. 3 is a plan view showing the wiring pattern of the conventional thin film transistor array shown in the equivalent circuit of FIG. 2, and the same reference numerals as in FIG. 2 represent the same parts. In addition, in FIG. 3, only the thin film transistor blocks B _n and B _n+1 are shown, and other blocks are not shown, but in reality, there are many thin film transistor blocks B _n , B _n+1 ,
B _n+2 , B _n+3 . . . constitute a thin film transistor array.

In order to increase the packaging density, the wiring pattern of such a thin film transistor array is arranged diagonally as shown in the figure. That is, for the thin film transistor block B _n , the thin film transistors in the block B _n
T _rn1 ~ T _rno , with T _rn1 at the top left in the drawing,
T _rn2 is placed at the bottom right of T _rn1 , T _rn3 is placed at the bottom right of T _rn2 , and so _on.Trno is placed at the bottom right in the same manner.
A thin film transistor block B _n having such a wiring pattern and a plurality of thin film transistor blocks B _n+1 , B _n+2 , B _n+3 having the same wiring pattern
... are sequentially arranged on an insulating substrate (block B _n+2 ,
B _n+3 . . . is not shown) to constitute a thin film transistor array. In a thin film transistor array having such a configuration, in a boundary region between thin film transistor blocks, a drain line and a source line between two adjacent thin film transistors partially run parallel to each other. For example, thin film transistor block B _n and
In B _n+1 , the thin film transistor T _rno and
T _r(n+1)1 is adjacent to the block boundary area, and its drain line D _no and source line
Part of S ₁ runs parallel.

[Problem that the invention attempts to solve]

The conventional thin film transistor array described above has the following problems. One of them is that if there is a line-to-line short circuit in the parallel portion of the drain line and source line that are connected to two adjacent thin film transistors in the boundary area between thin film transistor blocks, a signal that should not be output is output. It may happen that it goes out to the terminal and is supplied to the load. For example, between the thin film transistor blocks B _n B _n+1 , the drain line D _no connected to the thin film transistor T _rno
And, since there is a part of the source line _S1 connected to the thin film transistor T _r(n+1)1 that runs parallel to it,
If there is a short circuit between the lines in this parallel portion, the source line S ₁ and the drain line D _no are always shorted, so the source line S ₁ is always shorted regardless of the operation of the thin film transistors T _rno and T _r(n+1)1. The signal input to the drain line was output to the drain line D _no , causing negative effects such as load malfunction. Therefore, it is necessary to inspect whether or not there is a short circuit between the lines as described above, which has the disadvantage of increasing the number of manufacturing steps.

Furthermore, when there is a parallel running portion as described above, there is a stray capacitance between the lines, and if the distance of the parallel running portion is long, the influence of this cannot be ignored. For example, if the parallel running portion between the drain line D _no and the source line S ₁ as described above is long, the line-to-line capacitance in the parallel running portion becomes large, and the drain line D _no and the source line S ₁
If the load connected to the drain line is a high-impedance load, there will be many negative effects similar to those of the line-to-line short circuit described above. There were flaws.

This idea was made to improve the above-mentioned conventional drawbacks, and it prevents short circuits between the drain line and source line connected to two adjacent thin film transistors in the boundary area between thin film transistor blocks. The purpose is to reduce the number of manufacturing steps by eliminating the need for inspection, reduce crosstalk by eliminating stray capacitance between drain lines and source lines, and improve the reliability of thin film transistor arrays.

[Means and actions for solving problems]

In order to achieve the above object, this invention uses a wiring pattern in which the drain line and source line connected to two adjacent thin film transistors in the boundary area between thin film transistor blocks do not run parallel to each other. Thus, line-to-line short circuits between the drain line and source line are eliminated, as well as line-to-line stray capacitance between the lines.

〔Example〕

Examples of this invention will be described below with reference to the drawings. FIG. 1 is a diagram showing one embodiment of this invention, and is a plan view showing a wiring pattern of a thin film transistor array formed on an insulating substrate. In addition, in Figure 1, the second
Components with the same reference numerals as those in the conventional example shown in FIG. 3 represent the same components.

In Figure 1, the thin film transistor block
B _n is n thin film transistors T _rn1 ~ (n≧1)
These n thin film transistors are diagonally arranged on an insulating substrate from _the top left to the bottom right of the drawing. That is, thin film transistor
T _rn1 is placed at the top left, and T _rn2 is placed at the bottom right of it.
Further, at the lower right of T _rn2 , T _rn3 is arranged in the same manner, and T _rno is arranged at the lower rightmost position. Next, thin film transistor block B _{n +1} placed adjacent to thin film transistor block B n is also composed of n thin film transistors T _r(n+1)1 to _{T r(n+1)o.} are arranged diagonally from the bottom left to the bottom right of the drawing. That is, the thin film transistor
Thin film transistor T _r(n+1)1 adjacent to T _rno is placed at the bottom right of the drawing, and T _r(n+1)2 ,
The upper right corner of T _r(n+1)2 is T _r(n+1)3 , and so on.
T _r(n+1)o is arranged at the upper rightmost position. Furthermore, the thin film transistor block B _n+2 arranged adjacent to the thin film transistor block B _n+1 is also composed of n thin film transistors T _r(n+2)1 to _{T r(n+2)o} (this Block B _n+2 is only partially shown)
Its arrangement is the same as that of the thin film transistor block _Bn . In this way, a plurality of blocks in which thin film transistors are arrayed diagonally from the upper left to the lower right of the drawing and blocks arrayed from the lower right to the upper right are alternately arranged adjacent to each other. . (Although only a part of the thin film transistor block is shown in the drawing, in reality, there are many blocks such as B _n+3 , B _n+4 , etc.) Furthermore, the above thin film transistor array is a conventional thin film transistor array. (The explanation is omitted.) When thin film transistors are arranged in this way, two adjacent thin film transistors (for example, T rno and T _rno
A wiring pattern is formed so that the drain lines and source lines connected to T _r(n+1)1 ) and these two thin film transistors are all axisymmetric with respect to the virtual boundary area between the thin film transistor blocks. . Therefore, the wiring pattern is formed so that the drain line and source line connected to the two adjacent thin film transistors do not run parallel to each other anywhere. For example, the drain line D _no connected to the thin film transistor T _rno and the source line S _{1 connected to the thin film transistor T r(n+1)1 ,} and the source line S _o connected to the thin film transistor T _rno and the thin film transistor T _r(n The drain line D _(n+1)1 connected to ₊₁ )1 is designed not to run parallel to it anywhere. Further, the relationship between thin film transistors T _r(n+1)o and T _r(n+2)1 is also the same as above.

[Effect of the invention]

As described above in the embodiments, this invention allows wiring patterns of two adjacent thin film transistors in the boundary region of thin film transistor blocks constituting a thin film transistor to be connected to drain lines and source lines connected to the two thin film transistors, respectively. , so that they do not run side by side at any location.

Therefore, there is no need to test for short circuits between the drain line and source line as described above (as there is no parallel running part as described above, short circuits between lines will not occur).
Furthermore, since the stray capacitance between the lines and the deterioration of the insulation properties are substantially eliminated, the problem of crosstalk based on these does not occur, and there are many effects such as improved reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a thin film transistor array showing one embodiment of this invention, FIG. 2 is an equivalent circuit diagram of a conventional thin film transistor array, and FIG. 3 is a plan view of a conventional thin film transistor array. B, B _n , B _n+1 , B _n+2 ..., ... thin film transistor block, Tr, T _rn1 ..., T _r(n+1)1 ..., ... thin film transistor, D, D _n1 ..., D _{(n +1)1} ..., ...drain line, S, S ₁ , S ₂ ...S _o ...source line,
G, G _n , G _n+1 ..., ... gate line.

Claims (1)

[Scope of utility model registration request] In a thin film transistor array in which a thin film transistor block is constituted by n (n≧1) thin film transistors and a drain line and a source line connected to each thin film transistor, and a plurality of these thin film transistor blocks are arranged on an insulating substrate, the thin film transistor block is In the boundary area between the thin film transistor blocks, two thin film transistors arranged adjacent to each other, and drain lines and source lines respectively connected to the thin film transistors, are line-symmetrically arranged with respect to the virtual boundary line between the thin film transistor blocks. A thin film transistor array characterized in that the drain line and the source line do not run parallel to each other anywhere by forming a wiring pattern on the thin film transistor array.