KR0153222B1 - Driving circuit of display device - Google Patents

Abstract

The driving circuit of the display device of the present invention is connected to each of a plurality of first signal lines and first signal lines arranged in parallel with each other, and is in an ON / OFF state between a first signal line and a second signal line corresponding to the first signal line. And a plurality of connection lines each having a first connection point between the control means for controlling the control and the control means and each having a second connection point between the corresponding second signal line and the first connection point. The distance between the connection point and the second connection point is the same.

Description

Drive circuit of display device

1 is a circuit diagram of a main part of a TFT active matrix liquid crystal display.

2 is a cross-sectional view showing a circuit board in the vicinity of the sampling gate.

3 is a plan view showing an embodiment of a wiring pattern of a driving circuit of a conventional display device.

4 is a plan view showing an embodiment of a wiring pattern of a driving circuit of a display device of the present invention.

5 is a plan view showing another embodiment of the wiring pattern of the drive circuit of the display device of the present invention.

6 is a plan view showing another application of the driving circuit of the display device of the present invention.

* Explanation of symbols for main parts of the drawings

100: substrate 105: gate driving circuit

106: data driving circuit 110: liquid crystal panel

111: parallel gate bus line 112: parallel data bus line

113: capacitance 114: TFT

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to driving circuits for use in display devices such as liquid crystal display devices.

1 shows a conventional active matrix liquid crystal display device using a thin film transistor (TFT). In this liquid crystal display device, a liquid crystal panel and a driving circuit are formed on one and the same substrate, so that the device can be reduced in size and weight, and is integrally integrated as a display unit. and completed component). Such a technique is disclosed in Japanese Patent Laid-Open No. 63-148928 and is widely known and widely adopted.

With reference to FIG. 1, the structure of this display apparatus is demonstrated.

The display device includes a substrate 100, a liquid crystal panel 110 formed on the substrate 100, and a gate driving circuit 105. On the liquid crystal panel 110, a plurality of parallel gate bus lines 111 and a plurality of parallel data bus lines 112 are formed. The gate driving circuit 105 is formed on one side of the liquid crystal panel 110 and is connected to each gate bus line 111. The data driving circuit 106 is formed on the other side of the liquid crystal display panel 110 and is connected to each data bus line 112. A pixel (picture element) is provided at the intersection of the gate bus line 111 and the data bus line 112. Each pixel is composed of liquid crystal capacitance and storage capacitance for the pixel. Both capacitances are referred to as capacitance 113. Each pixel is connected via a respective TFT 114 to a corresponding one of the gate bus lines 111 and a corresponding one of the data bus lines 112. The gate driving circuit 105 outputs a signal for controlling the ON / OFF state of the TFT 114 to the gate bus line 111. When the TFT 114 is turned on in response to this control signal, the data signals provided from the data driving circuit 106 onto the data bus line 112 are written to the capacitance 113 of the pixel to drive and control the liquid crystal. do.

The data drive circuit 106 includes a shift register 107 and a sampling gate 108. The sampling gate 108 is controlled by the output of the shift register 107. When the sampling gate 108 is in the ON state, the R, G, and B video signals are supplied to the outside through the video signal line 120 and input to the data bus line 112. In this way, the above-described data signal is supplied.

Referring to Figs. 2 and 3, the structure of the vicinity of the sampling gate 108 and a manufacturing method thereof will be described in detail.

2 shows a cross-sectional view of the periphery of the sampling gate 108. As shown in FIG. 2, a polycrystalline silicon layer formed on the glass substrate 100 is patterned with a lower electrode 122 as a semiconductor layer of the TFT constituting the sampling gate 108. (pattern). A gate insulating film 123 is then formed over this lower electrode 122. Then, a polycrystalline silicon layer consisting of an upper electrode 124a as a gate electrode of the TFT and an interconnection line 124b is formed and patterned. After the doping process, a first interlayer insulating film 125 is formed over all surfaces by ion implantation in a predetermined portion. In a predetermined portion, contact holes 301, 302 and 303 are opened. Then, the metal wiring 126a and the connection electrode 126b are formed by patterning. The second interlayer insulating film 127 is formed. As a result, a sampling pattern 108 and a wiring pattern in the vicinity thereof are formed on the glass substrate 100.

3 shows a wiring pattern for connecting each sampling gate 108 to the video signal line 120. The source electrodes of the plurality of sampling gates 108 having the structure shown in FIG. 2 are connected to the video signal line 120 via the connection electrode 126b of the metal wiring layer and the connection line 124b of the polycrystalline silicon layer. . The video signal line 120 is formed of a metal wiring layer and is connected to the connection line 124b through the contact hole 300. The connecting line 124b is connected to the connecting electrode 126b through the plurality of contact holes 301, and is connected to the source electrode of the TFT constituting the sampling gate 108 through the plurality of contact holes 302. have. The signal lines X1 to Xn from the shift register 107 as the upper electrode 124a are connected to the gate of the sampling gate 108. In this way, the ON / OFF state of the sampling gate 108 is controlled so that the video signal line 120 is connected to the data bus line 112 through the plurality of contact holes 303.

The lengths LL1 to LL3 of the connection wirings 124b from the connection points on the R, G, and B image signal lines 120 through the contact holes 300 to the connection points on the connection electrodes 126b through the contact holes 301 It can be seen from FIG. 3 that each sampling gate 108 is different from one another. When the connecting line 124b is formed using the polycrystalline silicon layer, the sheet resistance is increased and thus the difference in wiring resistance between each connecting line 124b is increased. Therefore, when the same video signal is supplied from the video signal line 120 while the sampling gate 108 is set to the ON state, the levels of the video signals supplied to the data bus line 112 are different. This causes a phenomenon in which the brightness is not uniform. This phenomenon is detected as streaks in the case of a monochrome display device, and the image quality deteriorates considerably.

In a point-sequential driving method in which a signal is held by the capacitance of the source bus line 112, the signal is recorded as a source bus line having a relatively large capacitance. In such a case, the above-described drawbacks appear as timing errors caused by variations in the time constant caused by the phenomenon of distortion of the signal waveform and the difference in wiring resistance.

The above-mentioned various phenomena caused by the difference in wiring resistance can be prevented by a technique of making the wiring resistance equal. For example, Japanese Patent Laid-Open No. 5-72563 discloses a technique of making the resistance value the same by appropriately changing the width and length of the wiring pattern for connection.

In FIG. 3 showing the prior art of the present invention, the wiring width is made smaller for shorter wiring so as to increase the sheet resistance value, so that the wiring resistances are made equal to each other.

However, as the size of screens become larger and the resolutions become higher these days, it becomes necessary to realize interconnections in finer sizes. As described above, the method of changing the resistance value by varying the wiring width cannot be adopted because it is difficult to make the resistance values different from the viewpoint of pattern precision. Another problem with the mesh size of the design mask is causing physical disturbances.

When the above problem is solved, a small error in the wiring width directly affects the change in the resistance value. Therefore, it is not easy to make the wiring resistance the same.

When the length of the wiring is increased, sufficient distance and area are required, thus taking up space on the substrate. In addition, when the wiring length increases by using the folding pattern, interline capacitance is caused due to the additional pattern. As a result, the characteristic can be changed and further variation can occur.

The display circuit driving circuit of the present invention is connected to each of a plurality of first signal lines and a first signal line arranged in parallel with each other, and is connected between the first signal line and a second signal line corresponding to the first signal line. A plurality of connection lines having a first connection point between the control means for controlling the OFF and the control means, and having a second connection point between the corresponding second signal line; The distance between the first connection point and the second connection point is the same.

In the first embodiment of the present invention, the first connection points are provided at different positions among the plurality of connection lines so that the distance between the first connection point and the second connection point is made equal to each other at the plurality of connection lines.

In another embodiment of the present invention, each of the plurality of connection lines has a branched portion extending along a corresponding one of the second signal lines so that the distance between the first connection point and the second connection point is equal to each other in the plurality of connection wires. It is.

In another embodiment of the present invention, the connecting line has a sheet resistance that is at least twice as large as the sheet resistance of the thin film which is connected to the connecting line and becomes the electrode provided with the control means.

In another embodiment of the present invention, the first signal line is a data signal line, and the second signal line is a video signal line.

According to another aspect of the present invention, a driving circuit for a display device includes a plurality of first signal lines arranged in parallel with each other, a plurality of second signal lines arranged in parallel with each other and a plurality of groups, and connected to each of the first signal lines. A first connection point for the control means for controlling the ON / OFF state between the first signal line and the second signal line corresponding to the first signal line, and a second connection point for the corresponding one of the second signal lines. It includes a plurality of connection lines having, characterized in that the distance between the first connection point and the second connection point is equal to each other in the plurality of interconnections corresponding to each of the plurality of groups.

According to the present invention, since the lengths for the connection from the connection point are the same, there is no need to change the pattern width or the like to make the wiring resistance the same. This technique, which only changes the connection position, can perform the control width with a very high precision to the present technology level, and the fluctuations in the wiring resistance can be reduced to such an extent that problems rarely occur. Such a change can be realized inexpensively and easily as a conventional technique without using a special technique.

As such, it has the simple structure of the present invention described herein, which makes it possible to provide the advantage of providing a driving circuit which can make the wiring resistance equal to each other without any influence on various characteristics.

These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description, with reference to the accompanying drawings.

The invention has been described as an exemplary first embodiment with reference to the accompanying drawings.

[First Embodiment]

A first embodiment of the present invention will be described with reference to FIG. 4 shows an enlarged view of the wiring pattern in the vicinity of the sampling gate and the image signal line. The manufacturing process of the display device and the structure of a portion thereof, which are not described in this embodiment, are the same as in the conventional embodiment. In addition, like parts having the same structure are denoted by like reference numerals in the prior art shown in FIGS.

In this embodiment, the polycrystalline silicon layer which forms the connection line 1 for connecting the connection electrode 4 which consists of TFTs and is connected to the source electrode of the sampling gate 108 to the image signal line 120 is n-type. Doped with a thickness of 450 nm. In this case, first, the resistance was 30 mA / square. The video signal line 120 for supplying a video signal is formed of an Al metal wiring layer having a thickness of 400 nm. In this case, the sheet resistance was 0.1 kΩ / □.

The connection line 1 is respectively connected to the video signal line 120 through the contact hole 2. The source electrode of the sampling gate 108 is connected to the connection electrode 4 of a metal wiring layer through the contact hole 3, respectively, and is connected to the connection line 1 through the contact hole 5. As shown in FIG.

For example, in each of the sampling gates 108, the number of connection points through the contact holes 5 is six. When the left side of the sampling gate 108 is connected to the lowest line 120R of the video signal line 120, the connection point through the contact hole 5 is disposed at the lowest position and extends from the lowest point of the connection point to the line 120R. The length of is L as shown in FIG.

The center of the sampling gate 108 is connected to the center line 120G of the video signal line 120. Line 120G is located higher by line pitch of the image signal line of FIG. 4 than line 120R. Therefore, since the connection point through the contact hole 5 is disposed at a position higher by the same length as the line pitch than the position with respect to the left sampling gate 108, the length from the lowest of the connection points to 120G is May be equal to L.

The right side of the sampling gate 108 is connected to the upper line 120B of the video signal line 120. Line 120B is located higher than line 120G by the line pitch of video signal line 120 shown in FIG. Therefore, since the connection point through the contact hole 5 is disposed at an upper position by the same length as the line pitch than the position with respect to the center sampling gate 108, the length from the lowest of the connection points to the line 120B May be equal to L.

Thus, according to this embodiment, the connection point through the contact hole for each sampling gate 108 is shifted by the same length as the line pitch of the video signal line, so the length becomes equal to L for all the sampling gates 108. As a result, the wiring resistances can be made equal to each other.

According to the above configuration, the positional relationship between the connection point through the contact hole 5 and the connection electrode 4 becomes different for each of the sampling gates 108. This is believed to cause problems. However, in the case where the connecting electrode 4 is formed of a metal wiring layer and the ratio of the sheet resistance of the sheet layer to the sheet resistance of the gate layer constituting the connecting line 1 is set to 1/300, the position of the contact hole 5 The variation in the resistance value at the connection electrode 4 due to the change can be suppressed to a practically negligible level. When the ratio of the sheet resistance of the metal wiring layer to the sheet resistance of the gate layer is 1/2 or smaller, the variation in the resistance value can be effectively suppressed.

Second Embodiment

The second embodiment will be described with reference to FIG. 5. Similarly to FIG. 4, FIG. 5 shows an enlarged view of the wiring pattern and the image signal line in the vicinity of the sampling gate.

This embodiment is effective when the position of the contact hole 5 cannot be shifted by the same length as the line pitch of the video signal line 120 in the sampling gate 108 as in the first embodiment. In particular, the connecting line for connecting the sampling gate 108 to the video signal line 120, respectively (1) is connected to the video signal line 120 through the contact hole 2 and the connecting electrode through the contact hole 5; It is connected to (4). In order to ensure that the distances between the connection points through the contact holes 2 and 5 are equal to each other, the connection line 1 branches and extends along the image signal line 120 so that the contact points through the contact holes 2 The position is shifted to the branched connecting line.

The structure is described in more detail below.

The position of the contact hole 5 in the connection electrode 4 is not shifted in each of the sampling gates 108. The left side of the sampling gate 108 is connected to the lowest line 120R of the video signal line 120. Since the line 120R is the furthest line, the connecting lines 1 are arranged vertically, and the positions at which they are orthogonally cross (relative length L from the lowest of the contact holes 5). It connects directly to the line 120R via the contact hole 2 in the position which it has.

With respect to the center of the sampling gates 108 connected to the centerline 120G of the video signal line 120, the connection line 1 is arranged to branch along the line 120G and is the lowest of the contact holes 5. Is connected to the line 120G via the contact hole 2 at the terminal position of the branched part having the relative length L from.

With respect to the right side of the sampling gates 108 connected to the upper line 120B of the video signal line 120, the connecting line 1 is arranged to branch along the line 120B and is the lowest of the contact holes 5. It is connected to the line 120B via the contact hole 2 at the terminal position of the branched long part which has the relative length L from the thing.

As described above, in the first and second embodiments, since the lengths of the connection wirings between the connection points are all the same, various problems caused by the difference in the wiring resistance can be completely solved.

Third Embodiment

A third embodiment of the present invention will be described with reference to FIG. The first and second embodiments disclose configurations in which the wiring resistances are made equal to each other with respect to the connection relationship between the sampling gate 108 and the video signal line 120. It is to be understood that the present invention is not limited to this particular configuration. The present invention can be applied to other parts including the same problemism. This embodiment shows an embodiment in which the present invention is applied to the wiring pattern in the clock input portion of the shift register 107.

FIG. 6 shows an example of a wiring pattern in the clock input section of the shift register 107 in the circuit diagram of FIG. In this embodiment, two sets of shift registers are driven by a four phase clock signal. 6 shows a layout around a clocked inverter to which a clock signal is input.

Lines A and B correspond to the first shift register and lines C and D correspond to the second shift register. As shown in the figure, the distance between the TFT 510 and the clock signal line 500 is different between each set, that is, between the lines A and B and also between the lines C and D. According to the conventional wiring, this difference causes a difference in wiring resistance which causes the timing shift of sampling by two sets of shift registers. However, in this embodiment, the connection line is branched along the clock signal line if necessary and connected to the clock signal line at their terminal positions having the same relative distance from the connection point to the TFT 510. As a result, the distance from the connection point with clock signal line 500 to each TFT 510 becomes equal to each other between line A and line B and also between line C and line D. According to this configuration, it is also possible to prevent a change in timing for sampling at each stage of each shift register. In this way, image quality can be improved.

As mentioned above, according to the invention, the lengths for the connection measured from the connection points are made equal to each other only by changing the position of the connection points. Unlike the prior art, it is not necessary to change the pattern width and the like in order to make the wiring resistance equal to each other. In addition, it is not necessary to provide additional space for extending the line. Therefore, the image quality does not deteriorate due to the fluctuation of the pattern and the generation of the floating capacitance. It is possible to realize a driving circuit for a display device with a simple configuration and a great effect.

Many other modifications are natural to those skilled in the art and can be readily made without departing from the scope and spirit of the invention. Accordingly, the claims appended hereto are not intended to be limited to the description set forth herein, but rather should be construed broadly.

Claims (6)

ON / off of a plurality of first signal lines parallel to each other, a plurality of second signal lines parallel to each other, and a second signal line connected to each of the first signal lines and corresponding to the first signal line; Control means for controlling OFF, and a first connecting point between the control means and a second connecting point between the corresponding second signal lines of the plurality of second signal lines, respectively. And a plurality of connection lines, wherein the distance between the first connection point and the second connection point is the same at each of the plurality of connection lines. The method according to claim 1, wherein the first connection point is provided at different positions among the plurality of connection lines, so that the distance between the first connection point and the second connection point is equal to each other in the plurality of connection lines. Drive circuit of the display device. 2. The plurality of connection lines of claim 1, wherein each of the plurality of connection lines has a branched portion extending along it on the corresponding second signal line, such that the distance between the first connection point and the second connection point is increased. The drive circuit of a display device characterized by being the same as each other. 2. The drive circuit of a display device according to claim 1, wherein the sheet resistance of the connecting line is at least twice the sheet resistance of the thin film forming the control means and serving as an electrode to which the connecting line is connected. The display circuit of claim 1, wherein the first signal line is a data signal line, and the second signal line is an image signal line. A plurality of first signal lines parallel to each other, a plurality of second signal lines parallel to each other, and connected to each of the first signal lines, and corresponding to the first signal line and the first signal line; A control means for controlling ON / OFF between the second signal lines, and a first connection point between the control means and a corresponding second signal line in the plurality of second signal lines, respectively. A plurality of connection lines each having two connection points, wherein for each of the plurality of groups of the plurality of connection lines, a distance between the first connection contact point and the second connection point is the same at each of the plurality of connection lines; A drive circuit for a display device, characterized in that.