JPS5910588B2 - integrated circuit elements - Google Patents
integrated circuit elementsInfo
- Publication number
- JPS5910588B2 JPS5910588B2 JP51074521A JP7452176A JPS5910588B2 JP S5910588 B2 JPS5910588 B2 JP S5910588B2 JP 51074521 A JP51074521 A JP 51074521A JP 7452176 A JP7452176 A JP 7452176A JP S5910588 B2 JPS5910588 B2 JP S5910588B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- arrangement
- decoder
- circuit elements
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は集積回路素子、例えば単位デコーダの配列間隔
が小さく、コンタクトを有する拡散層が隣接して配置で
きない場合のデコーダを構成する各トランジスタの配置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the arrangement of transistors constituting an integrated circuit element, such as a unit decoder, when the array interval is small and diffusion layers having contacts cannot be arranged adjacently.
第１図は、周知のＮＯＲ型デコーダであり、プリチヤー
ジＭ０５１は単位デコーダあたり必ず１個必要とする。FIG. 1 shows a well-known NOR type decoder, and one precharge M051 is always required for each unit decoder.
一方集積度を上げる必要上、セルの１辺の長さ、すなわ
ちデコーダの配列間隔（第２図１１と１２の間隔ｌｐ）
をＡｌの最小配線ピッチ（第２図ａ）まで小さくした場
合、第２図ｂに示す如く各単位デコーダに１個づつプリ
チヤージＭ０５を従来のように並べて配列できない（１
ａ＞１ｐ）０これはおもにコンタクトを含む拡散層の配
列ピッチがＡｌの最小配線ピッチより大である場合に生
ずる。本発明の目的は、上記欠点を解消し、単位デコー
ダ配列間隔が、コンタクトを含む拡散層の配列ピッチよ
り小さい場合でも、各デコーダ出力線に１個プリチヤー
ジＭ０５が配置可能なデコーダ回路の素子配置法を提供
することにある。On the other hand, due to the need to increase the degree of integration, the length of one side of the cell, that is, the arrangement interval of decoders (interval lp in Figure 2 11 and 12)
When the wiring pitch of Al is reduced to the minimum wiring pitch (Fig. 2a), it is not possible to arrange one precharge M05 in each unit decoder as in the conventional arrangement as shown in Fig. 2b (Fig. 2b).
a>1p)0 This mainly occurs when the arrangement pitch of the diffusion layers including contacts is larger than the minimum wiring pitch of Al. An object of the present invention is to provide an element arrangement method for a decoder circuit in which one precharge M05 can be arranged in each decoder output line even when the unit decoder arrangement interval is smaller than the arrangement pitch of the diffusion layer including contacts. Our goal is to provide the following.
以下本発明を実施例によつて詳細に説明する。The present invention will be explained in detail below with reference to Examples.
第３図は、本発明による実施例である。本発明の特徴は
、デコーダ出力線（第３図１１、１２、１３）が２端（
ａ、ｂ）を有すること、またプリチヤージＭ０５は、上
記出力線と接続されておれば、配置は任意であることを
利用し、隣りあつたデコーダ出力線たとえば１２、１１
毎に第３図に示す如く、プリチヤージＭ０５を交互に出
力線の両端に設けることにある。このような配置をとれ
ば、Ａｌの配線ピッチの２倍の領域に１個のプリチヤー
ジＭ０５を作ればよく、デコーダのレイアウトが可能と
なる。第４図に本発明のレイアウトの一例を示す。以上
述べた如く、単位デコーダの配列間隔が小さく、コンタ
クトを含む拡散層が隣接して配置でＪ きぬ場合、本発
明の素子配置を用いれば、容易にデコーダのレイアウト
が可能となる。FIG. 3 is an embodiment according to the present invention. A feature of the present invention is that the decoder output lines (11, 12, 13 in FIG. 3) have two ends (
a, b), and that the precharge M05 can be arranged arbitrarily as long as it is connected to the above output line.
As shown in FIG. 3, precharge M05 is provided alternately at both ends of the output line. If such an arrangement is adopted, it is sufficient to create one precharge M05 in an area twice the Al wiring pitch, and the layout of the decoder becomes possible. FIG. 4 shows an example of the layout of the present invention. As described above, when the arrangement interval of unit decoders is small and the diffusion layers including contacts cannot be arranged adjacently, the layout of the decoders can be easily realized by using the element arrangement of the present invention.
第１図は、周知のＮＯＲ型デコーダ、第２図は、Ａｌの
配線ピッチで決まる単位デコーダ配列ピツｊ チおよび
コンタクトを有する拡散層の配列ピッチを示す図、第３
図、第４図は、本発明による実施例である。
：スイツチトランジスタ
１１，１２，１３：
配線、ＣＥ：スイツチトランジスタ１の駆動信号。FIG. 1 shows a well-known NOR type decoder, FIG. 2 shows a unit decoder arrangement pitch determined by the Al wiring pitch and an arrangement pitch of a diffusion layer having contacts, and FIG.
FIG. 4 shows an embodiment according to the present invention. : Switch transistors 11, 12, 13: Wiring, CE: Drive signal for switch transistor 1.
Claims (1)
に所定の信号を与えるために、上記配線の端部に設けた
回路素子を有する単一基板上に構成された回路において
、上記回路素子を、上記、配線ごとに、その配線の一方
の端部に交互になるように設けた集積回路素子。 ２ 回路素子として電界効果トランジスタを用い上記電
界効果トランジスタのソース側に所定の信号源を接続し
、ドレイン側を上記配線に接続し、ゲートを上記電界効
果トランジスタをオン、オフさせるための電圧源に接続
した特許請求の範囲第１項記載の集積回路素子。[Claims] 1. Constructed on a single substrate having two or more wires arranged in parallel to each other and a circuit element provided at the end of the wires in order to give a predetermined signal to the wires. An integrated circuit element in which the circuit elements are provided alternately at one end of each wiring. 2. Using a field effect transistor as a circuit element, a predetermined signal source is connected to the source side of the field effect transistor, the drain side is connected to the wiring, and the gate is connected to a voltage source for turning the field effect transistor on and off. An integrated circuit device according to claim 1 connected thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51074521A JPS5910588B2 (en) | 1976-06-25 | 1976-06-25 | integrated circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51074521A JPS5910588B2 (en) | 1976-06-25 | 1976-06-25 | integrated circuit elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53986A JPS53986A (en) | 1978-01-07 |
| JPS5910588B2 true JPS5910588B2 (en) | 1984-03-09 |
Family
ID=13549696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51074521A Expired JPS5910588B2 (en) | 1976-06-25 | 1976-06-25 | integrated circuit elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5910588B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BR8207659A (en) * | 1981-04-17 | 1983-03-29 | Tohru Negishi | SUNGLASSES FOR MULTIFOCAL LENSES |
| US4861151A (en) * | 1986-12-26 | 1989-08-29 | Tohru Negishi | Frame for multifocal spectacles |
-
1976
- 1976-06-25 JP JP51074521A patent/JPS5910588B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53986A (en) | 1978-01-07 |
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