JPH02148132U - - Google Patents

Info

Publication number
JPH02148132U
JPH02148132U JP5668389U JP5668389U JPH02148132U JP H02148132 U JPH02148132 U JP H02148132U JP 5668389 U JP5668389 U JP 5668389U JP 5668389 U JP5668389 U JP 5668389U JP H02148132 U JPH02148132 U JP H02148132U
Authority
JP
Japan
Prior art keywords
region
polycrystalline silicon
silicon film
drain
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5668389U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5668389U priority Critical patent/JPH02148132U/ja
Publication of JPH02148132U publication Critical patent/JPH02148132U/ja
Pending legal-status Critical Current

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Landscapes

  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案によるＴＦＴの断面図、第２図
は従来ＴＦＴの断面図、第３図はＴＦＴアレイの
平面図である。 １……透明ガラス基板、２，４……ＳｉＯ２膜
、３，５……多結晶シリコン膜、６……ＩＴＯ膜
。 FIG. 1 is a sectional view of a TFT according to the present invention, FIG. 2 is a sectional view of a conventional TFT, and FIG. 3 is a plan view of a TFT array. 1... Transparent glass substrate, 2, 4... SiO 2 film, 3, 5... Polycrystalline silicon film, 6... ITO film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ドレインに画像信号を入力し、ソースに表示画
素電極を結合した薄膜トランジスタに於いて、ド
レイン領域、チヤンネル領域、ソース領域を連続
した多結晶シリコン膜で形成し、上記ドレイン領
域の多結晶シリコン膜厚さ０．８μｍ以上とする
と共に、上記チヤンネル領域並びにソース領域の
多結晶シリコン膜をドレイン領域より薄く形成し
た事を特徴とする薄膜トランジスタ。 In a thin film transistor in which an image signal is input to the drain and a display pixel electrode is coupled to the source, the drain region, channel region, and source region are formed of a continuous polycrystalline silicon film, and the thickness of the polycrystalline silicon film in the drain region is A thin film transistor characterized in that the polycrystalline silicon film in the channel region and the source region is formed to be thinner than the drain region.
JP5668389U 1989-05-17 1989-05-17 Pending JPH02148132U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5668389U JPH02148132U (en) 1989-05-17 1989-05-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5668389U JPH02148132U (en) 1989-05-17 1989-05-17

Publications (1)

Publication Number Publication Date
JPH02148132U true JPH02148132U (en) 1990-12-17

Family

ID=31580725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5668389U Pending JPH02148132U (en) 1989-05-17 1989-05-17

Country Status (1)

Country Link
JP (1) JPH02148132U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10161152A (en) * 1996-11-29 1998-06-19 Seiko Epson Corp Liquid crystal pannel substrate, liquid crystal pannel using the same and projection-type display device
JP2004126597A (en) * 2003-10-06 2004-04-22 Seiko Epson Corp Substrate for liquid crystal panel and liquid crystal panel using the same and projection type display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10161152A (en) * 1996-11-29 1998-06-19 Seiko Epson Corp Liquid crystal pannel substrate, liquid crystal pannel using the same and projection-type display device
JP2004126597A (en) * 2003-10-06 2004-04-22 Seiko Epson Corp Substrate for liquid crystal panel and liquid crystal panel using the same and projection type display

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