JP4397753B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device using a semiconductor thin film having a crystal structure and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device using an inverted staggered thin film transistor (hereinafter abbreviated as TFT).

  Note that in this specification, “semiconductor device” refers to all devices that operate using semiconductor characteristics. Accordingly, TFTs, AMLCDs (active matrix liquid crystal display devices), and electronic devices described in this specification are all included in the category of semiconductor devices.

  Conventionally, a TFT is used as a switching element of an active matrix liquid crystal display device (hereinafter abbreviated as AMLCD). At present, products having a circuit configuration with TFTs using an amorphous silicon film (amorphous silicon film) as an active layer occupy the market. In particular, as the TFT structure, an inverted stagger structure with a simple manufacturing process is often employed.

  However, as the performance of AMLCDs increases year by year, the operating performance (especially the operating speed) required for TFTs tends to be severe. Therefore, it has become difficult to obtain an element having sufficient performance at the operating speed of a TFT using an amorphous silicon film.

  Accordingly, TFTs using a polycrystalline silicon film (polysilicon film) instead of an amorphous silicon film have attracted attention, and development of TFTs using a polycrystalline silicon film as an active layer has been proceeding at a remarkable pace. At present, some of them are commercialized.

  Many presentations have already been made on the structure of an inverted staggered TFT using a polycrystalline silicon film as an active layer. For example, “Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method: H. Hayashi et.al., IEDM95, PP829-832, 1995” There is a report.

  This report describes a typical example of an inverted stagger structure using a polycrystalline silicon film (Fig. 4), but there are various problems with such an inverted stagger structure (so-called channel stop type). I have it.

  First, since the entire active layer is as thin as about 50 nm, impact ionization occurs at the junction between the channel formation region and the drain region, and a deterioration phenomenon such as hot carrier injection appears remarkably. Therefore, it becomes necessary to form a large LDD region (Light Doped Drain region).

  The controllability of the LDD region becomes the most serious problem. In the LDD region, the control of the impurity concentration and the length of the region is very delicate, and the length control is particularly problematic. At present, a method of defining the length of the LDD region by a mask pattern is adopted. However, as the miniaturization proceeds, a slight patterning error causes a large difference in TFT characteristics.

  Variation in sheet resistance in the LDD region due to variation in the thickness of the active layer is also a serious problem. Further, variations such as the taper angle of the gate electrode can also cause variations in the effect of the LDD region.

  Further, in order to form the LDD region, a patterning process is necessary, which directly increases the manufacturing process and decreases the throughput. In the inverted stagger structure described in the above report, it is expected that at least six masks (up to source / drain electrode formation) are required.

  As described above, in the channel stop type inverted stagger structure, the LDD regions must be formed in the lateral plane on both sides of the channel formation region, and it is very difficult to form a reproducible LDD region. is there.

  Further, the conventional AMLCD has a structure in which an auxiliary capacitor is provided in each pixel in order to compensate for leakage of charges held in the liquid crystal layer.

  It is an object of the present invention to provide a technique for manufacturing a semiconductor device with high productivity and high reliability and reproducibility by a very simple manufacturing process. A TFT bottom gate type TFT is used as a pixel matrix circuit. At the same time, it is an object of the present invention to provide a configuration of a semiconductor device and a manufacturing method thereof that can be manufactured without complicating the process and particularly without increasing the number of masks when manufacturing an auxiliary capacitor.

The configuration of the invention disclosed in this specification includes a pixel matrix circuit having a plurality of gate wirings, a plurality of source wirings, a bottom gate thin film transistor disposed in each pixel, and an auxiliary capacitor connected to the pixel electrode. A semiconductor device,
The thin film semiconductor layer in which the source region, the drain region, and at least one channel formation region of the thin film transistor are formed has a crystal structure,
The source and drain regions are at least a first conductive layer toward the gate insulating film, a second conductive layer having a higher resistance than the first conductive layer, and a first conductive layer having the same conductivity type as the channel forming region. It has a laminated structure consisting of semiconductor layers,
The impurity concentration profile that imparts conductivity to the first and second conductive layers continuously changes from the first conductive layer to the second conductive layer,
The auxiliary capacitor includes a first electrode made of the same conductive film as the gate wiring, a dielectric in contact with the first electrode, and a second semiconductor in contact with the dielectric and having the same conductivity type as the channel formation region And a second electrode formed of a layer.

  Another configuration of the invention is characterized in that, in the pixel matrix circuit having the above-described configuration, a semiconductor layer is used for the second electrode of the auxiliary capacitor, instead of a conductive film common to the source wiring. .

  According to another aspect of the present invention, in the pixel matrix circuit having the above structure, the pixel electrode and the second electrode of the auxiliary capacitor are formed of a conductive film common to the source wiring.

  According to another aspect of the invention, in the matrix circuit, one electrode of the auxiliary capacitor is formed of a conductive film common to the gate wiring, and the pixel electrode has a region in contact with a dielectric of the auxiliary capacitor. A pixel device is used as an electrode for one of the auxiliary capacitors.

In addition, the configuration of the invention related to the manufacturing method is as follows:
Forming the gate wiring and the first electrode of the auxiliary capacitance on a substrate having an insulating surface;
Forming an insulating layer covering the gate wiring and the first electrode;
Forming an amorphous semiconductor film on the insulating layer;
Adding a catalyst element for promoting crystallization to the amorphous semiconductor film, and obtaining a semiconductor film having a crystal structure by heat treatment;
Adding an impurity selected from only Group 15 or Group 13 and Group 15 to the semiconductor film having the crystal structure to form a conductive layer;
A step of gettering the catalytic element in the semiconductor film having the crystal structure to the conductive layer by heat treatment;
The semiconductor film having the crystal structure is patterned to form a first thin film semiconductor layer that forms a channel formation region of the thin film transistor, and a second thin film semiconductor layer that overlaps the first electrode with the insulating layer interposed therebetween Forming, and
A first conductive film covering at least a region where a source region and a drain region of a thin film transistor are formed on the first thin film semiconductor layer; and a second cover covering a surface of the second thin film semiconductor layer. Forming a conductive film;
Etching the first thin film semiconductor layer using the first conductive film as a mask to form a channel formation region of the thin film transistor,
The second electrode of the auxiliary capacitor is formed on the second thin film semiconductor layer.

  Although one electrode of the auxiliary capacitor is formed in the semiconductor layer by the above manufacturing method, another structure relating to the manufacturing method of the present invention is the auxiliary capacitor together with the source wiring and the source electrode and the drain electrode of the thin film transistor. The second electrode is formed, and the conductive film common to the source wiring is used as the auxiliary capacitor electrode.

  In another method, the pixel electrode is used as an auxiliary capacitor electrode by forming the pixel electrode in contact with the pixel TFT and the dielectric of the auxiliary capacitor.

  By implementing the present invention, a semiconductor device with high productivity can be manufactured with a very small number of masks (typically four).

  In addition, since an electric field relaxation layer (LDD region, mask offset region, thickness offset region, etc.) having small variation in characteristics can be formed between the channel formation region and the source / drain electrodes, the semiconductor device has high reliability and high reproducibility. Can be realized.

  The embodiment of the present invention having the above-described configuration will be described in detail in the examples described below, particularly in the example 13 and later.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  [Example 1] A typical example of the present invention will be described with reference to FIGS. First, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

  A base film 102 made of an insulating film containing silicon as a main component is formed on a glass substrate (or quartz or silicon substrate) 101. A gate electrode (first wiring) 103 made of a conductive film is formed thereon.

  The line width of the gate electrode 103 is 1 to 10 μm (typically 3 to 5 μm). The film thickness is 200 to 500 nm (typically 250 to 300 nm). In this embodiment, a gate electrode having a line width of 3 μm is formed using a 250 nm thick Ta / TaN (tantalum / tantalum nitride) laminated film.

  As the gate electrode 103, a heat-resistant material (tantalum, tungsten, titanium, chromium, molybdenum, conductive silicon, or the like) that can withstand a temperature of at least 600 ° C. (preferably 800 ° C.) is used. The reason will be described later. Here, the first patterning step (gate electrode formation) is performed.

  Next, a silicon nitride film 104 (film thickness is 0 to 200 nm, typically 25 to 100 nm, preferably 50 nm), a silicon oxynitride film or a silicon oxide film (film thickness is 150 to 300) indicated by SiOxNy. nm, typically 200 nm) 105 is formed, and an amorphous semiconductor film 106 containing silicon as a main component is formed thereon. In this embodiment, an amorphous silicon film is taken as an example, but other compound semiconductor films (such as an amorphous silicon film containing germanium) may be used.

  Further, since the present invention has a channel etch type bottom gate structure, the amorphous silicon film 106 is formed thick. The film thickness range is 100 to 600 nm (typically 200 to 300 nm, preferably 250 nm). In this embodiment, it is 200 nm. As will be described later, the optimum film thickness needs to be appropriately determined depending on what offset region and LDD region are provided in the TFT of the present invention.

  In this embodiment, the amorphous silicon film 106 is formed by a low pressure thermal CVD method, but it is desirable to thoroughly control the concentration of impurities such as carbon, oxygen, and nitrogen during the film formation. If these impurities are large, the subsequent crystallization may be hindered.

In this embodiment, the concentration of each impurity in the formed amorphous silicon film is less than 5 × 10 ¹⁸ atoms / cm ^{3 for} carbon and nitrogen (typically 5 × 10 ¹⁷ atoms / cm ³ or less), oxygen Is controlled to be less than 1.5 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁸ atoms / cm ³ or less). If such management is performed, the impurity concentration finally contained in the channel formation region of the TFT falls within the above range.

  In this way, the state of FIG. Next, a solution containing a catalytic element (typically nickel) that promotes crystallization of silicon is applied by a spin coating method to form a Ni (nickel) -containing layer 107. For detailed conditions, it is preferable to refer to the technique described in Japanese Patent Application Laid-Open No. 7-306052 by the present inventors (here, Example 1 of the same publication). In addition, you may use the technique described in Example 2 of the gazette. (Fig. 1 (B))

In this publication, although means for applying an aqueous solution containing Ni is shown, the following addition means may be used.
(1) Direct addition by ion implantation or ion doping.
(2) Addition by plasma treatment using a Ni electrode.
(3) Formation of Ni film or Nix Siy (nickel silicide) film by CVD, sputtering or vapor deposition.

  In addition to Ni, catalytic elements that promote crystallization of silicon include Ge (germanium), Co (cobalt), platinum (Pt), palladium (Pd), iron (Fe), copper (Cu), gold ( Au), lead (Pb), or the like can be used.

  After the Ni-containing layer 107 is formed, after heat treatment (dehydrogenation process) at 450 to 500 ° C. for 2 hours, the temperature is 500 to 700 ° C. (typically 550 to 600 ° C.) for 2 to 12 hours (typically For 4 to 8 hours), a semiconductor film (crystalline silicon film (polysilicon film) in this embodiment) 108 having a crystal structure is obtained. In this embodiment, crystallization starts from the vicinity of the surface of the amorphous silicon film 106 and proceeds in the direction of the arrow. (Figure 1 (C))

  Next, the crystallinity improvement process of the crystalline silicon film 108 is performed by irradiating laser light or strong light having the same intensity. Here, reduction of intragranular defects, reduction of mismatch grain boundaries, crystallization of an amorphous component, and the like are performed, and a crystalline silicon film 109 having extremely excellent crystallinity is obtained. (Figure 1 (D))

Next, an element selected from Group 15 (typically phosphorus, arsenic or antimony) is added by an ion implantation method (with mass separation) or an ion doping method (without mass separation). In this embodiment, the phosphorus concentration is 1 × 10 ^{19 to} 3 × 10 ²¹ atoms / cm ³ , typically within a depth range of 30 to 100 nm (typically 30 to 50 nm) from the surface of the crystalline silicon film 109. Is adjusted to 1 × 10 to 1 × 10 ²¹ atoms / cm ³ .

In this embodiment, the region 110 containing high-concentration phosphorus formed in this manner is called an n ⁺ layer (or first conductive layer). The thickness of this layer is determined in the range of 30 to 100 nm (typically 30 to 50 nm). In this case, the n ⁺ layer 110 functions as a part of the source / drain electrode later. In this embodiment, an n ⁺ layer having a thickness of 30 nm is formed.

A region 111 containing phosphorus at a low concentration formed under the n ⁺ layer 110 is referred to as an n ⁻ layer (or a second conductive layer). In this case, the n ⁻ layer 111 has a higher resistance than the n ⁺ layer 110 and functions as an LDD region for electric field relaxation later. In this embodiment, an n ⁻ layer having a thickness of 30 nm is formed. (Figure 1 (E))

Under the n ⁻ layer 404, a region in which the phosphorus concentration is extremely lowered and a region 120 that is lower or more intrinsic or substantially intrinsic are formed. Such a region is referred to as i layer 120.

At this time, the concentration profile in the depth direction when phosphorus is added is very important. This will be described with reference to FIG. The concentration profile shown in FIG. 4 is an example when phosphine (PH ₃ ) is added by an ion doping method with an acceleration voltage of 80 keV and an RF power of 20 W.

  In FIG. 4, 401 indicates a crystalline silicon film, and 402 indicates a concentration profile of added phosphorus. This concentration profile is determined by setting conditions such as RF power, added ion species, and acceleration voltage.

At this time, the peak value of the concentration profile 402 is in the n ⁺ layer 403 or in the vicinity of the interface, and the phosphorus concentration decreases as the depth of the crystalline silicon film 401 increases (towards the gate insulating film). At this time, since the phosphorus concentration continuously changes over the entire area inside the film, the n ⁻ layer 404 is always formed under the n ⁺ layer 403.

The phosphorus concentration continuously decreases even inside the n ⁻ layer 404. In this embodiment, a region where the phosphorus concentration exceeds 1 × 10 ¹⁹ atoms / cm ³ is considered as the n ⁺ layer 403, and a region in the concentration range of 5 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ is an n ⁻ layer. Considered as 404. However, since there is no clear boundary, it is only considered as a guide.

Further, the region where the phosphorus concentration is extremely lowered and the lower layer thereof become an intrinsic or substantially intrinsic region (i layer) 405. Note that an intrinsic region is a region to which no impurity is intentionally added. The substantially intrinsic region is a region where the impurity concentration (phosphorus concentration in this case) is less than or equal to the spin density of the silicon film or a region where the impurity concentration is 1 × 10 ^{14 to} 5 × 10 ¹⁷ atoms / cm ^3. It refers to a region showing conductivity.

Although such an intrinsic or substantially intrinsic region is formed under the n ⁻ layer 404, the i layer 405 is basically composed of a semiconductor layer having the same conductivity type as the channel formation region. That is, when the channel formation region is weak n-type or p-type, the same conductivity type is exhibited.

Thus, n under the n ⁺ layer 110 by an ion implantation method or an ion doping method to form the n ⁺ layer 110 ^- it is possible to form the layer 111. Such a configuration cannot be realized when an n ⁺ layer is provided by film formation as in the prior art. Further, the thickness of the n ⁺ layer 110 and the n ⁻ layer 111 can be easily controlled by appropriately setting the conditions at the time of ion addition.

In particular, since the thickness of the n ⁻ layer 111 becomes the thickness of the LDD region later, very precise control is required. In the ion doping method or the like, since the concentration profile in the depth direction can be precisely controlled by setting the addition conditions, the thickness of the LDD region can be easily controlled. In the present invention, the thickness of the n ⁻ layer 111 may be adjusted in the range of 30 to 200 nm (typically 50 to 150 nm).

Although FIG. 4 shows the concentration profile when the doping process is performed once, the thickness of the n ⁺ layer 403 and the n ⁻ layer 402 can be controlled by dividing the doping process into a plurality of processes. For example, the n ⁻ layer 402 is formed by doping such that a peak of the concentration profile is located at a depth where the n ⁺ layer 403 is to be formed, and a relatively deep location at a low dose. Doping in which the peak of the concentration profile is located at an appropriate depth may be performed.

Next, when the state shown in FIG. 1E is obtained, heat treatment is performed at a temperature of 500 to 700 ° C. (typically 600 to 650 ° C.) for 0.5 to 8 hours (typically 1 to 4 hours). Furnace annealing) is performed to move Ni in the region of the crystalline silicon film to which phosphorus is not added to the n ⁺ layer 110 and n ⁻ layer 111 to which phosphorus is added. In other words, Ni diffuses in the direction of the arrow and is gettered to the n ⁺ layer 110 and the n ⁻ layer 111 to reduce the nickel concentration of the i layer 120 where the channel formation region is formed. (Fig. 2 (A))

By the gettering step of this embodiment, the nickel concentration of the i layer 120 is reduced to 5 × 10 ¹⁷ atoms / cm ³ or less as measured by SIMS. Further, by the gettering technique of this embodiment, the nickel concentration can be reduced to 1 × 10 ¹⁴ atoms / cm ³ or less to the spin density of the i layer 120 or less.

As described above, the present embodiment is greatly characterized in that Ni is gettered by phosphorus contained in the n ⁺ layer 110 and the n ⁻ layer 111, that is, the n ⁺ / n ⁻ layer is used as a gettering region. is there. Further, a part of the n ⁺ / n ⁻ layer obtained by gettering Ni remains as the first and second conductive layers constituting the source / drain region, but becomes inactive nickel phosphide after gettering. No problem.

  In this case, since the distance that Ni should move is only a distance corresponding to the thickness of the crystalline silicon film, gettering is completed very quickly (within a short time). Therefore, (1) the concentration of added phosphorus can be reduced, (2) the heat treatment temperature can be lowered, and (3) the heat treatment time can be shortened.

  In this embodiment, since the TFT is manufactured on the glass substrate, the maximum process temperature is determined by the heat resistance of the glass. However, if a highly heat-resistant substrate such as a quartz substrate is used as the substrate, the maximum temperature for heat treatment for gettering can be increased to 1000 ° C. (preferably 800 ° C.). If the temperature exceeds 800 ° C., the reverse diffusion of phosphorus from the gettering region to the gettering region begins to occur, which is not preferable.

  The reason why the heat resistance of the gate electrode 103 can withstand a temperature of at least 600 ° C. (preferably 800 ° C.) is that this gettering process is taken into consideration. Of course, when the gettering process is performed by lamp annealing or the like without using furnace annealing, the allowable range of the gate electrode is widened.

Thus, after the catalytic element in the i layer 120 is gettered to the n ⁺ / n ⁻ layer, the crystalline silicon film is patterned to form the island-shaped semiconductor layer 112. At this time, when the TFT is finally completed, the length (channel width (W)) in the direction perpendicular to the carrier moving direction is adjusted to 1 to 30 μm (typically 10 to 20 μm). . Here, the second patterning step is performed. (Fig. 2 (B))

  Here, although not shown in the drawing, a part of the exposed gate insulating layer is etched to make electrical connection between the gate electrode (first wiring) and the electrode (second wiring) to be formed next. A hole (a region indicated by 119 in FIG. 2D) is opened. Here, a third patterning step is performed.

  Next, a conductive metal film (not shown) is formed, and the source electrode 113 and the drain electrode 114 are formed by patterning. In this embodiment, a laminated film having a three-layer structure of Ti (50 nm) / Al (200 to 300 nm) / Ti (50 nm) is used. Further, as described above, wiring for electrically connecting to the gate electrode is also formed at the same time. Here, a fourth patterning step is performed. (Fig. 2 (C))

Further, as will be described later, the length (indicated by C ₁ ) of a region (hereinafter referred to as a channel etch region) 115 immediately above the gate electrode 103, that is, a region sandwiched between the source electrode 113 and the drain electrode 114 (hereinafter referred to as a channel etch region). Later, the lengths of the channel formation region and the offset region are determined. C ₁ can be selected from the range of 2 to 20 μm (typically 5 to ₁₀ μm). In this embodiment, C ₁ = 4 μm.

  Next, dry etching is performed using the source electrode 113 and the drain electrode 114 as a mask, and the island-shaped semiconductor layer 112 is etched in a self-aligning manner. Therefore, the etching proceeds only in the channel etch region 115. (Fig. 2 (D))

At this time, the n ⁺ layer 110 and the n ⁻ layer 111 are completely etched, and the etching is stopped in such a manner that only the intrinsic or substantially intrinsic i layer 120 is left. In the present invention, finally, only the semiconductor layer of 10 to 100 nm (typically 10 to 75 nm, preferably 15 to 45 nm) is left. In this embodiment, a semiconductor layer having a thickness of 30 nm is left.

  When the etching of the island-shaped semiconductor layer 112 (channel etch process) is completed in this way, a silicon oxide film or a silicon nitride film is formed as the protective film 116, and an inverted staggered TFT having a structure as shown in FIG. 2D is obtained. .

In this state, in the channel-etched island-like semiconductor layer 112, a region located immediately above the gate electrode 113 becomes a channel formation region 117. In the configuration of this embodiment, the gate electrode width corresponds to the length of the channel formation region, and the length indicated by L ₁ is called the channel length. In addition, the region 118 located outside the end portion of the gate electrode 113 does not receive the electric field from the gate electrode 113 and becomes an offset region. This length is represented by X _1.

In this embodiment, the line width (corresponding to L ₁ ) of the gate electrode 113 is 3 μm, and the length (C ₁ ) of the channel etch region 115 is 4 μm. Therefore, the length of the offset region (X ₁ ) Is 0.5 μm.

Here, an enlarged view of the drain region (semiconductor layer in contact with the drain electrode 114) is shown in FIG. In FIG. 3, 103 is a gate electrode, 301 is a channel formation region, 302 is an n ⁺ layer (source or drain electrode), 303 and 304 are offset regions having different film thicknesses, and 305 is an n ⁻ layer (LDD region).

  Note that although not described here, the source region (semiconductor layer in contact with the source electrode 113) also has a similar structure.

Further, although the structure shown in FIG. 3 is schematically shown, attention should be paid to the film thickness relationship in each region. The most preferable configuration in configuring the present invention is a case where the thicknesses are in the relationship of n ⁺ layer 302 <n ⁻ layer 305 <offset region (i layer) 304.

This is because the n ⁺ layer 302 only functions as an electrode and is thin and sufficient. On the other hand, the n ⁻ layer 305 and the offset region 304 need to have appropriate thicknesses for effective electric field relaxation.

In the configuration of this embodiment, two offset regions 303 and 304 and an LDD region 305 having different film thickness exist from the channel formation region 301 to the n ⁺ region 302. Reference numeral 303 denotes an offset region in the film surface direction formed by mask alignment, and is referred to as a mask offset region.

  Reference numeral 304 denotes an offset region in the film thickness direction corresponding to the film thickness of the i layer, and is referred to as a thickness offset region. The thickness of the thickness offset region 304 may be determined in the range of 100 to 300 nm (typically 150 to 200 nm). However, it is necessary to make the film thickness larger than the film thickness of the channel formation region. If the film thickness is thinner than the channel formation region, a good offset effect cannot be expected.

  The present inventors call such a structure composed of offset + LDD as an HRD (High Resistance Drain) structure, and distinguish it from a normal LDD structure. In the case of the present embodiment, the HRD structure is constituted by a three-stage structure of mask offset + thickness offset + LDD.

  At this time, since the LDD region 303 is controlled by the film thickness and impurity concentration of the LDD region, it has the advantages of extremely high reproducibility and small characteristic variation. As described in the conventional example, the LDD region formed by patterning has a problem of variation in characteristics due to patterning errors.

Note that since the length (X ₁ ) of the mask offset region 303 is controlled by patterning, it is affected by errors due to patterning, shrinkage of glass, and the like. However, since the thickness offset region 304 and the LDD region 305 exist after that, the influence of the error is alleviated and the characteristic variation can be reduced.

The length (X ₁ ) of the mask offset is expressed by (C ₁ −L ₁ ) / 2 using the channel length (L ₁ ) and the length (C ₁ ) of the channel etch region. Therefore, a desired offset length (X ₁ ) can be set by a patterning process when forming the source / drain electrodes. In the configuration of the present embodiment, the offset length (X ₁ ) can be 0.3 to 3 μm (typically 1 to 2 μm).

  Note that an inverted staggered TFT having a structure as shown in FIG. 2D cannot be realized by a conventional TFT using an amorphous silicon film as an active layer (island semiconductor layer). This is because, when an amorphous silicon film is used, the mobility of carriers (electrons or holes) becomes extremely slow unless the source / drain electrode and the gate electrode overlap each other.

Even if the source / drain electrode and the gate electrode overlap each other, the mobility (field effect mobility) of the TFT using the amorphous silicon film is at most about 1 to 10 cm ² / Vs. On the other hand, if the structure as in this embodiment is adopted, the mobility is too low to function as a switching element.

  However, since the crystalline silicon film is used as the active layer in the present invention, the carrier mobility is sufficiently fast. Therefore, sufficient mobility can be obtained even with the structure as in this embodiment. That is, the structure of this embodiment can be realized only by using a semiconductor film having a crystal structure as a semiconductor layer.

  In addition, since the inverted staggered TFT of this embodiment has an HRD structure, it is very strong against deterioration phenomena such as hot carrier injection due to impact ionization and has high reliability. Moreover, the effect of the LDD region is dominant, and the LDD region is formed with very good controllability, so that the variation in characteristics is very small.

  For this reason, the structure as in this embodiment is suitable for a TFT that constitutes a circuit that requires a high breakdown voltage and does not require a high operation speed.

  Further, as shown in the manufacturing process of this embodiment, only four masks are required to obtain an inverted staggered TFT having the structure shown in FIG. This means that the throughput and the yield are dramatically improved considering that the conventional channel stop type TFT requires six masks.

  As described above, according to the structure of this embodiment, a bottom gate type TFT having high reliability and reproducibility can be manufactured by a manufacturing process with high mass productivity.

Note that the mobility of a bottom gate type TFT (N-channel type TFT) manufactured in accordance with the manufacturing process of this embodiment is 30 to 250 cm ^{2 /} Vs (typically 10 to 150 cm ^{2 /} Vs).
The threshold voltage can be 0-3V.

[Example 2]
In the present embodiment, a configuration example different from the first embodiment in the configuration of the present invention is shown. Since the TFT manufacturing process may basically follow the first embodiment, only necessary portions will be described in this embodiment.

First, the state shown in FIG. 5A is obtained in accordance with the manufacturing process of Example 1. The difference from the first embodiment is that the length of the channel etch region 500 is C ₂ when the source electrode 501 and the drain electrode 502 are formed. At this time, C ₂ is narrower than the gate electrode width, and is selected in the range of 2 to 9 μm (typically 2 to 4 μm). That is, it is a feature of this embodiment that the gate electrode and the source / drain electrode are provided so as to overlap.

In this state, when the channel etch process is performed as shown in the first embodiment and a protective film is provided, the state shown in FIG. 5B is obtained. At this time, a region indicated by 503 is a channel formation region, and the channel length is represented by L ₂ (= C ₂ ). Further, the length (Y2) of the region 504 overlapped by the mask design (referred to as a mask overlap region) 504 is represented by (E−L ₂ ) / 2 where E is the gate electrode width.

FIG. 5C is an enlarged view of the drain region. In the TFT operation, carriers are channel formation region 503 (thickness 50 nm), mask overlap region 504 (thickness 160 nm), and LDD region 505 (thickness). 50 nm) and reaches the n ⁺ layer 506 (thickness 40 nm) and the drain electrode 502.

  In this case, an electric field from the gate electrode is also formed in the mask overlap region 504. However, since the electric field is weakened as the LDD region 505 is approached, such a region has substantially the same function as the LDD region. . Of course, if it is further closer to the LDD region 505, the electric field is not completely formed, and it can function as an offset (thickness offset) region.

  As described above, in the structure of this embodiment, the HRD structure is constituted by substantial LDD due to overlap + LDD due to thickness offset + low concentration impurities. Further, when the thickness of the overlap region 504 is thin, an LDD structure consisting only of LDD due to overlap + LDD due to low concentration impurities can be taken.

Even in the configuration of the present embodiment, the overlap region 504 and the LDD region 505 are controlled by the respective film thicknesses, so that the characteristic variation is very small. The length of the overlap region (Y ₂₎ but includes an error due to patterning such, LDD by overlap, because LDD is not affected by such errors due to the thickness direction offset and the low concentration impurity Y ₂ The characteristic variation due to the error is reduced.

  Note that the structure as in this embodiment is suitable for a TFT constituting a circuit that has a small offset component and requires a high operating speed.

  In addition, the structure of this embodiment has an advantage that the substrate floating effect is unlikely to occur because minority carriers accumulated in the channel formation region due to impact ionization are quickly extracted to the source electrode. Therefore, it is possible to realize a TFT having a high operation speed and a very high breakdown voltage characteristic.

  [Embodiment 3] This embodiment shows a configuration example different from Embodiments 1 and 2 in the configuration of the present invention. Since the TFT manufacturing process may basically follow the first embodiment, only necessary portions will be described in this embodiment.

First, the state shown in FIG. 6A is obtained in accordance with the manufacturing process of Example 1. The difference from the first embodiment is that the length of the channel etch region 600 is C ₃ when the source electrode 601 and the drain electrode 602 are formed. At this time, C ₃ is 1 to 10 μm (typically 3 to 5 μm) to match the gate electrode width.

In this state, when the channel etch process is performed as shown in the first embodiment and a protective film is provided, the state shown in FIG. 6B is obtained. At this time, a region indicated by 603 is a channel formation region, and the channel length is represented by L ₃ (= C ₃ ).

FIG. 6C is an enlarged view of the drain region. In the TFT operation, carriers are channel formation region 603 (thickness 100 nm), thickness offset region 604 (thickness 150 nm), and LDD region 605 (thickness). 100 nm) to reach the n ⁺ layer 606 (thickness 50 nm) and the drain electrode 602. That is, in the structure of the present embodiment, the HRD structure is a two-stage structure of thickness offset + LDD.

  Also in the configuration of the present embodiment, the thickness offset region 604 and the LDD region 605 are controlled by the respective film thicknesses, so that the characteristic variation is very small. In addition, sufficient breakdown voltage characteristics can be obtained.

  [Embodiment 4] This embodiment shows a configuration example different from Embodiments 1 to 3 in the configuration of the present invention. Since the TFT manufacturing process may basically follow the first embodiment, only necessary portions will be described in this embodiment.

  First, the state of FIG. 7A is obtained in accordance with the manufacturing process of Example 1. Here, the difference from the first embodiment is that when the source electrode 701 and the drain electrode 702 are formed, either the source electrode or the drain electrode is overlapped with the gate electrode, and the other is not overlapped. .

In this embodiment, the length of the channel etch region 700 is C ₄ . At this time, C ₄ is selected in the range of 1 to 10 μm (typically 3 to 6 μm).

In this state, a channel etch process is performed as shown in Embodiment 1 to provide a state shown in FIG. 7B when a protective film is provided. At this time, a region indicated by 703 becomes a channel formation region, and the channel length is represented by L ₄ (= C ₄ −X ₄ ).

Here, X4 is the length of the mask offset region 704. It may be the first embodiment with reference the numerical range of X _4. Further, the numerical range of the length of the mask overlap region 705 may be referred to the second embodiment.

  In this example, the HRD structure described in Example 1 and the HRD structure (or LDD structure) described in Example 2 are combined. Since the structural description has already been described in the first and second embodiments, the description thereof is omitted here.

  When the structure as in this embodiment is employed, it is particularly preferable to use the HRD structure (or LDD structure) shown in Embodiment 2 for the source region and the HRD structure described in Embodiment 1 for the drain region.

  For example, an electric field concentration is particularly intense at the channel end (junction) on the drain region side, and an HRD structure having a large resistance component as shown in the first embodiment is desirable. On the other hand, since there is no need for such a high withstand voltage countermeasure on the source side, an HRD (or LDD) structure with a small resistance component as shown in the second embodiment is suitable.

In this embodiment, the configuration of Embodiment 2 can be combined with either one of the source / drain regions. As described above, the HRD structure or the LDD structure shown in the first to third embodiments may be appropriately selected by the practitioner and used in the source / drain region, and an optimum structure may be designed in view of circuit design. In this case, 3 ² = 9 combinations are possible.

  [Embodiment 5] In this embodiment, an example in which a CMOS circuit (inverter circuit) is formed using bottom gate type TFTs having the configurations shown in Embodiments 1 to 4 will be described with reference to FIG. Note that the CMOS circuit is configured by complementarily combining an N-channel TFT and a P-channel TFT formed on the same substrate.

  FIG. 8 shows a CMOS circuit using the configuration shown in the fourth embodiment, in which 801 is a source electrode of a P-channel TFT, 802 is a source electrode of an N-channel TFT, and 803 is a drain electrode common to N / P.

In the N-channel TFT, n ⁺ layers 804 and 805 and n ⁻ layers 806 and 807 are formed by the manufacturing process described in Embodiment 1. On the other hand, p ⁺⁺ layers 808 and 809 and p ⁻ layers 810 and 811 are formed on the P-channel TFT.

  Note that it is very easy to manufacture a CMOS circuit on the same substrate. In the case of the present invention, first, the state of FIG.

  In this state, an element selected from the group 15 is added to the entire surface regardless of the N-type / P-type, but when a P-channel TFT is manufactured, the region to be the N-channel TFT is hidden by a resist mask or the like. An element selected from Group 13 (typically boron, indium, or gallium) may be added.

In this embodiment, boron is taken as an example. At this time, boron must be added to a concentration higher than that of phosphorus to reverse the conductivity. Also, in order to completely invert all n ⁺ and n ⁻ layers to p ⁺⁺ and p ⁻ layers, it is important to adjust the concentration profile when boron is added and add it deeper than the addition depth of phosphorus. It is.

Therefore, the concentration profile of boron in the film is as shown in FIG. In FIG. 9, 900 is a semiconductor layer, 901 is a phosphorus concentration profile before boron addition, 902 is a boron concentration profile after boron addition, 903 is a p ⁺⁺ layer, 904 is a p ⁻ layer, and 905 is an i layer. .

At this time, the thickness of the p ⁺⁺ layer 903 is 10 to 150 nm (typically 50 to 100 nm), and the boron concentration in the p ⁺⁺ layer is 3 × 10 ¹⁹ to 1 × 10 ²² atoms / cm. ³ , typically adjusted to 3 × 10 ^{19 to} 3 × 10 ²¹ atoms / cm ³ .

On the other hand, the thickness of the p ⁻ layer 904 is 30 to 300 nm (typically 100 to 200 nm), and the boron concentration is adjusted to 5 × 10 ^{17 to} 3 × 10 ¹⁹ atoms / cm ^3. To do. To do. However, since the P-channel TFT is inherently resistant to deterioration, it is not always necessary to use the p ⁻ layer as the LDD region. The purpose of referring to the thickness of the p ⁻ layer 904 is that the p ⁻ layer is always formed by a concentration gradient that continuously changes as long as an adding means such as an ion implantation method is used.

  By the way, in this embodiment, both the N-channel TFT and the P-channel TFT use the HRD structure (type using an overlap region) having the structure shown in Embodiment 2 on the source region side, and on the drain region side. The HRD structure (type using mask offset) having the configuration shown in the first embodiment is provided.

Therefore, as apparent from the top view, the source region side of the P-channel TFT has an overlap region having a length of Y _i , and the drain region side has a mask offset region having a length of X _i. is doing. The N channel TFT has an overlap region having a length of Y _j on the source region side and a mask offset region having a length of X _j on the drain region side.

At this time, the lengths of X _i and X _j and Y _i and Y _j can be freely adjusted by mask design. Therefore, each length may be determined as appropriate according to the circuit configuration, and it is not necessary to arrange the lengths of the N-channel type and the P-channel type.

  In addition, with such a structure, the breakdown voltage characteristics of the region serving as the common drain of the CMOS circuit can be increased, which is a very effective configuration when configuring a circuit with a high operating voltage.

Although the configuration of the CMOS circuit using the TFT having the configuration shown in Examples 1 to 4 is shown in FIG. 8, it goes without saying that all other combinations are possible. Since there are nine possible configuration patterns for one TFT, there are 9 ² = 81 patterns in a CMOS circuit. Among these combinations, an optimal combination may be adopted according to the performance required by the circuit.

Further, as shown in this embodiment, the present invention can be easily applied to a P-channel TFT. In that case, the mobility of the bottom gate type TFT (P channel type TFT) of the present invention is 30 to 150 cm ² / Vs (typically 10 to 100 cm cm ² / Vs), and the threshold voltage is −1 to −3 V. It can be realized.

  [Example 6] In this example, an example in which Ge (germanium) is used as a catalytic element for promoting crystallization of silicon will be described. In the case of using Ge, addition by ion implantation, ion doping, or plasma treatment is preferably performed because of its high versatility. Moreover, it is also possible to add from the vapor phase by performing a heat treatment in an atmosphere containing Ge.

Since Ge is an element belonging to the same group 14 as Si (silicon), compatibility with Si is very good. As described above, a compound of Ge and Si (indicated by Si _x Ge _1-x, where 0 <X <1) can also be used as the semiconductor layer of the present invention.

  Therefore, when the amorphous silicon film using Ge is crystallized as in this embodiment, there is no need to getter the catalytic element after crystallization. Of course, a gettering step may be performed, but the TFT characteristics are not affected.

Accordingly, the heat treatment in the gettering process can be omitted, and the throughput of the manufacturing process is greatly improved. In addition, since TFTs using Si _x Ge _1-x films are known to exhibit high mobility, if the Ge content in the silicon film is appropriate, an improvement in operating speed can be expected.

  Note that the configuration of this embodiment can be applied to any of the configurations of the first to fifth embodiments.

  [Embodiment 7] In this embodiment, an example will be described in which a device for controlling the threshold voltage is applied to the TFT of the present invention.

  In order to control the threshold voltage, an element selected from group 13 (typically boron, indium, gallium) or group 15 (typically phosphorus, arsenic, antimony) is added to the channel formation region. The technique is called channel doping.

  Channel doping is effective for the present invention, and the following two methods may be simple.

  First, at the time of forming an amorphous silicon film, a gas containing impurities for controlling a threshold voltage (for example, diborane, phosphine, etc.) is mixed in a film forming gas, and a predetermined amount is included simultaneously with film formation. There is. In this case, it is not necessary to increase the number of processes at all, but since the same concentration is added to both the N-type and P-type TFTs, it is not possible to meet the demand for different concentrations between the two.

  Next, after the channel etching step (channel forming region forming step) as described in FIG. 2D is completed, the channel forming region (or the channel forming region and the mask offset region) is formed using the source / drain electrodes as a mask. There is a method of selectively adding impurities.

  As an addition method, various methods such as an ion implantation method, an ion doping method, a plasma treatment method, a gas phase method (diffusion from an atmosphere), and a solid phase method (diffusion from the film) can be used. Since it is thin, a method that does not give damage, such as a gas phase method or a solid phase method, is preferable.

  Note that when an ion implantation method or the like is used, damage to the channel formation region can be reduced if a protective film that covers the entire TFT is provided.

  Further, after the impurity is added, an impurity activation step is performed by laser annealing, lamp annealing, furnace annealing, or a combination thereof. At this time, the damage received by the channel formation region is almost recovered.

When this embodiment is implemented, the channel formation region has a threshold of 1 × 10 ¹⁵ to 5 × 10 ¹⁸ atoms / cm ³ (typically 1 × 10 ¹⁵ to 5 × 10 ¹⁷ atoms / cm ³ ). An impurity for controlling the value voltage may be added.

  When this embodiment is applied to the TFT of the present invention, the threshold voltage of the N-channel TFT can be kept in the range of 0.5 to 2.5V. When applied to a P-channel TFT, the threshold voltage can be kept within the range of -0.1 to -2.0V.

  In addition, the structure of a present Example can be combined with any structure of Examples 1-6. Further, when applied to the CMOS circuit of Example 5, the N-type TFT and the P-type TFT can have different addition concentrations and different types of impurities to be added.

  Example 8 In the structure shown in FIG. 2D, the source electrode 113 and the drain electrode 114 are formed so as to completely surround the island-like semiconductor layer. In this embodiment, a configuration different from this will be described.

  The structure shown in FIG. 10A is basically similar to FIG. 2D, but is characterized in that the shapes of the source electrode 11 and the drain electrode 12 are different. That is, in part, the source electrode 11 and the drain electrode 12 are formed inside the island-shaped semiconductor layer (strictly, the source / drain region) by a distance indicated by a.

  A region indicated by 13 is a region having the same film thickness as the channel formation region 14 and has a width of a distance a. Although schematically shown in the drawing, the distance a is 1 to 300 μm (typically 10 to 200 μm).

  Here, the characteristics of this embodiment will be described in the light of the manufacturing process. In this embodiment, the source electrode 11 and the drain electrode 12 are formed as shown in FIG. Here, 15 is an island-like semiconductor layer, and the end 16 is exposed.

  When the channel etch process is performed in this state, the island-like semiconductor layer 15 is etched in a self-aligning manner using the source electrode 11 and the drain electrode 12 as a mask. In this case, the end portion 16 is also etched at the same time.

  In this way, a structure as shown in FIG. Therefore, it is clear that the end portion 16 has the same film thickness as the channel formation region 14.

There are the following two reasons for forming the protruding portion 13 of the island-like semiconductor layer.
(1) Used as an etching monitor in a channel etch process.
(2) When a protective film or an interlayer insulating film is formed in a later process, coverage defects due to steps in the island-shaped semiconductor layer are reduced.

  The etching monitor is used when inspecting whether or not the channel formation region has an appropriate film thickness by sampling inspection in the manufacturing process.

  In addition, the structure of a present Example can be combined with any structure of Examples 1-7.

  [Embodiment 9] In this embodiment, an example of the circuit configuration of the CMOS circuit (inverter circuit) shown in Embodiment 5 will be described with reference to FIG.

  FIG. 11A shows a CMOS circuit having the same structure as that shown in FIG. In this case, the circuit configuration includes a gate electrode 20, an N-type TFT semiconductor layer 21, a P-type TFT semiconductor layer 22, an N-type TFT source electrode 23, a P-type TFT source electrode 24, and a common drain electrode 25. .

  Note that the terminal portions a, b, c, and d correspond to the terminal portions a, b, c, and d of the inverter circuit shown in FIG.

  Next, FIG. 11B shows an example in which a semiconductor layer serving as a drain region is shared between an N-type TFT and a P-type TFT. Each code corresponds to the code described in FIG.

  In the structure shown in FIG. 11B, TFTs can be formed at a very high density, which is very effective when a circuit is highly integrated. The common semiconductor layer forms a PN junction, but this is not a problem.

  [Embodiment 10] In this embodiment, an example in which lamp annealing is used as a heat treatment means in the process of manufacturing TFTs and CMOS circuits having the configurations of Embodiments 1 to 5 will be described.

  As lamp annealing, heat treatment by RTA (Rapid Thermal Anneal) is known. This is a technique for performing high-temperature heat treatment in a short time (several seconds to several tens of seconds) by irradiating strong light from an infrared lamp, and has a very high throughput. In addition to infrared light, ultraviolet light may be supplementarily used.

  In the present invention, heat treatment is performed in the crystallization process of the amorphous semiconductor film, the crystallinity improvement process of the crystalline semiconductor film, the gettering process of the catalytic element, the impurity activation process for threshold control, and the like. . In this case, the present embodiment can be used.

  Note that the configuration of this embodiment and the configurations of other embodiments can be freely combined.

  [Embodiment 11] In this embodiment, a case where gettering of a catalytic element is performed by means different from Embodiment 1 will be described.

  In Example 1, the gettering process is performed using only elements selected from Group 15, but the gettering process for the catalytic element is performed even when an element selected from Groups 13 and 15 is added. be able to.

  In that case, after obtaining the state shown in FIG. 1E, only the region to be an N-channel TFT is hidden with a resist mask, and then boron is added. That is, only phosphorus exists in a region to be an N-channel TFT, and only boron exists in a region to be a P-channel TFT.

  Then, heat treatment may be performed in that state to perform a catalyst element gettering step. In our experiment, it has been confirmed that the gettering effect by phosphorus + boron is higher than the gettering effect by phosphorus alone. However, there was no gettering effect with boron alone, and a high gettering effect was obtained when the combination of boron and phosphorus at a higher concentration than phosphorus was used.

  Note that the configuration of this embodiment and the configurations of other embodiments can be freely combined.

[Example 12] When a quartz substrate or a silicon substrate having high heat resistance is used as a substrate, before forming the n ⁺ conductive layer and the n ⁻ conductive layer, about 700 to 1100 ° C. in an oxidizing atmosphere containing a halogen element It is also effective to perform the heat treatment. This is a technique that utilizes the gettering effect of metal elements by halogen elements.

  Further, by using this technique in combination with the gettering process as shown in Embodiment 11, the catalytic element used for crystallization of the amorphous semiconductor film can be removed more thoroughly. In this way, a highly reliable semiconductor device can be obtained if the catalytic element is thoroughly removed from at least the channel formation region.

  [Embodiment 13] In this embodiment, the TFT described in Embodiments 1 to 4 is applied to a pixel TFT of a pixel matrix circuit. Here, the TFT has an offset structure and an overlap structure shown in Embodiment 4. Is a composite structure.

  FIG. 12 is a schematic plan view of one pixel of the pixel matrix circuit of this embodiment, and FIG. 13 is a cross-sectional view. In each pixel of the pixel matrix circuit, a pixel TFT and an auxiliary capacitor are formed. In the pixel matrix circuit, a plurality of gate wirings 1010 for inputting signals for controlling on / off of the pixel TFTs are arranged in parallel in the X direction, and a plurality of source wirings 1020 for inputting image signals are provided in the Y direction. Are arranged in parallel with each other.

  Since the manufacturing process of the pixel matrix circuit is manufactured under the same process conditions as in the first embodiment, the description of the manufacturing process in this embodiment is simplified. A base film 1102 made of a silicon oxide film is formed on the surface of the glass substrate 1101. On the base film 1102, the gate wiring 1010 and the capacitor wiring 30 are formed in parallel with the gate wiring 1010 as the first layer wiring. As the conductive film constituting the first wiring layer, a multilayer film composed of a TaN film in the lower layer and a Ta film in the upper layer is used. The gate wiring 1010 is integrally formed with TFT gate electrodes 1011 and 1012, and the capacitor wiring 1030 is integrally formed with a capacitor electrode 1031 which is a lower electrode of the auxiliary capacitor.

  A gate insulating layer made of the silicon nitride film 1103 and the silicon nitride oxide film 1104 is formed on the first layer wiring / electrode. On the insulating layers 1103 and 1104, a semiconductor layer 1041 of the pixel TFT is formed. In this embodiment, the pixel TFT is a so-called multigate type in which a TFT having a gate electrode 1011 and a TFT having a gate electrode 1012 are connected in series to reduce leakage current.

  As the second-layer wiring, a source wiring 1020, a source electrode 1021, a drain electrode 1022, and a mask electrode 1023 made of a Ti / Al / Ti laminated film are formed. The source electrode 1021 is formed integrally with the data wiring 1020. The source wiring 1020 is arranged so as to form a lattice with respect to the gate wiring 1010 and the capacitor wiring 1030, and is insulated from these wirings 1010 and 1030 only by the gate insulating layer.

  Therefore, in order to reduce the parasitic capacitance between the first-layer wirings 1010 and 1030 and the second-layer wiring 1020, the thickness of the gate insulating layer is made thicker than that of the top gate type TFT. Here, the thickness is 0.3 to 0.8 μm, typically 0.4 to 0.5 μm. Therefore, the thickness of the first silicon nitride film 1103 constituting the gate insulating layer is set to 0 to 500 nm, typically 25 to 300 nm. The thickness of the second layer silicon nitride oxide film (or silicon oxide film) 1104 is 0 to 800 nm, typically 150 to 500 nm. Here, the thickness of the silicon nitride film 1103 is 150 nm, and the thickness of the silicon nitride oxide film 1104 is 300 nm.

  Channel etching is performed on the semiconductor layer 1041 of the pixel TFT using the second-layer electrodes 1021, 1022, and 1023 as a mask. The potential of the mask electrode 1023 is set to a floating state, and does not have a function of applying a voltage to the semiconductor layer 1041, but functions as a mask during a channel etch process. Here, the source electrode 1021 and the drain electrode 1022 are offset with respect to the gate electrodes 1011 and 1021, while the mask electrode 23 is formed so as to overlap the gate electrodes 1011 and 1021.

  In this structure, the offset type HRD described in the first embodiment is formed in the source region and the drain region, and measures against high breakdown voltage are taken. On the other hand, the impurity region under the mask electrode 1023 corresponds to a connecting portion of two TFTs, and functions only as a carrier path. Therefore, high mobility is given the highest priority. Therefore, the overlap type HRD region described in the second embodiment is provided in the impurity region to improve the mobility.

  In the pixel matrix circuit, since the voltage is applied to the pixel electrode so that the polarities are alternately reversed, it is preferable that the characteristics of the pixel TFT be equal to both positive and negative voltages. In this embodiment, the length of the offset region formed in the source region and the drain region is designed to be equal, and the length of the overlap region formed on both sides of the mask electrode 1023 is designed to be equal.

  As shown in the first and second embodiments, the offset length and the overlap length are determined by the wiring pattern of the first layer and the second layer, and can be 0.3 to 3 μm, respectively. Here, the offset length and the overlap length are each 1 μm. In the case of the pixel TFT, the channel width and the channel length are set to 1 to 10 μm. Here, the channel width is 5 μm and the channel length is 3 μm. In order to set the channel length to 3 μm, the width of the gate electrodes 1011 and 1012 is set to 3 μm. The overlap length on both sides of the mask electrode 1023 may be zero as shown in the third embodiment.

  Since the mask electrode 1023 is disposed so as to overlap the gate electrodes 1011 and 1021, the mask electrode 1023 is smaller than the width of the semiconductor layer 1041 in order to reduce the parasitic capacitance between the mask electrode 1023 and the gate electrodes 1011 and 1012. Also narrow.

  On the other hand, in the auxiliary capacitor, the drain electrode 1022 is formed to face the capacitor electrode 1031. With this structure, an auxiliary capacitor is formed in which the drain electrode 1022 and the capacitor electrode 1031 are counter electrodes and the gate insulating layers 1103 and 1104 are dielectrics. As shown in Embodiment 1, it is obvious that the pixel TFT can be formed with four masks, and even if the auxiliary capacitor 1030 is added, only the mask pattern is changed, and the number of masks does not increase. This means that the throughput and yield are drastically improved considering that six masks are required to manufacture only the conventional channel stop type TFT.

  A protective film 1116 made of silicon nitride oxide or silicon nitride having a thickness of 100 to 250 nm is formed to cover the pixel TFT and the auxiliary capacitor. Here, a silicon nitride oxide film having a thickness of 200 nm is formed.

  An interlayer insulating film 1130 having a thickness of 0.8 to 1.5 μm is formed on the protective film 1116 and serves as a base for the pixel electrode 1050. The interlayer insulating film 1130 is preferably a coating film that can obtain a flat surface. As one of the coating films, a resin film such as polyimide, polyamide, polyimide amide, or acrylic, or a silicon oxide based coating film such as PSG or silicon oxide can be used. In this embodiment, an acrylic resin film having a thickness of 1.0 μm is formed as the interlayer insulating film 1130.

  Then, a contact hole reaching the drain electrode 1022 is formed in the interlayer insulating film 1130 and the protective film 1117. Here, the number of masks is five. Next, an ITO film having a thickness of 100 to 150 nm is formed as a transparent conductive film. Here, the pixel electrode 1050 is formed by patterning with a thickness of 120 nm and patterning. This makes the number of masks six. The pixel matrix circuit is completed through the above steps. Note that the reflective electrode may be manufactured using the pixel electrode 1050 as a metal film such as Al.

  The auxiliary capacitor dielectric is a two-layer insulator of the silicon nitride film 1103 and the silicon nitride oxide film (silicon oxide film) 1104. However, it is possible to use only the lower silicon nitride film 1103. In this case, after the patterning of the island-shaped semiconductor layer shown in FIG. 2B, the silicon nitride oxide film 1104 exposed using the semiconductor layer as a mask is removed by etching, and then the second-layer wiring is formed. A source wiring 1020 and electrodes 1021, 1022, and 1023 are formed. However, in order to etch the silicon nitride oxide film 1104, it is necessary to use an etching gas or an etchant in which the silicon nitride film 1103 functions as an etching stopper. It is also effective to adjust the composition so that the silicon nitride oxide film 1104 can be etched more easily or to form a silicon oxide film instead of the silicon nitride oxide film.

  As described in the fifth and ninth embodiments, an inverter circuit composed of an n-channel pixel TFT and a CMOS TFT can be formed at the same time. Using this technique, a peripheral drive circuit for driving the pixel matrix circuit is also formed on the same substrate 1101, although not shown. Since TFTs arranged in the peripheral driver circuit give priority to high-speed operation, the source / drain regions are preferably overlapped.

  Although the pixel TFT of this embodiment is a multi-gate type having two gate electrodes, the number of gate electrodes is not limited to two but can be one or two or more. Regardless of the number of gate electrodes, the source and drain regions to which a voltage is applied by the source wiring 1020 and the pixel electrode 1050 should have an offset structure to take measures against high breakdown voltage. When the number of gates is 2 or more, impurity regions other than the source and drain regions are formed in the semiconductor layer. These impurity regions overlap the gate electrode or as shown in the third embodiment. Preferably, the offset length and the overlap length are formed to be zero, and high mobility is given priority.

  [Embodiment 14] In this embodiment, a modification of the auxiliary capacitor of Embodiment 13 is shown. FIG. 14 shows a cross-sectional view of the pixel matrix circuit of this embodiment. In FIG. 14, the same reference numerals as those in FIGS. 12 and 13 are the same constituent elements as those in the embodiment 13, and the difference from the embodiment 13 is the pattern of the semiconductor layer 1241 and the drain electrode 1222 of the pixel TFT.

  In this embodiment, the island-shaped semiconductor layer shown in FIG. 2B is formed by a patterning process so that the semiconductor layer faces the capacitor electrode 31. Then, the drain electrode 1222 is formed so as to partially overlap the capacitor electrode 1031. Channel etching is performed on the island-shaped semiconductor layer using the electrodes 1021, 1023, and 1222 as a mask. As a result, an i-type region 1242 including an intrinsic or substantially intrinsic i layer is formed on the capacitor electrode 1031 by channel etching of the semiconductor layer 1241. This i-type region 1242 has substantially the same thickness as the channel formation region of the pixel TFT and has the same function.

When a voltage is applied by the capacitor electrode 1031, a channel is formed in the i-type region 1242. Further, a channel is also formed in the i layer of the semiconductor layer 1241 where the drain electrode 1222 and the capacitor electrode 1031 overlap, that is, the mask overlap region in FIG. These channels function as the upper electrode of the auxiliary capacitor. The connection structure between the upper electrode of the auxiliary capacitor and the pixel electrode 1050 is the same as the connection structure between the channel formation region and the drain electrode shown in FIG. Referring to FIG. 5, an i-type region 1242 (503) composed of an i layer, a mask overlap region (504), an LDD region (505) composed of an n ⁻ layer, an n ⁺ layer (506), and a drain electrode 1222 (502) And the pixel electrode 1050 in this order.

  Here, it is preferable to set the mask overlap region length so that the main part of the upper electrode of the auxiliary capacitor becomes the i-type region 1242, which is about 0.3 to 3 μm. The reason why the drain electrode 1222 and the capacitor electrode 1031 are overlapped is to reduce the resistance between the pixel electrodes 1050 and the upper electrode of the auxiliary capacitor. In order to form a channel with a lower voltage by the i-type region 1224, it is preferable to take the threshold control measures shown in the seventh embodiment.

  Example 15 FIG. 15 is a cross-sectional view of a pixel matrix circuit of this example. In this embodiment, an i layer of the semiconductor layer of the pixel TFT is used as the upper electrode of the auxiliary capacitor as in the case of the embodiment 14. In FIG. 15, the same reference numerals as those in FIG. 14 are the same components as those in the fourteenth embodiment. What is different from the fourteenth embodiment is the pattern of the semiconductor layer 1341 and the drain electrode 1322 of the pixel TFT.

  In Example 14, channel etching is performed on the semiconductor layer 1241 facing the capacitor electrode 1031, but in this embodiment, channel etching is not performed on the semiconductor layer 1341 facing the capacitor electrode. Therefore, the drain electrode 1322 is formed so as to cover the surface of the semiconductor layer 1342 facing the capacitor electrode 1031.

In this structure, the upper electrode of the auxiliary capacitor becomes a channel formed in the i layer of the semiconductor layer 1342 by the voltage of the capacitor electrode 1031. The region where the channel is formed corresponds to the overlap region 504 (see FIG. 5) described in the second embodiment. Accordingly, referring to FIG. 5, the connection structure between the upper electrode of the auxiliary capacitor and the pixel electrode 1050 is the mask overlap region (504) made of i layer, the LDD region (505) made of n ⁻ layer, and the n ⁺ layer (506). The drain electrode 1322 (502) and the pixel electrode 1050 are arranged in this order.

  In order to form a channel with a low voltage by the i layer (mask overlap region) of the semiconductor layer 1341 serving as the auxiliary capacitor and the upper electrode, it is preferable to take measures against the threshold control described in the seventh embodiment.

  Example 16 FIG. 16 is a cross-sectional view of a pixel matrix circuit of this example. This embodiment is a modification of the fifteenth embodiment. In FIG. 16, the same reference numerals as those in FIG. 15 denote the same constituent elements as in the embodiment 15. The difference from the embodiment 15 is that in the pixel TFT, the pattern of the semiconductor layer 1441 and the drain electrode 1422 and the connection of the pixel electrode 1450 In addition, in the auxiliary capacitor, the semiconductor layer 1442 and the second-layer electrode 1424 are formed separately from the pixel TFT.

  In this embodiment, in the island-shaped semiconductor layer patterning step shown in FIG. 2B, an island-shaped region serving as a prototype of the semiconductor layer 1441 of the pixel TFT and a semiconductor layer 1442 of an auxiliary capacitor are formed. Next, a second-layer wiring source electrode 1022, mask electrode 1023, drain electrode 1422, and electrode 1424 are formed. The electrode 1424 covers the semiconductor layer 1424 so that the auxiliary capacitor semiconductor layer 1424 is not channel-etched. By performing channel etching, a semiconductor layer 1441 of the pixel TFT is formed.

  Next, a protective film 1116 and an interlayer insulating film 1130 are formed. A contact hole reaching the drain electrode 1422 and the auxiliary capacitance electrode 1424 is formed in the protective film 1116 and the interlayer insulating film 1130, and then the pixel electrode 1450 is formed. As shown in FIG. 16A, the pixel electrode 1450 is electrically connected to the drain electrode 1422 and the electrode 1422.

The structure of the auxiliary capacitor is substantially the same as that of the fifteenth embodiment, and the upper electrode of the auxiliary capacitor is a channel formed in the i layer of the semiconductor layer 1442. This i layer corresponds to the mask overlap region of FIG. The connection structure between the upper electrode of the auxiliary capacitor and the pixel electrode 1450 is that the semiconductor layer 1442 has an i-layer mask overlap region (504), an n ⁻ layer LDD region 505), an n ⁺ layer (506), and an electrode 1424 ( 502) and the pixel electrode 1450 in this order.

In this embodiment, the n ⁺ layer can function as an electrode. Therefore, as shown in FIG. 16B, in the step of forming a contact hole for the pixel electrode 1450, the electrode 1424 is also etched to connect the n ⁺ layer of the semiconductor layer 1424.

  In FIGS. 16A and 16B, the semiconductor layer 1442 is not subjected to channel etching, but the semiconductor layer is formed so as to cover at least the connection portion with the pixel electrode 1450 as shown in Example 8. A protruding portion may be formed on the side surface of 1442 to alleviate the step of the semiconductor layer 1442.

  [Embodiment 17] FIG. 17 shows a sectional view of a pixel matrix circuit of this embodiment. This embodiment is a modification of the sixteenth embodiment. In FIG. 17, the same reference numerals as those in FIG. 16 denote the same constituent elements as those in the sixteenth embodiment. The difference from the sixteenth embodiment is that the auxiliary capacitor semiconductor layer 1442 and the electrode 1424 in the sixteenth embodiment are not formed. This is a connection structure.

  In this embodiment, the pixel electrode 1550 is an upper electrode of an auxiliary capacitor. In the step of forming a contact hole for the pixel electrode 1550, the interlayer insulating film 1130, the protective film 1116 made of a silicon nitride oxide film, and the second layer 1104 of the gate insulating layer are etched. A silicon nitride film 1103 is formed as the first layer of the film.

  In this embodiment, a silicon nitride film 1103, a silicon nitride oxide film (silicon oxide film) 1104, and a protective film 1116 can be used as a dielectric of an auxiliary capacitor.

  For example, when the contact hole for the pixel electrode 1550 is formed, the mask pattern of the interlayer insulating film 1130 and the protective film 1116 is changed so that the protective film 1116 of the auxiliary capacitor contact hole is not removed. Three films can be used for the storage capacitor dielectric.

  For example, in the contact hole forming process using the protective film 1116 as a silicon nitride film, an etching gas or an etchant is used so that the second silicon oxynitride film (silicon oxide film) 1104 of the gate insulating layer serves as an etching stopper. For example, the silicon oxynitride film (silicon oxide film) 11140 and the silicon nitride film 1103 can be used as a storage capacitor dielectric.

  [Embodiment 18] This embodiment is a modification of Embodiment 17. In the seventeenth embodiment, the capacitor wiring 1030 is required separately from the gate wiring 1010 as the auxiliary capacitance electrode, but in this embodiment, an example in which the capacitive wiring is omitted is shown. FIG. 20 is a plan view of the pixel matrix circuit of this embodiment, and FIG. 18 is a schematic cross-sectional view. 20 and 18, the same reference numerals as those in FIG. 17 denote the same components.

  As shown in FIG. 20, gate electrodes 1211 and 1212 of the pixel TFT and an electrode 1231 of the auxiliary capacitor are integrally formed on the gate wiring 1210 of this embodiment. The point that the capacitor electrode 1231 and the pixel electrode 1231 are used as the auxiliary capacitor electrode is the same as that of the seventeenth embodiment, but the pixel electrode 1231 is opposed to the capacitor electrode 1231 formed on the gate wiring 1230 at the next stage or the previous stage.

  FIG. 18 corresponds to a cross-sectional view of a pixel having the pixel electrode 1650B. As shown in FIG. 20, the pixel electrode 1650B is opposed to the capacitor electrode 1231A formed on the gate wiring 1210A at the previous stage (next stage), and an auxiliary capacitor using the gate insulating layers 1103 and 1104 as a dielectric is formed. Further, the capacitor electrode 1231B formed on the gate wiring 1210B faces the pixel electrode 1650 of the next stage (previous stage).

  Further, the capacitor electrode 1231 of this embodiment can be applied when the pixel electrode has different connection portions between the drain electrode and the auxiliary capacitor, and can also be applied to the embodiment 16. FIGS. 19A and 19B are cross-sectional views of a pixel matrix circuit when this embodiment is applied to Embodiment 16 (FIG. 16). Note that FIG. 18 is applied to the reference numerals in FIG.

  [Embodiment 19] The material of the capacitor wirings / electrodes 1030 and 1031 which are the first-layer wirings is formed of a metal film that can be anodized, so that the surface of the capacitor electrode 1031 is anodized to form an anodized film. Can be formed. This anodic oxide film can be used as a dielectric for an auxiliary capacitor.

  A Ta film, a MoTa alloy film, or the like can be used as a metal film that can withstand the ring gettering process described in Embodiment 1 and can be anodized. The TaN / Ta laminated film used for the first wiring layer in this embodiment can also be anodized.

  For example, when this embodiment is applied to the pixel matrix circuit shown in FIGS. 17 and 18, in the step of forming contact holes for the pixel electrodes 1550 and 1650, the silicon nitride film 1103 is removed to remove the dielectric of the auxiliary capacitor. The body can only be an anodized film.

  [Embodiment 20] An electronic apparatus including the display device of this embodiment will be described with reference to FIG. In this embodiment, the AMLCD shown in the embodiment of the application product (electro-optical device) to which the liquid crystal display device according to the present invention can be applied is used for displays of various electronic devices. Note that the electronic device described in this embodiment refers to a product in which AMLCD is mounted as a display device.

Examples of the electrical engineering apparatus to which the present invention is applied include a video camera, a still camera, a projector, a head mounted display, a car navigation system, a personal computer, and a personal digital assistant (mobile computer, mobile phone).

  FIG. 21A illustrates a mobile computer, which includes a main body 001, a camera unit 2002, an image receiving unit 2003, operation switches 2004, and a display device 2005. The present invention is applied to the display device 2005.

  FIG. 21B illustrates a head mounted display which includes a main body 2201, a display device 102, and a band portion 2103. The present invention can be applied to the display device 2012.

  FIG. 21C illustrates a mobile phone, which includes a main body 2201, an audio output portion 2202, an audio input portion 2203, a display device 2204, operation switches 2205, and an antenna 2206. The present invention is applied to the display device 2204.

  FIG. 21D illustrates a video camera which includes a main body 2301, a display device 2302, an audio input portion 2303, operation switches 2304, a battery 2305, and an image receiving portion 2306. The present invention is applied to the display device 2302.

  FIG. 21E shows a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention is applied to the display device 2403.

  FIG. 21F shows a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention is applied to the display device 2502.

  As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices equipped with display devices in various fields. It can also be applied to electronic bulletin boards and display devices for advertising.

10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. FIG. 3 is an enlarged view illustrating a structure of a thin film transistor. The figure which shows the density | concentration profile in a film | membrane. FIG. 9 illustrates a structure of a thin film transistor. FIG. 9 illustrates a structure of a thin film transistor. FIG. 9 illustrates a structure of a thin film transistor. The figure which shows the structure of a CMOS circuit. The figure which shows the density | concentration profile in a film | membrane. FIG. 9 illustrates a structure of a thin film transistor. The figure which shows the structure of a CMOS circuit. The top view of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. Sectional drawing of 1 pixel of a pixel matrix circuit. The top view of 1 pixel of a pixel matrix circuit. FIG. 11 is a schematic diagram of an electronic device including a display device.

Explanation of symbols

101 Substrate 102 Base film 103 Gate electrode 104 Silicon nitride film 105 Silicon oxynitride film 106 Amorphous semiconductor film 107 Nickel-containing layer 108 Crystalline semiconductor film 109 Crystalline semiconductor film 110 n ⁺ layer (first conductive layer)
111 n ⁻ layer (second conductive layer)
112 Island-like semiconductor layer 113 Source electrode 114 Drain electrode 115 Channel etch region 116 Protective film 117 Channel formation region 118 Mask offset region 119 Contact hole

Claims (3)

A gate electrode formed on an insulating surface;
A gate insulating film formed to cover the gate electrode;
A crystalline semiconductor layer formed on the gate insulating film so as to cover the gate electrode;
A first stacked structure in which a first conductive layer, a third conductive layer, and a source electrode made of a metal film are stacked in this order on the crystalline semiconductor layer; a second conductive layer; a fourth conductive layer; A second stacked structure in which a drain electrode made of a metal film is stacked in this order;
A protective film provided on the crystalline semiconductor layer ,
One of the first laminated structure or the second laminated structure overlaps the gate electrode, and the other does not overlap the gate electrode,
The crystalline semiconductor layer includes a first region overlapping the first stacked structure, a second region overlapping the second stacked structure, the first stacked structure, and the second stacked structure. A third region that does not overlap the stacked structure;
The film thickness of the first region and the second region is larger than the film thickness of the third region,
The concentration of the impurity element imparting conductivity contained in the first conductive layer is lower than the concentration of the impurity element imparting conductivity contained in the third conductive layer,
The concentration of the impurity element imparting conductivity contained in the second conductive layer is lower than the concentration of the impurity element imparting conductivity contained in the fourth conductive layer,
The first conductive layer and the second conductive layer is seen containing a catalytic element,
An end portion of the crystalline semiconductor layer has a protruding portion covered with the protective film . In claim 1,
Of the third region of the crystalline semiconductor layer, a region not overlapping with the gate electrode functions as an offset region. In claim 2,
The semiconductor device, wherein the catalyst element is Ni, Ge, Pt, Co, Fe, Au, Pd, Pb, or Cu.

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