KR101930439B1 - Pixel - Google Patents

Abstract

The pixel includes an organic light emitting diode, a driving transistor for transmitting a driving current according to a data signal to the organic light emitting diode, and a wiring extending to overlap at least a first region of the semiconductor layer of the driving transistor.

Description

Pixel {PIXEL}

This disclosure relates to pixels.

Among the flat panel display devices, organic light emitting display devices display images using an organic light emitting diode that emits light by recombination of electrons and holes. The organic light emitting display device has a fast response speed, is driven at low power consumption, It has attracted attention because of its excellent viewing angle.

2. Description of the Related Art Conventionally, organic light emitting display devices are classified into a passive matrix type OLED (PMOLED) and an active matrix type OLED (AMOLED) according to a method of driving an organic light emitting diode.

Of these, an active matrix type OLED (AMOLED) which is selected and turned on for each unit pixel in view of resolution, contrast, and operation speed has become mainstream.

The performance of a flat panel display device is judged by various indicators. One of such indicators is evaluation for displaying a clear and clear image without a motion blur of a pattern when a moving picture or a text accompanying the moving picture is implemented.

The motion blur occurs due to the reaction rate of the liquid crystal in the case of a liquid crystal display (LCD).

However, in the case of an organic light emitting display device, since the principle of self-luminescence after exciting atoms of the organic light emitting layer does not occur, a motion blur due to the reaction speed does not occur. However, A motion blur occurs due to a delay in a response time due to the hysteresis characteristic of the hysteresis characteristic.

Specifically, in the organic light emitting diode display, the driving transistor transfers a driving current of a data voltage level according to a data signal to an organic light emitting layer. However, due to the hysteresis characteristic of the driving transistor, the gray level of current data may not be normally displayed. In particular, when the amount of current rapidly changes from a low gray level to a high gray level or from a high gray level to a low gray level, the current corresponding to the gray level change can not be properly transmitted due to hysteresis,

Therefore, it is necessary to research and improve the hysteresis characteristic of the driving transistor so that a sharp image of a high image quality is displayed by eliminating a drag phenomenon in an organic light emitting display device.

SUMMARY OF THE INVENTION The present invention provides a pixel with improved response time delay due to hysteresis.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

According to an aspect of the present invention, there is provided a pixel including an organic light emitting diode, a driving transistor for transmitting a driving current according to a data signal to the organic light emitting diode, .

 The pixel may further include an auxiliary transistor connected to one end connected to the wiring and supplying a predetermined first voltage to the wiring.

The pixel may further include a switching transistor connected to one end of the driving transistor and transmitting the data signal.

The pixel may further include a compensation transistor connected between the gate and the other terminal of the driving transistor and compensating for a threshold voltage of the driving transistor.

The pixel may further include an initialization transistor connected to a gate of the driving transistor and transmitting an initialization voltage to the gate of the driving transistor.

The present invention proposes a structure for improving the hysteresis characteristic of a thin film transistor, and it is an object of the present invention to provide a pixel having a driving transistor with improved response time and an organic light emitting diode have.

Particularly, there is a phenomenon that, when a frame is changed at an extreme luminance change such as Black to White, the luminance is maintained at an intermediate level and then white is displayed. Without changing the structure of the driving transistor, By improving the response time, the image can be displayed with the correct luminance. Due to the improvement of the structure of the driving transistor, the maximum PPI (pixel per inch) can be realized according to the pixel structure and the driving method.

1 is a schematic diagram illustrating a thin film transistor according to an embodiment of the present invention.
FIG. 2 is a layout diagram showing a structure of a thin film transistor according to an embodiment of the present invention. FIG.
3 is a cross-sectional view illustrating a cross-sectional structure of a thin film transistor corresponding to a solid line AA 'in the layout diagram of FIG.
4 is a cross-sectional view showing a cross-sectional structure of a thin film transistor corresponding to a solid line BB 'in the layout diagram of FIG. 2;
FIG. 5 and FIG. 6 are arrangement views showing the structure of a thin film transistor according to another embodiment of FIG. 2;
FIGS. 7 to 9 are layouts illustrating a structure of a thin film transistor according to another embodiment of the present invention. FIG.
10 is a layout view showing the structure of a thin film transistor according to another embodiment of the present invention.
11 is a circuit diagram illustrating a pixel structure to which a structure of a thin film transistor according to an embodiment of the present invention is applied.
12 is a circuit diagram showing a basic structure (6TR structure) of a conventional pixel.
FIG. 13 is a block diagram of an OLED display including a pixel having a thin film transistor according to an embodiment of the present invention. FIG.
14 is a timing chart showing a pixel driving operation of the organic light emitting diode display shown in FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In addition, in the various embodiments, components having the same configuration are represented by the same reference symbols in the first embodiment, and only the configuration other than the first embodiment will be described in the other embodiments.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

FIG. 1 is a schematic diagram illustrating a thin film transistor according to an embodiment of the present invention. Referring to FIG.

In general, a thin film transistor (TFT) is applied from a MOSFET, but unlike a metal-oxide-semiconductor (MOS) transistor, a bulk terminal is not used. A gate terminal, and a drain terminal. The main function of the thin film transistor is a switching operation, in which a current flowing between a source and a drain is switched to an ON state or an OFF state by controlling a voltage applied to a gate which is a third electrode.

Each pixel of the organic light emitting display of the active matrix controls the amount of driving current of the OLED by the thin film transistor included in the pixel and is emitted with the luminance corresponding to the data signal transmitted to each pixel.

In particular, a driving thin film transistor for controlling a driving current transmitted to an organic light emitting layer in each of a plurality of pixels of an organic light emitting display has a hysteresis characteristic according to a driving current change between a previous frame and a current frame in gradation representation according to a data voltage, It is causing dragging in expression.

1, a thin film transistor according to an embodiment of the present invention includes a bias electrode connected to a channel region between a source terminal and a drain terminal, Add a terminal.

Referring to FIG. 1, a thin film transistor has a P-type structure, but the present invention is not limited thereto. It is needless to say that a Bias terminal can be connected to an N-type thin film transistor.

FIG. 2 is a layout diagram showing a layout structure of a thin film transistor according to an embodiment of the present invention, particularly showing a layout of the thin film transistor shown in FIG. 1. FIG.

In the layout structure of FIG. 2, the structure of the lowest transparent insulating substrate and the buffer layer that can be laminated thereon is omitted, and the semiconductor layer 10 used as the active layer is indicated.

The semiconductor layer 10 is an active layer including a region into which P-type or N-type semiconductor impurity ions are introduced and a region in which no impurity ions are implanted.

Specifically, the lower region of the region where the source electrode 20 and the drain electrode 30 are respectively located is a semiconductor layer region doped with P-type or N-type semiconductor impurity ions. The semiconductor layer region connected to the source electrode 20 is referred to as a source region and the semiconductor layer region to which the drain electrode 30 is connected is referred to as a drain region. A region between the source region and the drain region in the semiconductor layer 10, where the semiconductor impurity is not implanted, is referred to as a channel region.

Although the shape of the semiconductor layer 10 is not particularly limited, the shape of the semiconductor layer 10 according to an embodiment of the present invention may be a T-shape in which a part of the channel region except the source region and the drain region is protruded . Hereinafter, the protruded channel region portion is referred to as a bias terminal connection portion.

A region directly connected to the bias electrode 60 through the contact hole 61 among the protruded channel regions of the semiconductor layer 10 is called a bias region.

Referring to FIG. 2, a gate metal layer 40 is stacked on the semiconductor layer 10. Specifically, the gate metal layer 40 is stacked on top of the channel region of the semiconductor layer 10 to which the impurity ions are not doped.

Although not shown in FIG. 2, an insulating layer made of an insulating material is provided between the semiconductor layer 10 and the gate metal layer 40 so as not to electrically conduct.

An intermediate layer (not shown) is formed as an insulating layer on the substrate including the gate metal layer 40, and then each electrode is formed.

A source electrode 20 connected to a source region of the semiconductor layer 10, a drain electrode 30 connected to a drain region of the semiconductor layer 10, a bias electrode connected to a bias region of the semiconductor layer 10 60, and a gate electrode 50 connected to the gate metal layer 40 are formed.

The source electrode 20, the drain electrode 30 and the bias electrode 60 are connected to the semiconductor layer 10 through the contact holes 21, 31 and 61 formed by etching the intermediate layer and the gate insulating layer. The gate electrode 50 is connected to the gate metal layer 40 through the contact hole 51 etched by patterning the intermediate layer.

The structure of the thin film transistor according to one embodiment of the present invention according to the structure of FIG. 2 is specifically understood by referring to FIGS. 3 and 4 which are sectional views corresponding to the solid lines A-A 'and B-B' shown in the layout layout diagram of FIG. .

3 is a cross-sectional view showing a cross-sectional structure of the thin film transistor corresponding to the solid line A-A 'in the layout diagram of FIG.

That is, it is a cross-sectional structure of a thin film transistor corresponding to the A-A 'solid line passing through the source electrode 20, the gate electrode 50, and the drain electrode 30.

Referring to FIG. 3, a step of forming a thin film transistor according to an embodiment of the present invention can be seen.

A semiconductor layer 110 doped with semiconductor impurity ions is formed on a substrate 100. The substrate 100 may be formed of a transparent insulating substrate such as a glass substrate, but this is only one embodiment and is not necessarily limited.

The semiconductor layer 110 is formed by forming an amorphous silicon film on the substrate 100 and patterning the amorphous silicon film by an etching process. The formation of the amorphous silicon film is only an example and may be formed of a polysilicon film. The semiconductor layer 110 is formed of a source region 110S and a drain region 110D doped with semiconductor impurity ions and a channel region 110C doped with semiconductor dopant ions.

The doping method and order of the impurity ions are not particularly limited and the impurity ions may be firstly classified according to the layering method of the thin film transistor and then impurity ions may be implanted using the gate metal layer 140, can do.

The gate insulating layer 115 is formed on the substrate on which the semiconductor layer 110 is formed. The gate insulating layer 115 is a layer for preventing electrical conduction between the semiconductor layer 110 and the gate metal layer 140 formed later, and is not limited to a specific material, and may be formed using a conventional insulating material .

After the gate insulating layer 115 is formed, a gate metal layer 140 is formed on a predetermined region of the region where the semiconductor layer 110 is located. The gate metal layer 140 may be formed on a predetermined region of the channel region 110C between the source region 110S and the drain region 110D of the semiconductor layer 110. [

A gate insulating layer 115 and a gate metal layer 140 are formed and then etched and patterned using the gate metal layer 140 as a mask and then patterned to form a source of the semiconductor layer 110. [ A process of doping the region 110S and the drain region 110D with an impurity ion can be performed.

The gate metal layer 140 may be made of a metal material, but may be made of a metal material such as MoW, Al or the like in consideration of adhesion with an adjacent layer, surface flatness of a layer to be laminated, and workability.

An intermediate layer 145 as an insulating layer is formed on at least one layer on the gate insulating layer 115 on which the gate metal layer 140 and the gate metal layer 140 are stacked. The material constituting the intermediate layer 145 is not particularly limited and may be composed of a conventional insulating material.

A predetermined region of the intermediate layer 145 and the gate insulating layer 115 is etched to expose a part of the source region 110S and the drain region 110D of the semiconductor layer 110 Thereby forming a contact hole. That is, a source region contact hole 121 exposing the source region 110S of the semiconductor layer 110 and a drain region contact hole 131 exposing the drain region 110D of the semiconductor layer 110 are formed.

A source electrode 120 and a drain electrode 130 are formed on the source region contact hole 121 and the drain region contact hole 131, respectively.

The source electrode 120 and the drain electrode 130 may be formed of a metal material that is electrically conductive, and may be formed of a metal such as MoW, but the present invention is not limited thereto. The source electrode 120 and the drain electrode 130 may be subsequently annealed to form a smooth ohmic contact with the semiconductor layer 110.

A predetermined region of the intermediate layer 145 formed on the gate metal layer 140 is etched to form a gate region contact hole 151 in which the gate metal layer 140 is exposed. A gate electrode 150 is formed on the gate region contact hole 151.

4 is a cross-sectional view of the thin film transistor corresponding to the solid line B-B 'in the layout diagram of FIG. 2, and is a cross-sectional view corresponding to the solid line B-B' passing through the gate electrode 50 and the bias electrode 60.

4, the layers constituting the thin film transistor of the present invention include a semiconductor layer 210, a gate insulating layer 215, a gate metal layer 240, an intermediate layer 245, and electrodes formed on a substrate 200, 3, and thus a detailed description thereof will be omitted.

4 is a sectional view of the thin film transistor with respect to a solid line passing through the bias electrode 260 and the gate electrode 250. The bias electrode 260 formed on the intermediate layer 245 is electrically connected to the semiconductor layer 210 through the bias contact hole 261. [ ).

In particular, the semiconductor layer 210 connected to the bias electrode 260 corresponds to the bias region defined above. The bias region of the semiconductor layer 210 corresponds to a channel region in which the gate metal layer 240 is stacked with the gate insulating layer 215 interposed therebetween. According to an embodiment of the present invention, an auxiliary voltage applied through the bias electrode 260 is transferred to the channel region of the semiconductor layer 210.

The bias contact hole 261 is formed by simultaneously etching the intermediate layer 245 and the gate insulating layer 215 so that a part of the bias region of the semiconductor layer 210 is exposed.

The gate electrode 250 is formed after the gate contact hole 251 is formed so as to expose the gate metal layer 240. The gate contact hole 251 is formed in the middle layer 245 And etching a part of the region where the gate metal layer 240 is located in the lower part of the region.

In addition to the structure of the thin film transistor according to the embodiment of FIG. 2, various structures can be formed. FIGS. 5 and 6 are embodiments of other structures.

5 and 6, the protruding portion of the channel region of the semiconductor layer 10 formed in the T-shape, that is, the bias terminal connection portion, is not located at the center as shown in FIG. 2, to be. However, the bias terminal connection portion is formed so as not to overlap the source region or the drain region of the semiconductor layer 10 without deviating from the width of the channel region of the semiconductor layer 10.

5 and 6, the bias electrode 60 is formed on the bias terminal connection portion of the semiconductor layer 10 and is contacted through the contact hole 61. Accordingly, an auxiliary voltage applied to the bias electrode 60 is transferred to the channel region of the semiconductor layer 10 through the bias terminal connection portion biased toward the source region or the drain region of the semiconductor layer 10.

7 to 9 illustrate the structure of a thin film transistor according to another embodiment of the present invention. As compared with the structure of the thin film transistor of FIGS. 2, 5, and 6, It can be seen that the width of the bias region of the layer 10 is smaller than the width 100 of the channel region of the semiconductor layer 10.

More specifically, the width 100 of the bias terminal connection portion of the semiconductor layer 10 in the thin film transistor of FIGS. 7 to 9 is wider than the width of the bias terminal connection portion of the thin film transistor of FIGS. 2, 5, and 6. Therefore, the width of the bias region of the semiconductor layer 10 to which the bias electrode 60 is directly connected is configured to be smaller than the width 100 of the bias terminal connection portion.

7 to 9 can improve the process convenience by forming the channel region of the semiconductor layer 10 relatively wide in width, and the predetermined voltage transmitted through the channel region and the subsequent bias region becomes more It can be a configuration that can be easily transmitted.

7 to 9, the width 100 of the bias terminal connection portion is not particularly limited, but is preferably at least the width of the bias region of the semiconductor layer 10 or the width of the bias electrode 60, As shown in FIG.

Here, the length of the channel region means the length of the remaining length of the source region and the drain region in the entire length of the semiconductor layer 10.

7, the width 100 of the bias terminal connection portion is extended in the direction of the source electrode 20 with respect to the gate electrode 50.

The structure of the thin film transistor of FIG. 8 is such that the width 100 of the bias terminal connection portion extends equally in both the direction of the source electrode 20 and the direction of the drain electrode 30 with respect to the gate electrode 50.

9, the width 100 of the bias terminal connection portion is extended in the direction of the drain electrode 30 with respect to the gate electrode 50.

7 to 9 illustrate one embodiment of the present invention. Therefore, it is needless to say that various embodiments are possible as the extended width of the bias terminal connection portion.

10 is a layout diagram showing the structure of a thin film transistor according to another embodiment of the present invention.

10, unlike the thin film transistor according to the embodiments of the present invention, at least one bias electrode B2 is additionally provided in addition to one bias electrode B1 connected to a bias region following a channel region of the semiconductor layer As shown in FIG.

That is, the shape of the semiconductor layer 10 is not a T shape but a roughly positive shape.

And has a channel region protruding upward and downward with respect to a channel region where a source region and a drain region are formed at the ends of the semiconductor layer 10.

10, an upper protruding portion (referred to as a first bias terminal connecting portion) 65-2 of the channel region of the semiconductor layer 10 on which the source electrode 20 and the drain electrode 30 are formed A first bias electrode 65 is formed on the first bias region 65-1 connected thereto. A second bias electrode 67 is formed on the second bias region 67-1 connected to the lower protruded portion (referred to as a second bias terminal connection portion) 67-2 of the channel region of the semiconductor layer 10, .

More specifically, the first bias electrode 65 is connected to the first bias region 65-1 of the semiconductor layer 10 through the bias contact hole 66. The first bias region 65-1 is connected to the channel region through the first bias terminal connection portion 65-2.

On the other hand, the second bias electrode 67 is connected to the second bias region 67-1 of the semiconductor layer 10 through the bias contact hole 68. The second bias region 67-1 is connected to the channel region through the second bias terminal connection portion 67-2.

At this time, the widths of the first bias terminal connection portion 65-2 and the second bias terminal connection portion 67-2 are not particularly limited, but the widths of the bias regions 65-1 and 67-1 As shown in FIG.

10, since the widths of the first bias terminal connection portion 65-2 and the second bias terminal connection portion 67-2 are extended, the gate electrode 50 is formed in the direction of the source electrode 20, May be formed to be biased toward the electrode (30).

In FIG. 10, the additional bias electrode B2 is formed as one electrode. However, the present invention is not limited thereto.

10, by forming at least one bias electrode in the thin film transistor of the present invention, a predetermined bias voltage can be more accurately and reliably applied to the channel region of the semiconductor layer before the data signal is written I will.

11 is a circuit diagram illustrating a pixel structure in which the structure of a thin film transistor according to an embodiment of the present invention is applied. Concretely, the driving transistor M1 for supplying the driving current according to the predetermined data signal among the thin film transistors M1 to M7 constituting the circuit diagram of Fig. 11 is constituted by the above-mentioned thin film transistor of the present invention. That is, in the circuit diagram of FIG. 11, the thin film transistors M2 to M7 are all thin film transistors having a three-terminal structure of gate, source, and drain. The driving transistor M1 is a thin film transistor of the present invention having a four terminal structure of gate, source, Transistors.

The pixel according to an exemplary embodiment of the present invention includes a first scan line for transmitting a first scan signal Scan [n] for activating a pixel to transfer a data signal, Source voltage and the source-drain voltage of the driving transistor Ml to a constant voltage by applying the initializing voltage Vint to the bias electrode of the driving transistor Ml and applying the auxiliary voltage Vsus to the bias electrode of the driving transistor Ml And the second scanning line Scna [n-1] for controlling the scanning lines Scna [n-1].

Further, the pixel according to an embodiment of the present invention transmits a corresponding data line for transmitting a data signal (Data (t)) corresponding to an external video signal and a light emission control signal EM [n] for controlling light emission of the pixel Respectively.

11 includes a driving transistor M1 connected to the anode electrode of the organic light emitting diode OLED, a switching transistor M2 connected to the source electrode of the driving transistor M1, A first emission control transistor M5 connected between the first power source voltage ELVDD and a node N2 connected between the driving transistor M1 and the switching transistor M2, An auxiliary transistor M7 connected to the electrode to transmit a predetermined auxiliary voltage Vsus to the bias electrode and a storage capacitor Cst disposed between the driving transistor M1 and the first power source voltage ELVDD.

The pixel of the present invention may further include an initialization transistor M4 for transferring the initialization voltage Vint during the initialization period.

The pixel may further include a threshold voltage compensating transistor M3 for diode-connecting the driving transistor Ml to compensate the threshold voltage of the driving transistor Ml.

The pixel includes at least one second emission control transistor M6 which is connected to the anode electrode of the organic light emitting diode OLED in addition to the first emission control transistor M5 and controls light emission according to the driving current of the organic light emitting diode OLED Or more.

The pixel may further include a boost capacitor Cboost positioned between the contact N1 connected to the gate electrode of the driving transistor M1 and the gate electrode of the switching transistor M2.

The embodiment of the circuit diagram of the pixel in which the thin film transistor according to the embodiment of the present invention is applied to the driving transistor may be various and is not necessarily limited to Fig.

An organic light emitting diode (OLED) of a pixel includes an anode electrode and a cathode electrode, and emits light by a driving current corresponding to a corresponding data signal. In the present invention, the driving current according to the data signal is compensated so as not to be influenced by the threshold voltage of the driving transistor (M1) of the pixel.

In the circuit diagram of the pixel, the driving transistor M1 is a four-terminal transistor, specifically, a source electrode connected to the contact N2, a drain electrode connected to the contact N3 to which the threshold voltage compensating transistor M3 is connected, A gate electrode connected to the node N1 to which the first transistor Cboost is connected, and a bias electrode to which the auxiliary transistor M7 is connected. The driving transistor M1 receives the data signal through the switching transistor M2 connected to the contact N2.

The driving transistor M1 transmits a driving current corresponding to a voltage difference between the source electrode and the gate electrode to the organic light emitting diode OLED to emit light.

A predetermined initializing voltage Vint is applied to the gate electrode of the driving transistor M1 and a predetermined auxiliary voltage Vsus is applied to the bias electrode before the data signal is written to the driving transistor M1 do.

The switching transistor M2 is connected to the data line and is connected to a source electrode to which the data signal Data (t) is transferred, a drain electrode connected to the contact N2, and a scan signal Scan [n] And a gate electrode.

When the scanning signal Scan [n] is transferred through the corresponding scanning line and the switching transistor M2 is turned on, the data signal Data (t) is transferred to the contact N2 and the data signal Data (t ) Is transferred to the source electrode of the driving transistor Ml.

The scan signal Scan [n] is simultaneously transmitted to the gate electrode of the threshold voltage compensating transistor M3.

The threshold voltage compensating transistor M3 is connected between the gate electrode and the drain electrode of the driving transistor M1 and is turned on while the scanning signal Scan [n] is transferred to the gate- Diode connection. Then, a voltage (Vdata-Vth) lowered by the threshold voltage of the driving transistor (M1) is applied to the gate electrode of the driving transistor (M1) at the data voltage applied to the source electrode of the driving transistor (M1). Since the gate electrode of the driving transistor Ml is connected to one end of the storage capacitor Cst, the voltage Vdata-Vth is held by the storage capacitor Cst. Since the voltage Vdata-Vth reflecting the threshold voltage Vth of the driving transistor M1 is applied and held to the gate electrode, the driving current flowing to the driving transistor M1 affects the threshold voltage of the driving transistor M1 I do not accept.

The initialization transistor M4 includes a gate electrode connected to the previous scan line of the corresponding scan line and receiving the scan signal Scan [n-1], a source electrode connected to a voltage source for transferring the initialization voltage Vint, And a drain electrode connected to the gate electrode of the first transistor M1.

When the scan signal Scan [n-1] is transferred to the initialization transistor M4 at the gate-on voltage level during the initialization period before the data signal is written, the initialization transistor M4 is turned on, The initializing voltage Vint is applied to the gate electrode of the transistor M1 so that the gate electrode of the driving transistor M1 is initialized to the initializing voltage.

On the other hand, during the initialization period in which the scan signal Scan [n-1] is transferred to the gate-on voltage level, the scan signal Scan [n-1] is transferred to the gate electrode and the auxiliary transistor M7 is turned on. Then, the auxiliary voltage Vsus is applied to the bias electrode of the driving transistor M1 through the auxiliary transistor M7 turned on. Since the scan signal Scan [n] and the emission control signal EM [n] are all transmitted at the gate-off voltage level during the initialization period in which the scan signal Scan [n-1] The source and the drain of the transistor M1 are all floated. Therefore, by applying the auxiliary voltage Vsus to the bias electrode connected to the bias region following the channel region of the driving transistor Ml during the initialization period before data is written, ultimately, the source voltage and the drain voltage of the driving transistor Ml are supplied to the auxiliary Voltage can be set. At this time, the source-drain voltage difference of the driving transistor M1 becomes approximately zero (0).

The data voltage is written to the source electrode of the driving transistor M1 in a state in which the driving transistor M1 of all the pixels sets the source voltage and the drain voltage of the driving transistor M1 to the auxiliary voltage by this operation, The hysteresis characteristic according to the gradation change can be improved.

On the other hand, since each of the plurality of driving transistors is applied with the data voltage of the immediately preceding frame, the gate-source voltages of the plurality of driving transistors may be at different levels before writing the data voltage of the current frame.

In the embodiment of the present invention, the source and drain voltages of all the driving transistors are set to a predetermined auxiliary voltage and the gate voltage is set to the initializing voltage Vint during the initialization period to bias all the driving transistors on the same condition. So that the gate-source voltages of the driving transistors of all the pixels are determined in accordance with the data voltage of the corresponding current frame under the same condition without being influenced by the hysteresis characteristic.

In the embodiment of the present invention, the signals for controlling the switching operations of the initializing transistor M4 and the auxiliary transistor M7 are used as the scanning signals transmitted through the previous scanning lines of the scanning lines connected to the corresponding pixel lines. However, The control signal supplied through the control line may be used.

On the other hand, in the case of a pixel included in the first pixel line, the scan signal transmitted to the initializing transistor M4 and the auxiliary transistor M7 may be a dummy scan signal generated and transmitted by the scan driver.

The storage capacitor Cst includes a first electrode connected to the contact N1 and a second electrode connected to the first power supply voltage ELVDD.

Since the storage capacitor Cst is connected to the contact N1 to which the gate electrode of the driving transistor Ml is connected, the storage capacitor Cst stores the gate electrode voltage value of the driving transistor Ml in accordance with the driving process of the pixel.

The first emission control transistor M5 of the pixel according to an embodiment of the present invention includes a gate electrode connected to a corresponding emission control line and receiving a emission control signal EM [n], a first power supply voltage ELVDD, And a drain electrode connected to the contact N2.

The pixel may further include a second emission control transistor M6. The second emission control transistor M6 may include a gate electrode connected to the corresponding emission control line and receiving the emission control signal EM [n] A source electrode connected to the contact N3, and a drain electrode connected to the anode electrode of the organic light emitting diode OLED.

The configuration of the light emission control transistor of the present invention is one embodiment and is not necessarily limited to this configuration.

When the emission control signal EM [n] is transferred to the gate-on voltage level, the first emission control transistor M5 and the second emission control transistor M6 are turned on and stored in the storage capacitor Cst during the data write- Emitting diode OLED by a driving current corresponding to a data voltage according to a data signal. As described above, since the data voltage stored in the storage capacitor Cst is a voltage value (Vdata-Vth) in which the threshold voltage (Vth) is taken into account, the influence of the threshold voltage can be excluded when the light emission is performed for the corresponding driving current.

The transistor included in the driving circuit diagram of the pixel shown in FIG. 11 has been described on the assumption that the transistor is a PMOS, but the present invention is not limited thereto and can be implemented by an NMOS.

The detailed operation of the driving of the pixel shown in Fig. 11 will be described in detail in the following description of the timing diagram of Fig.

FIG. 12 is a circuit diagram showing a basic structure (6TR structure) of a conventional pixel. Unlike FIG. 11, it can be seen that the driving transistor M10 has a three-terminal structure composed of only a gate, a source, and a drain. Therefore, since the conventional thin film transistor is used, there is no bias electrode connected to the channel region of the driving transistor M10, and there is no auxiliary transistor connected to the bias electrode.

The operation of the initialization period and the period during which the data signal is written and the components of the pixel circuit of FIG. 12 are not so different from those of FIG. 11, so a detailed description thereof will be omitted.

However, since the driving transistor MlO of FIG. 12 has a general three-terminal structure, the source and drain voltages of the driving transistor are not set to a specific voltage before data writing as compared with the case of FIG. 11 so that the effect of improving hysteresis characteristics is small have.

The following Table 1 shows the relationship between the pixel (Experimental Example) in which the thin film transistor structure of the present invention shown in FIG. 11 is applied to the driving transistor and the pixel (Comparative Example) in which the conventional thin film transistor structure shown in FIG. 12 is applied to the driving transistor (Black to white).

Efficiency according to luminance variation Start -> End Experimental Example (7TR) Comparative Example (6TR) Improvement rate 0 -> 64 89.87% 62.19% 27.68 0 -> 128 91.69% 64.71% 26.98 0 -> 192 93.28% 67.28% 26.00 0 -> 255 96.20% 72.27% 23.93

As can be seen from Table 1, the variation of the luminance when the gradation level was changed from 0, which is the lowest gradation, to the predetermined gradation level was superior to the experimental example of the present invention using the thin film transistor having the 7 TR structure as compared with the comparative example.

It can be seen that the efficiency according to the luminance variation is greatly improved in the experimental example in the case of the extreme gradation change. Therefore, it can be seen that a pixel including a driving transistor to which the thin film transistor according to the present invention is applied can change immediately without passing through an intermediate gray level in expressing an extreme gradation, thereby greatly improving the hysteresis characteristic.

13 is a block diagram of an OLED display including the pixel of FIG. 11 including a thin film transistor according to an embodiment of the present invention.

A display device 300 according to an embodiment of the present invention includes a display unit 310 including a plurality of pixels, a scan driver 320, a data driver 330, a light emitting driver 340, a controller 350, And a power supply unit 360 for supplying an external voltage.

Each of the plurality of pixels is connected to two of the plurality of scan lines S0 to Sn transmitted to the display unit 310. [ 13, the pixel is connected to the scanning line corresponding to the pixel line and the scanning line of the previous line, but the pixel is not necessarily limited to this.

Each of the plurality of pixels includes one of a plurality of data lines D1 to Dm transmitted to the display unit 310 and one of the plurality of emission control lines EM1 to EMn transmitted to the display unit 310. [ Line.

The scan driver 320 generates and transmits two corresponding scan signals to each pixel through the plurality of scan lines S0 to Sn. That is, the scan driver 320 transmits the first scan signal through the scan line corresponding to the pixel line including each pixel, and transmits the second scan signal through the scan line corresponding to the previous pixel line of the pixel line.

13, the pixel 370, which is one of the plurality of pixels included in the nth pixel line, is connected to the scan line Sn corresponding to the nth pixel line and the (n-1) th pixel line before the nth pixel line And is connected to the corresponding scanning line Sn-1, respectively. The pixel 370, which is one of the plurality of pixels included in the nth pixel line, corresponds to the pixel shown in Fig.

The pixel receives the first scan signal Scan [n] through the scan line Sn and simultaneously receives the second scan signal Scan [n-1] through the scan line Sn-1.

The data driver 330 transmits data signals to the respective pixels through the plurality of data lines D1 to Dm.

The light emission driving unit 340 generates and transmits a light emission control signal to each pixel through the plurality of light emission control lines EM1 to EMn.

The control unit 350 converts a plurality of video signals R, G and B transmitted from the outside into a plurality of video data signals DR, DG and DB and transmits them to the data driver 330. The controller 350 receives the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync and the clock signal MCLK to drive the scan driving unit 320, the data driving unit 330, and the light emitting driving unit 340 And transmits the generated control signals to the respective control signals. That is, the control unit 350 includes a scan driving control signal SCS for controlling the scan driving unit 320, a data driving control signal DCS for controlling the data driving unit 330, And generates and transmits control signals ECS.

The display unit 310 includes a plurality of pixels located at intersections of the plurality of scan lines S0 to Sn, the plurality of data lines D1 to Dm, and the plurality of emission control lines EM1 to EMn.

The plurality of pixels receive an external voltage such as a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization voltage VINT, and an auxiliary voltage Vsus from a power supply unit 360. The first power source voltage ELVDD has a voltage level higher than the second power source voltage ELVSS.

The display unit 310 includes a plurality of pixels arranged in a substantially matrix form. Although not particularly limited, the plurality of scanning lines S0 to Sn extend in a substantially row direction in the arrangement of the pixels and are substantially parallel to each other, and the plurality of data lines D1 to Dm extend in a substantially column direction, Do.

Each of the plurality of pixels emits light of a predetermined luminance by a driving current supplied to the organic light emitting diode according to a corresponding data signal transmitted through the plurality of data lines (D1 to Dm).

FIG. 14 is a timing chart showing the pixel driving operation of the organic light emitting display shown in FIG. 13, and the driving process of the pixel having the circuit structure of FIG. 11 will be described in detail with reference to FIG.

As described above with reference to FIG. 11, the pixel according to the exemplary embodiment of the present invention is connected to two consecutive scan lines, and receives a scan signal.

First, the scan signal S [n-1] transmitted through the (n-1) th scan line at time t1 changes to a low level and maintains a low level during a period T1.

The initializing transistor M4 and the auxiliary transistor M7, which receive the scanning signal S [n-1] from the pixel, are simultaneously turned on.

During the period T1, the initializing voltage Vint is applied to the gate electrode of the driving transistor M1 through the initializing transistor M4. The source electrode and the drain electrode of the driving transistor Ml are in a state in which the transistors connected to these electrodes are off and are floating. At this time, the auxiliary voltage Vsus is applied to the source electrode and the drain electrode of the floating driving transistor M1 through the bias electrode connected to the channel region of the driving transistor M1. The auxiliary voltage Vsus is transmitted through the auxiliary transistor M7 turned on during the period T1.

The source electrode and the drain electrode of the driving transistor Ml are set to a predetermined voltage before data writing due to the auxiliary voltage Vsus applied to the channel region of the driving transistor Ml and the source- There is no car. A voltage of a predetermined level is applied before data writing according to a data signal. Therefore, even when an extreme gradation change is displayed, the gradation can be changed immediately without passing through the intermediate gradation, and the target gradation can be accurately displayed. Thus, the hysteresis characteristic can be remarkably improved.

Meanwhile, since the initializing voltage Vint is applied to the gate voltage of the driving transistor M1 during the period T1, the gate-source voltage difference Vgs can be kept constant before data writing. Since the electrode voltage of the driving transistor Ml included in all the pixels is set to a predetermined voltage before the threshold voltage of the driving transistor Ml is compensated in each frame and the data is written, the influence of the hysteresis characteristic of the driving transistor Ml It is possible to realize an image that is expressed in a desired gradation without receiving it.

Then, the scanning signal S [n] transitioned to the high level at the time point t2 and the scanning signal S [n] transferred through the nth scanning line at the time point t3 changes to the low level, Level.

The initialization transistor M4 and the auxiliary transistor M7 are turned off and the voltage of the contact N1 is floating because the scan signal S [n-1] is transferred to the high state during the period T2.

At the same time, the switching transistor M2 and the threshold voltage compensating transistor M3, which receive the scanning signal S [n] from the pixel during the period T2, are turned on. During the period T2, the data voltage Vdata according to the data signal Date (t) is transferred to the source electrode of the driving transistor M1 through the switching transistor M2. The driving transistor M1 is connected to the threshold voltage compensating transistor M3.

The voltage held at the contact N1 connected to one end of the storage capacitor Cst during the period T2 is the voltage Vgs corresponding to the gate-source electrode voltage difference of the driving transistor M1, (Vdata-Vth) lowered by the threshold voltage Vth of the driving transistor Md.

Since the auxiliary voltage is applied to the driving transistor M1 during the initialization period of the T1 period to improve the hysteresis characteristic, it is possible to solve the problem of delaying the response speed in gradation representation according to the data voltage Vdata.

When the scanning signal S [n] transitions to the high level at the time point t4, the switching transistor M2 and the threshold voltage compensating transistor M3 are turned off. Then, the voltage of the contact N1 is floating again.

The emission control signal EM [n] transmitted to the pixel included in the n-th pixel line at time t5 changes to the low level.

The first emission control transistor M5 and the second emission control transistor M6 of the pixel to which the emission control signal EM [n] is transmitted are turned on, and the organic light emitting diode OLED is connected to the storage capacitor Cst And the driving current of the data voltage corresponding to the stored data signal is transmitted to emit light.

The pixel and the display device including the same according to the embodiment of the present invention can solve the problem of the response speed due to the hysteresis characteristic while excluding the influence of the threshold voltage of the driving transistor in displaying an image according to the data signal, It is possible to provide a clear high quality image by emitting light with a desired luminance directly in the frame without delaying the speed.

In particular, even if an extreme luminance change occurs when data is changed from the immediately preceding frame to the corresponding frame, an auxiliary voltage is applied through the bias electrode before the corresponding frame data is written, so that the source- The hysteresis characteristic can be improved.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are illustrative and explanatory only and are intended to be illustrative of the invention and are not to be construed as limiting the scope of the invention as defined by the appended claims. It is not. Therefore, those skilled in the art can readily select and substitute it. Those skilled in the art will also appreciate that some of the components described herein can be omitted without degrading performance or adding components to improve performance. In addition, those skilled in the art may change the order of the method steps described herein depending on the process environment or equipment. Therefore, the scope of the present invention should be determined by the appended claims and equivalents thereof, not by the embodiments described.

10, 110, 210: semiconductor layer 20, 120: source electrode
30, 130: drain electrode
40, 140, 240: gate metal layer 50, 150, 250: gate electrode
60, 65, 67, 260:
21, 31, 51, 61, 121, 131, 151, 251, 261:
100, 200: substrate
300: organic light emitting display
310: Display section 320:
330: Data driver 340:
350: control unit 360: power supply unit
370: pixel

Claims (5)

Organic light emitting diodes;
A driving transistor for transmitting a driving current according to a data signal to the organic light emitting diode;
A wiring extending to overlap with at least a first region of the semiconductor layer of the driving transistor; And
And an auxiliary transistor connected to one end of the driving transistor, the auxiliary transistor being turned on during an initialization period before data writing to supply a predetermined first voltage to the wiring to reduce a source-drain voltage difference of the driving transistor. .
delete The method according to claim 1,
And a switching transistor connected to one end of the driving transistor and transmitting the data signal. The method according to claim 1,
And a compensating transistor connected between the gate and the other end of the driving transistor and compensating a threshold voltage of the driving transistor. The method according to claim 1,
Further comprising an initialization transistor coupled to a gate of the driving transistor and transmitting an initialization voltage to a gate of the driving transistor.

Images