JP4700160B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4700160B2
JP4700160B2 JP2000069563A JP2000069563A JP4700160B2 JP 4700160 B2 JP4700160 B2 JP 4700160B2 JP 2000069563 A JP2000069563 A JP 2000069563A JP 2000069563 A JP2000069563 A JP 2000069563A JP 4700160 B2 JP4700160 B2 JP 4700160B2
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formed
film
conductive
substrate
insulating film
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JP2001255560A5 (en
JP2001255560A (en
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潤 小山
舜平 山崎
秀明 桑原
康行 荒井
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株式会社半導体エネルギー研究所
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    • HELECTRICITY
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. In particular, the present invention relates to a configuration of each pixel in a pixel region that forms a display portion and a configuration of a driver circuit that transmits a signal to the pixel. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and includes electro-optical devices, semiconductor circuits, and electronic devices in its category.
[0003]
[Prior art]
A liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices are often used because high-definition images can be obtained compared to passive liquid crystal display devices. In an active matrix liquid crystal display device, a voltage is applied to pixels arranged in a matrix to control the orientation of the liquid crystal and display image information on a screen.
[0004]
Such an active matrix liquid crystal display device is widely used in various electronic devices such as liquid crystal televisions, as well as portable information terminals such as notebook personal computers (notebook personal computers), mobile computers, and mobile phones. . Such a display device can be made lighter and thinner than a CRT, and depending on the application, a large screen area and a high density of pixels are required.
[0005]
A technique for forming a TFT channel formation region or the like with an amorphous semiconductor film typified by amorphous silicon is excellent in productivity. The amorphous semiconductor film has a feature that it can be formed on a relatively inexpensive and large-area substrate such as barium borosilicate glass or alumino borosilicate glass. However, the field effect mobility of a TFT in which a channel formation region is formed of an amorphous silicon film is at most 1 cm. 2 Can only get about / Vsec. Therefore, although it can be used as a switching TFT (pixel TFT) provided in the pixel region, a driving circuit cannot be formed to perform a desired operation. Therefore, an IC chip (driver IC) manufactured using a single crystal silicon substrate is used as a drive circuit that controls a voltage applied to a pixel in accordance with a signal, and a TAB (Tape Automated Bonding) method or a COG (Chip (Chip)) is formed around the pixel region. on Glass) method.
[0006]
In the TAB method, wiring is formed with a copper foil on a flexible insulating substrate, and an IC chip is directly mounted on the wiring. One end of the flexible substrate is connected to the input terminal of the display device. It is a method to implement. On the other hand, the COG method is a method in which an IC chip is directly bonded and connected in accordance with a wiring pattern formed on a substrate of a display device.
[0007]
As another method for mounting a driver circuit, Japanese Patent Application Laid-Open No. 7-014880 and Japanese Patent Application Laid-Open No. 11-160734 disclose a driver circuit using TFTs made of a non-single crystal semiconductor material on a substrate such as glass or quartz. A technique is disclosed that is formed, divided into strips (hereinafter, a substrate having a drive circuit cut out in a strip shape in this manner is referred to as a stick driver), and mounted on a substrate of a display device.
[0008]
In any case, it is preferable that the area for mounting the drive circuit on the substrate on which the pixel area is formed is as small as possible, and various ingenuity including the layout of wiring and the like has been elaborated in the method for mounting the drive circuit.
[0009]
[Problems to be solved by the invention]
So far, CRTs have been most used as monitors for televisions and personal computers. However, from the viewpoint of space saving and low power consumption, as it is being replaced by liquid crystal display devices, the screen area and the high definition are being promoted for liquid crystal display devices. Reduction has been demanded.
[0010]
An active matrix display device uses a photolithographic technique to manufacture pixel TFTs and uses at least five photomasks. A photomask is used in the photolithography technique to form a photoresist pattern as a mask for an etching process on a substrate. By using one photomask, the steps such as resist coating, pre-baking, exposure, development, and post-baking, and the steps before and after that, such as film formation and etching, resist stripping, cleaning, and drying are performed. Due to the addition of processes and the like, the work related to manufacturing has become complicated and problematic.
[0011]
In order to improve productivity and improve yield, reducing the number of steps is considered as an effective means. However, as long as the number of photomasks is not reduced, there is a limit to reducing the manufacturing cost.
[0012]
In addition, since the substrate is an insulator, static electricity is generated due to friction during the manufacturing process. When this static electricity is generated, a short circuit occurs at the intersection of the wirings provided on the substrate, or the TFT is deteriorated or destroyed by the static electricity, resulting in display defects or image quality deterioration in the electro-optical device. In particular, static electricity is generated during the rubbing of the liquid crystal alignment process performed in the manufacturing process, which is a problem.
[0013]
In addition, as the number of pixels increases, the number of IC chips to be mounted inevitably increases. In an RGB full color display XGA panel, the number of terminals on the source line side of the pixel area is about 3000, and UXGA requires 4800. The size of the IC chip is limited by the wafer size in the manufacturing process, and the practical size is limited to a long side of about 20 mm. This IC chip can cover only 400 connection terminals with one IC chip even if the pitch of the output terminals is 50 μm. The above XGA panel requires about 8 IC chips only on the source line side, and the UXGA panel requires 12 IC chips.
[0014]
Although a method of manufacturing a long IC chip is also conceivable, the number of strip-shaped IC chips that can be taken out from a circular silicon wafer is inevitably reduced, which is not practical. Furthermore, since the silicon wafer itself is fragile, the probability of breakage increases if a very long wafer is manufactured. Further, for mounting an IC chip, it is necessary to reduce the alignment accuracy and the contact resistance of the terminal portion. When the number of IC chips attached to one panel increases, there is a concern that the incidence of defects increases and the yield in that process decreases. In addition, since the temperature coefficient of silicon that is the base of the IC chip is different from that of the glass substrate on which the pixel region is formed, deflection occurs after bonding and direct defects such as an increase in contact resistance occur. In addition, the reliability of the element is reduced due to the generated stress.
[0015]
On the other hand, the stick driver can form a drive circuit having the same length as that of the pixel region, and the drive circuit can be formed and mounted by using one stick driver. However, as the area of the circuit portion increases, the number of stick drivers that become defective due to a single point defect increases, so the number of stick drivers that can be taken out from one substrate decreases, leading to a decrease in process yield. End up.
[0016]
From the viewpoint of productivity, it is considered that a method of forming a large number of stick drivers with TFTs manufactured from a crystalline semiconductor film on a large-area glass substrate or quartz substrate is considered excellent. However, the driving frequency of the circuit is different between the scanning line side and the source line side, and the value of the driving voltage to be applied is also different. Specifically, although a breakdown voltage of about 30 V is required for the TFT of the stick driver on the scanning line side, the driving frequency is 100 kHz or less and high speed is not required. Although it is sufficient that the breakdown voltage of the TFT of the stick driver on the source line side is about 12 V, the driving frequency is about 65 MHz at 3 V, and high speed operation is required. As described above, it is necessary to appropriately create the structure of the stick driver and the TFT in the driver depending on the difference in required specifications.
[0017]
Based on such a background, a first object of the present invention is to reduce the number of steps for manufacturing a pixel TFT of a liquid crystal display device to realize a reduction in manufacturing cost and an improvement in yield. We also provide a method for forming a drive circuit formed of TFTs that satisfy the characteristics required by each circuit on a large area substrate such as a glass substrate, and a display device on which such a drive circuit is mounted. It is a second problem to provide a technique for improving the performance.
[0018]
[Means for Solving the Problems]
A first means for solving the above problem is that a pixel TFT to be formed in a pixel region is formed by a channel etch type inverted staggered TFT, and patterning of a source region and a drain region and patterning of a pixel electrode are performed with the same photomask. It is characterized by performing.
[0019]
A method for manufacturing a pixel TFT of the present invention will be briefly described with reference to FIGS. First, a pattern of the gate wiring 102 and the capacitor wiring 103 is formed using a first mask (first photomask). Next, an insulating film (gate insulating film), a first semiconductor film, a one-conductivity-type second semiconductor film, and a first conductive film are sequentially stacked.
[0020]
The first conductive film, the one-conductivity-type second semiconductor film, and the first semiconductor film are etched into a predetermined shape with the second mask (second photomask) to form a channel formation region or source of the pixel TFT. Alternatively, the drain region is determined, and the source wiring and drain electrode patterns are formed. Thereafter, a second conductive film for forming a pixel electrode is formed.
[0021]
The pixel electrode 119 is formed by etching the second conductive film with the third mask (third photomask). Further, the first conductive film and the one-conductivity-type second semiconductor film remaining on the channel formation region of the pixel TFT are removed by etching. In this etching process, since the etching selectivity cannot be increased, a part of the first semiconductor film is also etched.
[0022]
Through such a process, the number of photomasks necessary for manufacturing the pixel TFT can be three. In the case where a protective insulating film is formed over the pixel TFT, another photomask is required because it is necessary to provide an opening in the pixel electrode. The source wiring can be covered with a second conductive film which is the same material as the pixel electrode, and the entire substrate can be protected from external static electricity or the like. In addition, a protective circuit may be formed in a region other than the pixel TFT portion using the second conductive film. With such a configuration, generation of static electricity due to friction between the manufacturing apparatus and the insulating substrate in the manufacturing process can be prevented. In particular, the TFT and the like can be protected from static electricity generated during rubbing of the liquid crystal alignment treatment performed in the manufacturing process.
[0023]
In a reflective liquid crystal display device, there is a method of forming a pixel electrode having an optimum reflection characteristic by making the surface of the pixel electrode uneven to obtain a bright display. The present invention can also be applied to such a reflective liquid crystal display device, and therefore, it is not necessary to increase the number of photomasks. As a method for making the surface of the pixel electrode uneven, a method is used in which when the gate wiring is formed, an island-like pattern is formed in a region below the pixel electrode. Since only the layer of the gate insulating film and the pixel electrode is formed on the pattern, an uneven shape corresponding to the pattern can be formed on the surface of the pixel electrode.
[0024]
According to a second means for solving the above problem, a TFT having a crystalline semiconductor layer is provided in a display device having a first substrate on which a pixel region is formed and a second substrate on which a counter electrode is formed. A plurality of drive circuits formed using them and input / output terminals subordinate to the drive circuits as one unit are formed on a third substrate, and then the third substrate is divided into individual units. The stick driver obtained in this way is mounted on a first substrate.
[0025]
The configuration of each circuit of the stick driver is different between the scanning line side and the source line side, and the thickness of the gate insulating film of the TFT, the channel length, and the like are different according to required circuit characteristics. For example, in a scanning line stick driver composed of a shift register circuit, a level shifter circuit, and a buffer circuit, the TFT of the buffer circuit that requires a withstand voltage of 30 V is formed thicker than the TFT of the shift register circuit. In addition, the stick driver on the source line side composed of a shift register circuit, a latch circuit, a level shifter circuit, and a D / A converter circuit has a thickness of the gate insulating film of the shift register circuit and the latch circuit in order to drive at a high frequency. It is made thinner and the channel length is shorter than other TFTs.
[0026]
Further, a signal dividing circuit is provided on the source line side that requires a high frequency input digital signal, and means for reducing the frequency of the data signal input to the stick driver is provided. This reduces the burden on the TFT of the stick driver and improves the reliability of the drive circuit. The signal dividing circuit includes n input units and m × n output units, receives the input signal from each of the n input units, and corrects the pulse length of the input digital signal by extending the time. The frequency of the input digital signal is lowered by sending out digital signals from m × n output units. The modified digital signal may be a signal obtained by extending the pulse length of the input digital signal by several times.
[0027]
The basic concept of the present invention is shown in FIG. A plurality of driver circuits are formed over the first substrate 3201 in which the display region 3202 is formed and the third substrate 3206, and the third substrate 3206 is divided into strips or rectangles for each of the driver circuits. The stick driver taken out is attached to the first substrate. The configuration of the drive circuit differs between the scanning line side and the source line side, but in any case, a plurality of stick drivers are mounted on each side. FIG. 32 shows a form in which stick drivers 3203 and 3204 in which scanning line driving circuits are formed and stick drivers 3207 and 3208 in which source line driving circuits are formed are mounted.
[0028]
From the viewpoint of improving productivity, it is suitable to make a plurality of stick drivers on a third substrate having a large area. For example, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit may be formed on a large substrate having a size of 300 × 400 mm or 550 × 650 mm, and finally divided and taken out. The length of the short side of the stick driver is 1 to 6 mm, and the length of the long side is 15 to 80 mm. In order to divide in such a size, it is possible to form a ruled line on the surface of the glass substrate using a diamond piece or the like, and to cut along the ruled line by applying an external force. The machine that performs this processing is also called a glass scriber. However, the processing width of the blade necessary for cutting is not less than 100 μm, and it is necessary to allow for 100 to 500 μm. Further, the alignment accuracy with the marker formed on the substrate also has an error of ± 100 μm. Therefore, in order to cut out a stick driver having a short side of 2 mm with a glass scriber, it is necessary to allow 1 to 5 mm of cutting margin, which limits the number of pieces taken from one substrate. On the other hand, a dicing apparatus using a blade dicing method for cutting a silicon wafer into individual dies has a blade (blade) width of 0.02 to 0.05 mm, and an accuracy of 100 μm or less considering the alignment accuracy. The substrate can be divided.
[0029]
Therefore, in a method for efficiently removing the stick driver from one substrate, a processing region to be divided by a glass scriber having a low processing accuracy and a processing region to be cut by a dicing apparatus having a high processing accuracy are arranged separately. Specifically, a group consisting of regions each having a side of 100 to 200 mm is formed, and a plurality of stick drivers having a short side length of 1 to 6 mm are arranged in the group. The group is divided by a glass scriber, and a dicing device is used to take out the stick driver from the divided group.
[0030]
Further, the stick driver on the source line side has a channel length of 0.3 to 1 μm, and more design rules than the stick driver on the scanning line side in order to form a necessary circuit within the limited area as described above. Is reduced and formed. As a preferable method, an exposure technique using a stepper method is adopted.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
The configuration of the pixels in the pixel region in the liquid crystal display device of the present invention will be described. FIG. 1 is an example of a plan view, and here, for simplification, one pixel configuration of a plurality of pixels arranged in a matrix is shown. 2 and 3 are diagrams showing a manufacturing process.
[0032]
As shown in FIG. 1, the pixel region has a plurality of gate wirings arranged in parallel to each other and a plurality of source wirings crossing each gate wiring. A pixel electrode 119 is provided in a region surrounded by the gate wiring and the source wiring. Further, the wiring 120 made of the same material as the pixel electrode overlaps the source wiring 117 so as not to overlap with the pixel electrode 119. A TFT as a switching element is provided in the vicinity of the intersection of the gate wiring 102 and the source wiring 117. This TFT is an inverted staggered (or also referred to as a bottom gate type) TFT having a channel formation region formed of a semiconductor film having an amorphous structure (hereinafter referred to as a first semiconductor film).
[0033]
Further, a capacitor wiring 103 is arranged in parallel with the gate wiring 102 between two adjacent gate wirings below the pixel electrode 119. The capacitor wiring 103 is provided in all pixels, and forms a storage capacitor using the insulating film 104b existing between the pixel electrode 119 and a dielectric.
[0034]
The inverted staggered TFT of the present invention includes a gate electrode (an electrode integrally formed with the same layer as the gate wiring 102 and connected to the gate wiring), a gate insulating film, and a first semiconductor film on the insulating substrate. A source region and a drain region made of a second semiconductor film containing an impurity element of one conductivity type (usually n-type), a source electrode (integrated with the source wiring 117), and an electrode 118 (hereinafter, (Also referred to as a drain electrode).
[0035]
Below the source wiring (including the source electrode) and the drain electrode 118, a gate insulating film, a first semiconductor film, and a second semiconductor film containing an impurity element imparting n-type are sequentially formed over the insulating substrate. Are stacked.
[0036]
Of the first semiconductor film, the region between the region in contact with the source region and the drain region is thinner than the other regions. The film thickness is reduced because part of the first semiconductor film is removed when the second semiconductor film containing an impurity element imparting n-type conductivity is separated by etching to form a source region and a drain region. It was because it was done. In addition, the end face of the pixel electrode, the end face of the drain electrode, and the end face of the drain region coincide with each other by this etching. Such an inverted stagger type TFT is called a channel etch type. In addition, the feature of the inverted staggered TFT in the present invention is that the end face of the wiring 120 covering the source electrode, the end face of the source region, and the end face of the source wiring coincide.
[0037]
[Embodiment 2]
FIG. 6 is a diagram showing the configuration of the display device of the present invention. A pixel region 652 is formed over the substrate 651. On the region where the pixel region 652 is formed, a second substrate 660 on which a counter electrode is formed is bonded via a liquid crystal layer (not shown). The distance between the first substrate and the second substrate, that is, the thickness of the liquid crystal layer is determined by the spacer, but is 3 to 8 μm for nematic liquid crystal and 1 to 4 μm for smectic liquid crystal. The first and second substrates are preferably made of non-alkali glass such as aluminoborosilicate glass or barium borosilicate glass, and the thickness is 0.3 to 1.1 mm (typically 0.7 mm). Since it is used, the thickness of the liquid crystal layer is relatively negligible in appearance.
[0038]
In the pixel region 652, a scanning line group (corresponding to a gate wiring) group 658 and a source line group 659 intersect to form a matrix, and a TFT is disposed corresponding to each intersecting portion. As the TFT arranged here, the inverted staggered TFT described in Embodiment 1 is used. The amorphous silicon layer can be formed by plasma CVD at a temperature of 300 ° C. or lower. For example, even an non-alkali glass substrate having an outer dimension of 550 × 650 mm is a film necessary for forming a TFT. The thickness can be formed in tens of seconds. Such a feature of the manufacturing technique can be used very effectively in manufacturing a large-screen display device.
[0039]
In the area outside the pixel area 652, stick drivers 653 and 654 in which a drive circuit is formed are mounted. Reference numeral 653 denotes a driving circuit on the source line side, and reference numeral 654 denotes a driving circuit on the scanning line side. In order to form a pixel region corresponding to RGB full color, the number of source lines is 3072 in the XGA class, and 768 scanning lines are required. In addition, UXGA requires 4800 and 1200, respectively. The source lines and scanning lines formed in such a number are divided into several blocks at the end of the pixel region 652 to form lead lines 657 and collected according to the pitch of the output terminals of the stick drivers 653 and 654. ing.
[0040]
On the other hand, an external input terminal 655 is formed at an end portion of the substrate 651, and an FPC (Flexible Printed Circuit) connected to an external circuit is bonded to this portion. The external input terminal 655 and the stick driver are connected by a connection wiring 656 formed on the substrate 651, and finally collected according to the pitch of the input terminals of the stick driver.
[0041]
The circuit configuration of the stick driver is different between the scanning line side and the source line side. FIG. 7 shows an example of this, and similarly to FIG. 6, the scanning line side stick driver 671 and the source line side stick driver 672 are provided outside the pixel region 670. Depending on the pixel density, about 1 to 2 stick drivers are mounted on the scanning line side, and about 2 to 10 stick drivers are mounted on the data line side. The scanning line side stick driver 671 is composed of a shift register circuit 673, a level shifter circuit 674, and a buffer circuit 675. Among them, the buffer circuit 675 is required to have a withstand voltage of about 30 V, but the operating frequency is about 100 kHz. In particular, the TFT forming this circuit has a gate insulating film thickness of 150 to 250 nm and a channel length of 1 to 1. Form at 2 μm. On the other hand, the stick driver on the source line side includes a shift register circuit 676, a latch circuit 677, a level shifter circuit 678, and a D / A conversion circuit 679. Since the shift register circuit 676 and the latch circuit 677 are driven at a driving voltage of 3 V and a frequency of 50 MHz or more (for example, 65 MHz), the TFT forming this circuit has a gate insulating film thickness of 20 to 70 nm and a channel length of 0. It is formed with 3 to 1 μm.
[0042]
A stick driver in which such a driver circuit is formed is formed over a third substrate 811 as shown in FIG. 8A, and is provided with a circuit portion 812 formed of TFTs, an input terminal 813, and an output terminal 814. It has been. The channel formation region and the source and drain regions of the TFT of the driver circuit portion 812 are formed using a crystalline semiconductor film. As the crystalline semiconductor film, a film obtained by crystallizing an amorphous semiconductor film by a laser crystallization method or a thermal crystallization method can be applied, and other single crystal semiconductors formed using SOI technology. It is also possible to form with layers.
[0043]
FIG. 8B is a top view of the stick driver, and the cross-sectional view of FIG. 8A corresponds to the line AA ′. A plurality of output terminals connected to source lines or scanning lines in the pixel region are formed at a pitch of 40 to 100 μm. Similarly, the input terminals 813 are formed according to the required number. These input terminal 813 and output terminal 814 are formed in a square or rectangular shape with a side length of 30 to 100 μm. As shown in FIG. 6, the stick driver is not formed in accordance with the length of one side of the pixel region, but is formed in a rectangular shape or a strip shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm. As an example, when the size of the pixel region, that is, the screen size is increased, the length of one side of the screen is 443 mm in the 20 type. Of course, it is possible to form a stick driver corresponding to this length, but it cannot be a practical shape to ensure the strength of the substrate. Rather, dividing the stick driver into a plurality of lengths of 15 to 80 mm facilitates the handling and improves the manufacturing yield.
[0044]
The advantage of the external dimensions of the stick driver over the IC chip is the length of the long side, and it is not suitable from the viewpoint of productivity to form the IC chip with a length of 15 to 80 mm. Although it is not impossible, it reduces the number of IC chips taken from a circular silicon wafer, so it cannot be a realistic choice. On the other hand, the drive circuit of the stick driver is formed on a glass substrate and is not limited to the shape of the substrate used as a base, so that productivity is not impaired. In this way, by using a stick driver formed with a long side of 15 to 80 mm, the number required for mounting corresponding to the pixel region can be smaller than when using an IC chip. Yield can be improved.
[0045]
A method of mounting the stick driver manufactured using the third substrate on the first substrate is the same as the COG method, and a connection method using an anisotropic conductive material, a wire bonding method, or the like is adopted. be able to. An example is shown in FIG. FIG. 9A shows an example in which the stick driver 208 is mounted on the first substrate 201 using an anisotropic conductive material. A pixel region 202, a lead line 206, a connection wiring, and an input / output terminal 207 are provided over the first substrate 210. The second substrate is bonded to the first substrate 201 with a sealant 204, and a liquid crystal layer 205 is provided therebetween. An FPC 212 is bonded to one end of the connection wiring and the input / output terminal 207 with an anisotropic conductive material. The anisotropic conductive material is composed of a resin 215 and conductive particles 214 having a diameter of several tens to several hundreds μm with Au or the like plated on the surface. The wiring 213 is electrically connected. Similarly, the stick driver 208 is bonded to the first substrate with an anisotropic conductive material, and the conductive particles 210 mixed in the resin 211 are connected to the input / output terminal 209 provided in the stick driver 208 and the lead wire 206 or the connection. It is electrically connected to the wiring and input / output terminal 207.
[0046]
FIG. 10A is a partial cross-sectional view for explaining in detail a method of mounting the stick driver 224 by this method. The stick driver 224 is preferably provided with an input / output terminal 225, and a protective insulating film 226 is preferably formed on the periphery thereof. A first conductive layer 221, a second conductive layer 223, and an insulating layer 222 are formed on the first substrate 220 as shown in the figure. Here, the first conductive layer 221, the second conductive layer 223, The lead wire or connection wiring is formed. These conductive layers and insulating layers formed on the first substrate are formed in the same process as the pixel TFTs in the pixel region. For example, when the pixel TFT is formed in an inverted staggered type, the first conductive layer 221 is formed in the same layer as the gate electrode and is formed of a material such as Ta, Cr, Ti, or Al. Usually, a gate insulating film is formed on the gate electrode, and the insulating layer 222 is formed of the same layer. The second conductive layer 223 provided over the first conductive layer 221 is formed of the same transparent conductive film as the pixel electrode, and is provided in order to improve contact with the conductive particles 227. ing. By making the size and density of the conductive particles 227 mixed into the resin 228 suitable, an electrical connection structure can be formed between the stick driver and the first substrate in such a form.
[0047]
FIG. 10B shows an example of the COG method using the shrinkage force of the resin. A barrier layer 229 is formed of Ta, Ti, or the like on the stick driver side, and Au is formed thereon by about 20 μm by an electroless plating method or the like. A bump 230 is formed. Then, a photocurable insulating resin 231 is interposed between the stick driver and the first substrate, and an electrical connection is formed by press-contacting the electrodes using the shrinkage force of the resin that is hardened by photocuring.
[0048]
Further, as shown in FIG. 9B, a stick driver may be fixed to the first substrate with an adhesive 216, and the input / output terminal of the stick driver and the lead line or connection wiring may be connected by the Au wire 217. . Then, the resin 218 is sealed.
[0049]
The method of mounting the stick driver is not limited to the method based on FIGS. 9 and 10, and other than the method described here, a known COG method, wire bonding method, or TAB method can be used. .
[0050]
By making the thickness of the stick driver the same as that of the second substrate on which the counter electrode is formed, the height between the two becomes almost the same, which contributes to the thinning of the entire display device. it can. Further, by manufacturing each substrate with the same material, thermal stress does not occur even if a temperature change occurs in the liquid crystal display device, and the characteristics of the circuit manufactured by the TFT are not impaired. In addition, the number required for one pixel region can be reduced by mounting the drive circuit with a stick driver longer than the IC chip as shown in this embodiment.
[0051]
【Example】
[Example 1]
This embodiment shows a manufacturing method of a liquid crystal display device, and details of a method of forming a TFT of a pixel portion on a substrate with an inverted stagger type and manufacturing a storage capacitor connected to the TFT according to the steps shown in FIGS. Explained. In addition, the same drawing shows a manufacturing process of a terminal portion provided at an end portion of the substrate and electrically connected to wiring of a circuit provided on another substrate.
[0052]
In FIG. 2A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass is used for the substrate 100. In addition, a substrate such as a quartz substrate or a plastic substrate can be used.
[0053]
After a conductive layer is formed over the entire surface of the substrate 100, a photolithography process using a first photomask is performed, and an etching process is performed to form a gate electrode 102 ′, a gate wiring (not shown), a capacitor wiring 103, and a terminal 101. Form. At this time, etching is performed so that a tapered portion is formed at least at the end portion of the gate electrode 102 ′. A top view at this stage is shown in FIG.
[0054]
The gate electrode 102, the gate wiring and the capacitor wiring 103, and the terminal 101 of the terminal portion are preferably formed of a low-resistance conductive material such as aluminum (Al) or copper (Cu), but Al alone has poor heat resistance, In addition, since it is easily corroded, it is formed in combination with a heat-resistant conductive material. Further, an AgPdCu alloy may be used as the low resistance conductive material. As a heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and Nd (neodymium), or the element as a component. It is formed of an alloy, an alloy film in which the above elements are combined, or a nitride containing the above elements as a component. For example, a laminate of Ti and Cu and a laminate of TaN and Cu can be given. Further, it is preferable to form in combination with a heat-resistant conductive material such as Ti, Si, Cr, or Nd because the flatness is improved. In addition, a single layer of heat-resistant conductive material or an alloy of Mo and W or Mo and Ta may be used.
[0055]
In order to manufacture a liquid crystal display device, the gate electrode and the gate wiring are preferably formed by combining a heat-resistant conductive material and a low-resistance conductive material. If the screen size is up to about 4 types, a two-layer structure in which a conductive layer (A) made of a nitride of a heat-resistant conductive material and a conductive layer (B) made of a heat-resistant conductive material are laminated. The conductive layer (B) may be formed of an element selected from Al, Cu, Ta, Ti, W, Nd, Cr, an alloy containing the element as a component, or an alloy film combining the elements. (A) is formed of a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium nitride (TiN) film, or the like. For example, a two-layer structure in which Cr as the conductive layer (A) and Al containing Nd as the conductive layer (B) are stacked is preferable. The conductive layer (A) is 10 to 100 nm (preferably 20 to 50 nm), and the conductive layer (B) is 200 to 400 nm (preferably 250 to 350 nm).
[0056]
On the other hand, for application to large screens of class 4 or higher, a conductive layer (A) made of a heat-resistant conductive material, a conductive layer (B) made of a low-resistance conductive material, and a conductive layer made of a heat-resistant conductive material ( A three-layer structure in which C) is laminated is preferable. The conductive layer (B) made of a low-resistance conductive material is formed of a material containing aluminum (Al) as a component. In addition to pure Al, 0.01 to 5 atomic% of scandium (Sc), Ti, Nd, silicon Al containing (Si) or the like is used. The conductive layer (C) has an effect of preventing hillocks from being generated in Al of the conductive layer (B). The conductive layer (A) is 10 to 100 nm (preferably 20 to 50 nm), the conductive layer (B) is 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (C) is 10 to 100 nm (preferably 20 to 50 nm). In this embodiment, the conductive layer (A) is formed to a thickness of 50 nm with a Ti film by sputtering using Ti as a target, and the conductive layer (B) is formed to a thickness of 200 nm with an Al film by sputtering using Al as a target. Then, a conductive layer (C) is formed to a thickness of 50 nm with a Ti film by sputtering using Ti as a target.
[0057]
Next, an insulating film 104a is formed over the entire surface. The insulating film 104a is formed by sputtering and has a thickness of 50 to 200 nm. For example, a silicon nitride film is used as the insulating film 104a and is formed with a thickness of 150 nm. Of course, the gate insulating film is not limited to such a silicon nitride film, and other insulating films such as a silicon oxide film, a silicon oxynitride film, and a tantalum oxide film are used, and a single layer or a stacked layer made of these materials is used. It may be formed as a structure. For example, a stacked structure in which the lower layer is a silicon nitride film and the upper layer is a silicon oxide film may be used.
[0058]
A first semiconductor film 105 is formed over the entire surface of the insulating film 104a with a thickness of 50 to 200 nm (preferably 100 to 150 nm) by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon (a-Si) film is formed to a thickness of 150 nm by sputtering using a silicon target. In addition, the first semiconductor film includes a microcrystalline semiconductor film, an amorphous silicon germanium film (Si X Ge (1-X) , (0 <X <1)), amorphous silicon carbide (Si X C Y It is also possible to apply a compound semiconductor film having an amorphous structure such as
[0059]
Next, a second semiconductor film of one conductivity type (containing an n-type or p-type impurity element) is formed to a thickness of 20 to 80 nm. The one-conductivity-type second semiconductor film is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second semiconductor film 106 of one conductivity type is formed using a silicon target to which phosphorus (P) is added. Alternatively, a silicon target may be used for sputtering to form a film in an atmosphere containing phosphorus. In addition, the second semiconductor film may be formed using a hydrogenated microcrystalline silicon film (μc-Si: H).
[0060]
The first conductive film 107 made of a metal material is formed by a sputtering method or a vacuum evaporation method. The material of the first conductive film 107 is not particularly limited as long as it is a metal material that can be in ohmic contact with the second semiconductor film 106, and an element selected from Al, Cr, Ta, and Ti, or the element as a component Or an alloy film in which the above elements are combined. In this embodiment, a sputtering method is used. As the first conductive film 107, a Ti film with a thickness of 50 to 150 nm and aluminum (Al) with a thickness of 300 to 400 nm are formed on the Ti film, Further, a Ti film having a thickness of 100 to 150 nm is formed thereon (FIG. 2A).
[0061]
The insulating film 104a, the first semiconductor film 105, the one-conductivity-type second semiconductor film 106, and the first conductive film 107 are all formed by a known method, and are manufactured by a plasma CVD method or a sputtering method. can do. In this example, these films (104a, 105, 106, 107) were continuously formed by a sputtering method by appropriately switching the target and the sputtering gas. At this time, in the sputtering apparatus, it is preferable to use the same reaction chamber or a plurality of reaction chambers and to continuously laminate these films without exposing them to the atmosphere. In this way, mixing of impurities can be prevented by not exposing to the atmosphere.
[0062]
Then, using the second photomask, a photolithography process is performed to form a resist mask 108. Unnecessary portions are removed by etching to form wirings (source wirings and drain electrodes in a later process) 111. As an etching method at this time, wet etching or dry etching is used. At this time, the first conductive film 107, the one-conductivity-type second semiconductor film 106, and the first semiconductor film 105 are sequentially etched according to the pattern of the resist mask 108. In this step, not only the wiring but also the pattern of the semiconductor layer forming the TFT is formed at the same time. In the TFT formation portion, a wiring 111 made of a first conductive film, a second semiconductor film 110 containing an impurity element imparting n-type conductivity, and a first semiconductor film 109 are formed. In this example, SiCl Four And Cl 2 And BCl Three The first conductive film 107 in which a Ti film, an Al film, and a Ti film are sequentially stacked is etched by dry etching using a mixed gas of 1 as a reaction gas, and the reaction gas is changed to CF Four And O 2 Instead of the mixed gas, the first semiconductor film 105 and the second semiconductor film 106 containing an impurity element imparting n-type conductivity are selectively removed (FIG. 2B). Further, the capacitor wiring 103 and the insulating film 104a are left in the capacitor portion, and similarly, the terminal 101 and the insulating film 104a remain in the terminal portion. A top view of this state is shown in FIG. However, for simplification, the second conductive film 112 formed on the entire surface is not shown in FIG.
[0063]
Next, after removing the resist mask 108, a mask that covers the entire surface of the pixel region is formed by screen printing, and the insulating film 104a that covers the pad portion of the terminal portion is selectively removed. Since this process does not require high alignment accuracy, it can be performed using screen printing or a shadow mask. Thus, the insulating film 104b is formed (FIG. 2C).
[0064]
Then, a second conductive film 112 made of a transparent conductive film is formed over the entire surface (FIG. 2D). The material of the second conductive film 112 is indium oxide (In 2 O Three ) Or indium tin oxide alloy (In 2 O Three -SnO 2 , Abbreviated as ITO) or the like using a sputtering method or a vacuum deposition method. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, etching of ITO is likely to generate a residue, so in order to improve etching processability, an indium oxide-zinc oxide alloy (In 2 O Three —ZnO) may also be used. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and excellent thermal stability as compared with ITO, even if the wiring 111 in contact with the second conductive film 112 is formed of an Al film, a corrosion reaction occurs. Can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0065]
Next, resist masks 113a to 113c are formed by a photolithography process using a third photomask. Then, unnecessary portions are removed by etching, so that the first semiconductor film 114, the source region 115 and the drain region 116, the source electrode 117 and the drain electrode 118, and the pixel electrode 119 are formed (FIG. 3A). In this photolithography process, the second conductive film 112 is patterned, and at the same time, the wiring 111, the one-conductivity-type second semiconductor film 110, and a part of the first semiconductor film 109 are removed by etching to form openings. To do. In this embodiment, first, the second conductive film 112 made of ITO is selectively removed by wet etching using a mixed solution of nitric acid and hydrochloric acid or a ferric chloride solution, and the wiring 111 is formed by wet etching. After the selective removal, the second semiconductor film 110 containing the impurity element imparting n-type conductivity and part of the first semiconductor film 109 were etched by dry etching. In this embodiment, wet etching and dry etching are used. However, the practitioner may appropriately select the reaction gas and perform only dry etching, or the practitioner may appropriately select the reaction solution and perform wet etching. You may do it alone.
[0066]
In addition, the bottom of the opening reaches the first semiconductor film, and the first semiconductor film 114 having a recess is formed. By this opening, the wiring 111 is separated into the source wiring 117 and the drain electrode 118, and the one-conductivity-type second semiconductor film 110 is separated into the source region 115 and the drain region 116. In addition, the second conductive film 120 in contact with the source wiring covers the source wiring and serves to prevent static electricity generated in a subsequent manufacturing process, particularly a rubbing process. In this embodiment, the second conductive film 120 is formed over the source wiring, but the second conductive film 120 may be removed. In this photolithography process, a storage capacitor is formed by the capacitor wiring 103 and the pixel electrode 119 using the insulating film 104b in the capacitor portion as a dielectric. In addition, in this photolithography process, a second conductive film made of a transparent conductive film is formed which is covered with the resist mask 113c and formed in the terminal portion.
[0067]
Next, the resist masks 113a to 113c were removed. A cross-sectional view of this state is shown in FIG. FIG. 1 is a top view of one pixel, and cross-sectional views along line AA ′ and BB ′ correspond to FIG. 3B, respectively.
[0068]
FIG. 11A is a top view of the gate wiring terminal portion 501 and the source wiring terminal portion 502 in this state. In addition, the same code | symbol is used for the location corresponding to FIGS. 1-3. FIG. 11B corresponds to a cross-sectional view taken along the line EE ′ and the line FF ′ in FIG. In FIG. 11A, reference numeral 503 made of a transparent conductive film denotes a connection electrode that functions as an input terminal. In FIG. 11B, reference numeral 504 denotes an insulating film (extending from 104b), 505 denotes a first amorphous semiconductor film (extending from 114), and 506 includes an impurity element imparting n-type conductivity. A second amorphous semiconductor film (extending from 115).
[0069]
In this manner, the pixel TFT having the inverted staggered n-channel TFT 201 and the storage capacitor 202 can be completed by three photolithography processes using the three photomasks. By arranging these in a matrix corresponding to each pixel to form a pixel portion, one substrate for manufacturing an active matrix electro-optical device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0070]
Next, the alignment film 121 is selectively formed only on the pixel portion of the active matrix substrate. As a method of selectively forming the alignment film 121, a screen printing method may be used, or a method of forming and removing a resist mask using a shadow mask after applying the alignment film may be used. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. Then, the alignment film 121 is subjected to a rubbing process so that the liquid crystal molecules are aligned with a certain pretilt angle.
[0071]
Next, the active matrix substrate and the counter substrate 124 provided with the counter electrode 122 and the alignment film 123 are bonded to each other with a sealant while maintaining a substrate interval with a spacer, and then a liquid crystal is interposed between the active matrix substrate and the counter substrate. Material 125 is injected. A known material may be used as the liquid crystal material 125, and TN liquid crystal is typically used. After injecting the liquid crystal material, the injection port is sealed with a resin material (FIG. 3C).
[0072]
As shown in the second embodiment, a stick driver in which a drive circuit is formed is attached to the terminal portion. Different drive circuits are used for the stick driver on the scanning line side and the source line side. In this manner, an active matrix liquid crystal display device in which a pixel region is manufactured using three photomasks can be completed.
[0073]
[Example 2]
In this embodiment, an example in which a protective film is formed on the pixel TFT manufactured in Embodiment 1 is shown in FIG. Since the present embodiment is the same up to the state of FIG. 3B of the first embodiment, different points will be described below. In addition, the same reference numerals are used for portions corresponding to FIG.
[0074]
First, after obtaining the state of FIG. 3B according to Example 1, a thin inorganic insulating film is formed on the entire surface. As the thin inorganic insulating film, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a tantalum oxide film may be used and formed as a single layer or a laminated structure made of these materials.
[0075]
Next, a photolithography process is performed using a fourth photomask, a resist mask is formed, unnecessary portions are removed by etching, and an insulating film 402 is formed in the pixel TFT portion and an inorganic insulating film 401 is formed in the terminal portion. Form each one. The inorganic insulating films 401 and 402 function as a passivation film. In the terminal portion, the thin inorganic insulating film 401 is removed by a fourth photolithography process, and the second conductive film made of a transparent conductive film formed on the terminal 101 in the terminal portion is exposed.
[0076]
Thus, in this embodiment, an inverted staggered n-channel TFT protected by an inorganic insulating film and a storage capacitor can be completed by four photolithography processes using four photomasks. These can be arranged in a matrix corresponding to each pixel, and a pixel portion can be formed to form one substrate for manufacturing an active matrix electro-optical device. The present embodiment can be combined with the configuration of the first embodiment.
[0077]
[Example 3]
Embodiment 1 mainly shows an example in which an insulating film, a first amorphous semiconductor film, a second amorphous semiconductor film of one conductivity type, and a first conductive film are formed by a sputtering method. In the example, an example using a plasma CVD method is shown. Specifically, an insulating film, a first amorphous semiconductor film, and a one-conductivity-type second semiconductor film are formed by a plasma CVD method.
[0078]
In this embodiment, a silicon oxynitride film is used as the insulating film and is formed with a thickness of 150 nm by plasma CVD. At this time, in the plasma CVD apparatus, the power supply frequency is 13 to 70 MHz, preferably 27 to 60 MHz. In particular, by using a power supply frequency of 27 to 60 MHz, a dense insulating film can be formed, and the breakdown voltage as a gate insulating film can be increased. SiH Four And NH Three N 2 A silicon oxynitride film manufactured by adding O is a preferable material for this application because the internal stress of the film is relieved. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and other insulating films such as a silicon oxide film, a silicon nitride film, and a tantalum oxide film are used, and a single layer or a stacked layer made of these materials is used. It may be formed as a structure. Also good. For example, a stacked structure in which a lower layer is a silicon nitride film and an upper layer is a silicon oxide film is a preferable form as a gate insulating film.
[0079]
In the case where a silicon oxide film is used, tetraethyl orthosilicate (TEOS) and O2 are formed by plasma CVD. 2 The reaction pressure is 40 Pa, the substrate temperature is 250 to 350 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. 2 And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 300 to 400 ° C. thereafter.
[0080]
As the first semiconductor film, a hydrogenated amorphous silicon (a-Si: H) film is typically formed to a thickness of 100 nm by a plasma CVD method. At this time, in the plasma CVD apparatus, the power supply frequency may be 13 to 70 MHz, preferably 27 to 60 MHz. By using a power supply frequency of 27 to 60 MHz, it becomes possible to improve the deposition rate, and the deposited film is preferable because it becomes an a-Si film with a low defect density. In addition, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film can be applied to the first amorphous semiconductor film. In the film formation of the amorphous semiconductor film by the plasma CVD method, if pulse modulated discharge of 100 to 100 kHz is performed, the generation of particles due to the gas phase reaction of the plasma CVD method can be prevented, and the generation of pinholes in the film formation is prevented. Since it can prevent, it is preferable.
[0081]
In this embodiment, as the semiconductor film containing the impurity element of one conductivity type, a second amorphous semiconductor film of one conductivity type is formed with a thickness of 20 to 80 nm. For example, an a-Si: H film containing an n-type impurity element may be formed. For this purpose, silane (SiH Four ) Phosphine (PH Three ) Is added. Alternatively, a hydrogenated microcrystalline silicon film (μc-Si: H) may be used instead of the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity.
[0082]
These films can be continuously formed by appropriately switching the reaction gas. In the plasma CVD apparatus, the same reaction chamber or a plurality of reaction chambers can be used, and these films can be continuously stacked without being exposed to the atmosphere. In this way, continuous film formation without exposure to the atmosphere can prevent impurities from being mixed into the first semiconductor film.
[0083]
[Example 4]
As shown in FIG. 2, in the step of sequentially and successively laminating an insulating film, a first amorphous semiconductor film, a second amorphous semiconductor film of one conductivity type, and a first conductive film, a sputtering apparatus Alternatively, as one form of plasma CVD apparatus, a multi-chamber type apparatus including a plurality of reaction chambers can be applied.
[0084]
FIG. 13 shows an outline of the multi-chamber type apparatus (continuous film forming system) as viewed from above. The configuration of the apparatus includes load / unload chambers 10 and 15 and chambers 11 to 14 for forming a film, and each chamber is connected to a common chamber 20. A vacuum exhaust pump and a gas introduction system are disposed in the load / unload chamber, the common chamber, and each chamber.
[0085]
The load / unload chambers 10 and 15 are load lock chambers for carrying the processing substrate 30 into the chamber. The first chamber 11 is a reaction chamber for forming the insulating film 104. The second chamber 12 is a reaction chamber for forming the first amorphous semiconductor film 105. The third chamber 13 is a reaction chamber for forming a single conductivity type amorphous semiconductor film 106. The fourth chamber 14 is a reaction chamber for forming the first conductive film 107.
[0086]
An example of the operation of such a multi-chamber apparatus will be described. Initially, all the chambers are once evacuated to a high vacuum state, and then a gas such as nitrogen or argon is flowed to maintain the pressure in the chamber at a pressure of about 0.01 to 5 Pa, thereby back diffusion from the exhaust port. And contamination due to degassing from the inner wall of the chamber.
[0087]
The processing substrate is set in the load / unload chamber 10 together with the cassette 28 in which a large number of substrates are stored. The processing substrate is taken out of the cassette by opening the gate valve 22 and transferred to the common chamber 20 by the robot arm 21. At this time, alignment is performed in the common room. In addition, this board | substrate 30 used what formed wiring 101,102,103 obtained according to Example 1. FIG.
[0088]
Here, the gate valve 22 is closed, and then the gate valve 23 is opened. Then, the processing substrate 30 is transferred to the first chamber 11. In the first chamber, film formation is performed at a temperature of 150 ° C. to 300 ° C. to obtain the insulating film 104. Note that as the insulating film, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, a stacked film of these, or the like can be used. In this embodiment, a single layer silicon nitride film is used, but a laminated structure of two layers or three or more layers may be used. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.
[0089]
After completion of the formation of the insulating film, the processing substrate is drawn out to the common chamber by the robot arm and transferred to the second chamber 12. In the second chamber, as in the first chamber, film formation is performed at a temperature of 150 ° C. to 300 ° C., and the first semiconductor film 105 is obtained by a plasma CVD method. Note that as the first amorphous semiconductor film, a microcrystalline semiconductor film, an amorphous germanium film, an amorphous silicon / germanium film, or a stacked film thereof can be used. Further, the heat treatment for reducing the hydrogen concentration may be omitted by setting the formation temperature of the first semiconductor film to 350 ° C. to 500 ° C. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.
[0090]
After completion of the formation of the first semiconductor film, the processing substrate is drawn out to the common chamber and transferred to the third chamber 13. In the third chamber, as in the second chamber, film formation is performed at a temperature of 150 ° C. to 300 ° C., and a first conductivity type first film containing an impurity element (P or As) imparting n-type by plasma CVD is used. 2 semiconductor film 106 is obtained. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.
[0091]
After the formation of the second semiconductor film of one conductivity type, the processing substrate is drawn out to the common chamber and transferred to the fourth chamber 14. In the fourth chamber, the first conductive film 107 is obtained by a sputtering method using a metal target.
[0092]
The substrate to be processed on which the four layers are continuously formed in this way is transferred to the load lock chamber 15 by the robot arm and stored in the cassette 29.
[0093]
[Example 5]
In the fourth embodiment, an example in which a plurality of chambers are used for continuous lamination is shown. In this embodiment, the apparatus shown in FIG. 14 is used for continuous lamination while maintaining a high vacuum in one chamber. The method can also be adopted.
[0094]
In this example, the apparatus system shown in FIG. 14 was used. In FIG. 14, 40 is a processing substrate, 50 is a common chamber, 44 and 46 are load lock chambers, 45 is a chamber, and 42 and 43 are cassettes. In this embodiment, in order to prevent contamination that occurs when the substrate is conveyed, the layers are formed in the same chamber.
[0095]
When the apparatus shown in FIG. 14 is applied to the first embodiment, a plurality of targets are prepared in the chamber 45, and the reaction gases are sequentially replaced to form the insulating film 104, the first semiconductor film 105, and the one conductivity type second. The semiconductor film 106 and the first conductive film 107 may be stacked.
[0096]
In the case of application to Embodiment 4, the reaction gas may be sequentially changed to sequentially stack the insulating film 104, the first amorphous semiconductor film 105, and the one-conductivity-type second semiconductor film 106.
[0097]
[Example 6]
As shown in Embodiment 4, in the manufacturing process of a TFT using a plasma CVD method, the second semiconductor film of one conductivity type can be formed using a microcrystalline semiconductor film. Silane gas (SiH) diluted with hydrogen at a substrate heating temperature during film formation of 80 to 300 ° C., preferably 140 to 200 ° C. Four : H 2 = 1: 10-100) and phosphine (PH Three ) As a reaction gas, gas pressure 0.1 to 10 Torr, discharge power 10 to 300 mW / cm 2 Thus, a microcrystalline silicon film can be obtained. Alternatively, phosphorus (P) may be formed by plasma doping after the microcrystalline silicon film is formed. By forming the second semiconductor film of one conductivity type with a microcrystalline semiconductor film, the resistance of the source and drain regions can be reduced, and the characteristics of the TFT can be improved.
[0098]
[Example 7]
In Embodiments 1 to 3, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device is shown. In this embodiment, an example applied to a reflective liquid crystal display device will be described with reference to FIGS. . 15 is a cross-sectional view, FIG. 16 is a top view, and FIG. 15 shows a cross-sectional structure taken along the chain line GG ′ in FIG. 16 and a cross-sectional structure corresponding to the surface cut along HH ′. ing.
[0099]
First, a substrate having an insulating surface is prepared. In this embodiment, in addition to a light-transmitting substrate such as a glass substrate, a quartz substrate, and a plastic substrate, the substrate is a reflective type, and therefore an insulating film is formed on a semiconductor substrate, a stainless steel substrate, a ceramic substrate, or the like. But you can.
[0100]
Next, after a conductive film made of a metal material is formed over the substrate, a resist pattern is formed using a first photomask, and then a gate wiring 750 and a convex portion 751 are formed by an etching process. The convex portion is arranged in a region surrounded by the gate wiring and the source wiring, that is, a region serving as a display region where a pixel electrode is formed. In addition, the shape of the convex part 751 is not specifically limited, The cross section of radial direction may be a polygon, and the shape which is not left-right symmetric may be sufficient. For example, the shape of the convex portion 751 may be a columnar shape or a prism shape, or may be a cone shape or a pyramid shape. Further, the convex portions 751 may be arranged regularly or irregularly. In this embodiment, since the gate wiring desirably has a tapered shape, the convex portion 751 also has a tapered pyramid shape. The angle of the tapered portion is 5 to 45 degrees, preferably 5 to 25 degrees.
[0101]
Next, an insulating film (gate insulating film) 752, a first semiconductor film, a one-conductivity-type second semiconductor film, and a first conductive film are sequentially stacked. Note that either an amorphous semiconductor or a microcrystalline semiconductor may be used for the first semiconductor film. A microcrystalline semiconductor may be used as the second semiconductor film of one conductivity type as shown in Embodiment 6. Further, these films can be formed using a sputtering method or a plasma CVD method in a plurality of chambers or in the same chamber without being continuously exposed to the atmosphere. By not exposing to the atmosphere, contamination of impurities can be prevented. The insulating film 752 is formed on the substrate on which the projecting portion 751 is formed, and has an uneven surface.
[0102]
Next, after a resist pattern is formed using a second photomask, the first conductive film, the second semiconductor film, and the first semiconductor film are etched by an etching process. Thus, a source wiring 608 and an electrode (drain electrode) 609 are formed, and a first semiconductor film 605 is formed. By this etching process, a source layer, a drain electrode, and a semiconductor layer for forming a TFT are formed in a predetermined pattern.
[0103]
Thereafter, a second conductive film is formed on the entire surface. Note that a reflective conductive film is used as the second conductive film. Although it is desirable to apply Al, Ag, or the like as such a conductive film, a layer of Ti, Ta, or the like may be formed as a barrier metal layer for the lower layer because of poor heat resistance.
[0104]
Next, after forming a resist pattern using a third photomask, etching is performed to form a pixel electrode 604 made of the second conductive film. Thus, the surface of the insulating film formed on the convex portion 601 has unevenness, and the pixel electrode 604 is formed on the insulating film 602 having the unevenness on the surface. Therefore, the surface of the pixel electrode 604 is made uneven. Light scattering properties.
[0105]
Further, with the configuration of this embodiment, the number of photomasks used in the photolithography technique can be three when the pixel TFT portion is manufactured. Conventionally, it has been necessary to increase the number of steps for forming the convex and concave portions. However, in this embodiment, since the convex portions are formed simultaneously with the gate wiring, the convex and concave portions can be formed in the pixel electrode without increasing the number of steps.
[0106]
[Example 8]
In this embodiment, a method for manufacturing a TFT suitable for a stick driver on the scanning line side will be mainly described. A shift register circuit, a buffer circuit, and the like are formed in the stick driver on the scanning line side. Here, it is assumed that the shift register circuit is driven at 3 to 5V and the buffer circuit is driven at 33V. Since the TFTs constituting the buffer circuit are required to have a high breakdown voltage, it is necessary to make the gate insulating film thicker than the TFTs of other circuits. The manufacturing method will be described with reference to FIGS.
[0107]
In FIG. 17A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass or the like is used for the substrate 301. Since such a glass substrate shrinks slightly depending on the heating temperature, the shrinkage rate of the substrate can be reduced by using a substrate that has been heat-treated at a temperature 500 to 650 ° C. above the glass strain point.
[0108]
The blocking layer 302 is provided to prevent a slight amount of alkali metal contained in the substrate 301 from diffusing into the semiconductor layer, and is formed using an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In order to stabilize the threshold voltage (Vth) of the TFT, it is desirable that the stress of the blocking layer is a tensile stress. The stress is controlled according to the manufacturing conditions of the insulating film. For that purpose, the blocking layer is not limited to a single layer, and may be formed by laminating a plurality of insulating films having different compositions. For example, SiH by plasma CVD method Four , NH Three , N 2 A silicon oxynitride film made of O is formed to 10 to 200 nm (preferably 50 to 100 nm) and similarly SiH Four , N 2 A silicon oxynitride film formed from O can be stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm) to form a blocking layer.
[0109]
The semiconductor film 303 having an amorphous structure is formed with a thickness of 25 to 100 nm. As a typical example of a semiconductor film having an amorphous structure, an amorphous silicon (a-Si) film, an amorphous silicon-germanium (a-SiGe) film, an amorphous silicon carbide (a-SiC) film, There are crystalline silicon tin (a-SiSn) films, and any of them can be applied. These semiconductor films having an amorphous structure are formed by a plasma CVD method, a sputtering method, a low pressure CVD method, or the like, and are formed so as to contain about 0.1 to 40 atomic% of hydrogen in the film. A suitable example is SiH by plasma CVD. Four Or SiH Four And H 2 The film thickness is 55 nm. SiH Four Instead of Si 2 H 6 May be used.
[0110]
Then, a catalytic element that can lower the crystallization temperature of the amorphous semiconductor film is added. The catalyst element can be directly injected into the amorphous semiconductor film. However, the layer 304 containing the catalyst element is formed by spin coating, printing, spraying, bar coater, sputtering, or vacuum deposition. It may be formed to a thickness of ˜5 nm. Examples of such catalytic elements are nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co) with respect to amorphous silicon. Platinum (Pt), copper (Cu), and gold (Au) are known to be effective. In order to form the layer 304 containing the catalytic element by spin coating, an aqueous solution containing 1 to 100 ppm (preferably 10 ppm) of the catalytic element in terms of weight is applied by rotating the substrate with a spinner.
[0111]
In the crystallization step shown in FIG. 17B, first, heat treatment is performed at 400 to 500 ° C. for about 1 hour, so that the amount of hydrogen contained in the amorphous silicon film is 5 atom% or less. Then, using a furnace annealing furnace, heat treatment is performed at 550 to 600 ° C. for 1 to 8 hours in a nitrogen atmosphere. Preferably, heat treatment is performed at 550 ° C. for 4 hours. Thus, the crystalline semiconductor film 305 can be obtained. By such a thermal crystallization method, a crystalline silicon film having a crystal structure is formed from the amorphous silicon film.
[0112]
However, an amorphous region may remain locally in the crystalline semiconductor film 305 manufactured by this thermal crystallization method. In such a case, the Raman spectroscopy is 480 cm. -1 The presence of an amorphous component having a broad peak can be confirmed. The laser crystallization method is suitable for the purpose of crystallizing the remaining amorphous region.
[0113]
Laser light sources used in the laser crystallization method include excimer laser, YAG laser, YVO Four Laser, YAlO Three A laser, a YLF laser, or the like can be used. An excimer laser can radiate light having a wavelength of 400 nm or less with high output, and thus can be suitably used for crystallization of a semiconductor film. On the other hand, YAG laser, YVO Four Laser, YAlO Three A solid laser such as a laser or a YLF laser uses the second harmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic (266 nm). Due to the penetration depth of light, the second harmonic (532 nm) is used from the surface and inside of the semiconductor film, and the third harmonic (355 nm) and the fourth harmonic (266 nm) are used in the same manner as the excimer laser. Crystallization can be performed by heating from the surface of the semiconductor film.
[0114]
FIG. 17C shows such a state. For example, an Nd: YAG laser is used, its pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 100 to 500 mJ / cm. 2 (Typically 100-400mJ / cm 2 ) And scanning the linear laser beam 306 formed by an optical system including a cylindrical lens in a direction perpendicular to the longitudinal direction (or relatively moving the substrate). The line width of the linear laser beam 306 is 100 to 1000 μm, for example, 400 μm. In this way, by using the thermal crystallization method and the laser crystallization method in combination, the crystalline semiconductor film 307 with high crystallinity can be formed.
[0115]
The crystalline semiconductor film 307 formed as described above is suitable for forming a channel formation region, a source region, a drain region, an LDD region, and the like as an active layer of a TFT. Microscopically, a crystalline silicon film manufactured by a thermal crystallization method using a catalytic element such as nickel has a structure in which a plurality of needle-like or rod-like crystals are aggregated. However, it is expected that the continuity of adjacent crystal grains is high and almost no dangling bonds are formed. Most of the crystal grains are oriented to <110>. One reason is that the crystal growth process using a catalyst element such as nickel is considered to involve the silicide of the catalyst element, and the thickness of the semiconductor film is as thin as 25 to 100 nm. Among the initial nuclei, those whose (111) plane is substantially perpendicular to the substrate surface preferentially grow, so it is considered that the <110> orientation is substantially increased.
[0116]
After that, the crystalline semiconductor film 307 forms island-shaped semiconductor layers 308 to 311 by etching treatment. In FIG. 17D, four semiconductor layers are shown for convenience. In the following description, TFTs for circuits driven at a low voltage such as a shift register circuit are formed for the semiconductor layers 308 and 309, and TFTs for circuits driven at a high voltage such as a buffer circuit are formed for the semiconductor layers 310 and 311, respectively. This will be explained as a premise.
[0117]
The gate insulating film formed over the semiconductor layer is formed with a different thickness even if the TFT is formed over the same substrate in consideration of circuit drive voltage. Therefore, a two-stage film formation process is required. First, the gate insulating film first layer 312 is formed to a thickness of 40 to 200 nm (preferably 70 to 90 nm). Then, the first layer of the gate insulating film over the semiconductor layers 308 and 309 is selectively etched and removed to form a state as shown in FIG.
[0118]
Subsequently, as shown in FIG. 17F, a gate insulating film second layer 313 is formed in the same manner. As a result, when the gate insulating film first layer 312 and the gate insulating film second layer 313 are formed to a thickness of 80 nm, the thickness of the gate insulating film on the semiconductor layers 308 and 309 is 80 nm. Thus, the thickness of the gate insulating film of the semiconductor layers 310 and 311 can be 160 nm.
[0119]
The gate insulating film is formed of an insulating film containing silicon using a plasma CVD method or a sputtering method. SiH by plasma CVD Four And N 2 A silicon oxynitride film formed from a mixed gas of O is a material suitable for a gate insulating film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and an insulating film containing other silicon may be used. When a silicon oxide film is applied, TEOS (Tetraethyl Orthosilicate) and O 2 The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. 2 And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0120]
A conductive film for forming a gate electrode is formed on the gate insulating film thus manufactured. The gate electrode of the TFT shown in this embodiment is formed by laminating two kinds of conductive materials having a selection ratio of 5 to 20 (preferably 10 to 13) or more by a dry etching method. For example, a first conductive film made of a nitride conductive material and a second conductive film made of a heat-resistant conductive material that can withstand heat treatment at 400 to 650 ° C. are used. As a specific example thereof, the first conductive film is formed using a material selected from tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN), and the second conductive film is formed using tantalum (Ta), It is formed of one or more alloy materials selected from titanium (Ti), tungsten (W), and molybdenum (Mo). Of course, applicable gate electrode materials are not limited to the materials described here, and other conductive materials can be selected as long as they are combinations of conductive materials satisfying the above specifications. Note that the selectivity here refers to the ratio of the etching rate of the second conductive film to the first conductive film.
[0121]
In the present embodiment, although not shown, the first conductive film is formed with a TaN film to a thickness of 50 to 100 nm, and the second conductive film is formed with a W film to a thickness of 100 to 400 nm. The TaN film is formed by sputtering using a Ta target and sputtering with a mixed gas of Ar and nitrogen. The W film is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF 6 It can also be formed by a thermal CVD method using In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Using a W target with a purity of 99.9999%, and forming a W film with sufficient consideration to prevent impurities from entering the gas phase during film formation, a resistivity of 9 to 20 μΩcm is achieved. can do.
[0122]
The gate electrode is formed by a two-stage etching process. As shown in FIG. 18A, a resist mask 314 is formed, and a first etching process is performed. The etching method is not limited, but preferably an ICP (Inductively Coupled Plasma) etching apparatus is used, and CF is used as an etching gas. Four And Cl 2 The plasma is generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 0.5 to 2 Pa, preferably 1 Pa. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF Four And Cl 2 When W is mixed, the W film and the Ta film can be etched at the same rate.
[0123]
In the first etching treatment, the end portions of the first conductive film and the second conductive film are processed so as to have a tapered shape. The angle of the tapered portion is 15 to 45 °. However, in order to perform etching without leaving a residue on the gate insulating film, it is preferable to perform an overetching process that increases the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 315 to 318 (the first conductive layers 315a to 318a and the second conductive layers 315b to 318b) formed of the first conductive film and the second conductive film by the first etching treatment. Form.
[0124]
Next, a second etching process is performed as shown in FIG. Using ICP etching equipment, CF as etching gas Four And Cl 2 And O 2 And 500 W of RF power (13.56 MHz) is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage) so that the self-bias voltage is lower than that in the first etching process. Under such conditions, the W film is anisotropically etched, and the Ta film is anisotropically etched at a slower etching rate to form second-shaped conductive films 319 to 322 (first conductive layers 319a to 322a). And second conductive layers 319b to 322b) are formed. Although the gate insulating film is not shown in detail in the drawing, a region not covered with the second shape conductive layers 315 to 318 is etched and thinned by about 20 to 50 nm.
[0125]
Then, as shown in FIG. 18C, two types of impurity regions having different concentrations are formed. All of the impurity regions are n-type, and an impurity element imparting n-type such as phosphorus (P) or arsenic (As) is added by an ion doping method or an ion implantation method. In the first doping treatment, first impurity regions 323 to 326 are formed in a self-aligning manner using the second conductive layers 319b to 322b as masks. Conceptually, a condition of high acceleration voltage and low dose is selected, and the concentration of the impurity element imparting n-type added to the first impurity regions 323 to 326 is 1 × 10 5. 16 ~ 1x10 19 atoms / cm Three So that the concentration becomes. For example, phosphine (PH Three ), The acceleration voltage is set to 70 to 120 keV, and 1 × 10 13 /cm 2 Dosage amount of
[0126]
Next, in the second doping process to be performed, the condition of low acceleration and high dose is selected, and the impurity regions 327 to 330 are formed. The impurity concentration of the second impurity regions 327 to 330 is 1 × 10 20 ~ 1x10 twenty one atoms / cm Three To be in the range. Therefore, an example of the conditions in the ion doping method is that the dose amount is 1 × 10 13 ~ 5x10 14 atoms / cm 2 And an acceleration voltage of 30 to 70 keV. Thus, the first impurity regions 323 to 326 formed in the semiconductor layer are formed so as to overlap with the first conductive layers 319 a to 322 a, and the second impurity regions 327 to 330 are formed of the second shape conductive layers 315 to 315. 318 is formed outside.
[0127]
Then, as shown in FIG. 18D, third impurity regions 332 to 335 to which an impurity element imparting p-type conductivity is added are formed in the semiconductor layers 308 and 310 forming the p-channel TFT. At this time, the entire surface of the island-like semiconductor layers 309 and 311 forming the n-channel TFT is covered with a resist mask 331. Phosphorus (P) is added to the impurity regions 332 to 335 at different concentrations, but diborane (B 2 H 6 An impurity element imparting p-type is added by an ion doping method using), and the impurity concentration imparting p-type is 2 × 10 even in the shifted region. 20 ~ 2x10 twenty one atoms / cm Three It forms so that it becomes.
[0128]
Through the above steps, impurity regions are formed in the respective semiconductor layers. The second conductive layers 319 to 322 function as gate electrodes. Then, a first interlayer insulating film 336 shown in FIG. 18E is formed. The first interlayer insulating film 336 is a silicon oxynitride film and has a thickness of 100 to 200 nm. Thereafter, a treatment for activating the impurity element added to each semiconductor layer is performed for the purpose of controlling the conductivity type. In this step, a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
[0129]
In laser annealing, excimer laser light with a wavelength of 400 nm or less, YAG laser, YVO Four The second harmonic of the laser (532 nm) is used. The activation conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 300 mJ / cm. 2 And When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 200 to 400 mJ / cm. 2 And good. Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.
[0130]
Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0131]
The second interlayer insulating film 337 is formed with an average film thickness of 1.0 to 2.0 μm using an inorganic insulating material such as silicon oxide or silicon oxynitride or an organic insulating material. As the organic insulating material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. in a clean oven. When acrylic is used, a two-component type is used, and after mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, preheating at 80 ° C. for 60 seconds with a hot plate. Further, it is formed by baking at 250 ° C. for 60 minutes using a clean oven.
[0132]
Then, wirings 338 to 345 which are in contact with the second impurity region or the third impurity region formed in the semiconductor layer are formed. This wiring is formed of a 50 to 200 nm Ti film 768a, a 100 to 300 nm Al film 768b, a 50 to 200 nm tin (Sn) film, or a Ti film. In the wirings 338 to 345 formed with such a structure, the Ti film formed first is in contact with the semiconductor layer, and the heat resistance of the contact portion is improved.
[0133]
As described above, a driver circuit having p-channel TFTs 346 and 348 and n-channel TFTs 347 and 349 can be formed. The gate insulating films of the p-channel TFT 348 and the n-channel TFT 349 are formed thicker than the gate insulating films of the p-channel TFT 346 and the n-channel TFT 347, and have a structure that increases the withstand voltage.
[0134]
The p-channel TFT 346 includes a channel formation region 350, a third impurity region 351 that overlaps with the second conductive layer 319 that is a gate electrode, and a third impurity region 352 that is formed outside the gate electrode. The p-channel TFT 348 includes a channel formation region 356, a third impurity region 357 that overlaps with the second conductive layer 321 that is a gate electrode, and a third impurity region 358 that is formed outside the gate electrode. Yes. The p-channel TFT has a single drain structure, and the third impurity region functions as a source or a drain.
[0135]
In the n-channel TFT 347, a channel formation region 353, a first impurity region 354 overlapping with the second conductive layer 320 which is a gate electrode, and a second impurity region 355 formed outside the gate electrode are formed. The n-channel TFT 349 includes a channel formation region 359, a first impurity region 360 that overlaps with the second conductive layer 322 that is a gate electrode, and a second impurity region 361 that is formed outside the gate electrode. . The first impurity regions 354 and 360 are LDD (Lightly Doped Drain) regions, and the second impurity regions 355 and 361 are regions functioning as a source region or a drain region. In particular, since the first impurity region has a GOLD (Gate Overlapped Drain) structure formed so as to overlap with the gate electrode, TFT deterioration due to the hot carrier effect can be prevented, and a high voltage of 10 V or more is applied. Even so, a very stable operation can be obtained.
[0136]
In any case, these TFTs may be formed with a channel length of 1 to 5 μm, preferably 1.5 to 2.5 μm. Therefore, the design rule to be applied may be 1 to 1.5 μm for the line and space (interval between the line width and the adjacent line) and about 2 μm for the contact hole.
[0137]
The TFT manufactured in this embodiment is suitable for forming a scanning line side stick driver. In particular, a p-channel TFT 348 and an n-channel TFT 349 shown in FIG. 18E are applied to a buffer circuit to which a high voltage of 30 V is applied. In addition, a p-channel TFT 346 and an n-channel TFT 347 may be applied to a shift register circuit or the like. Here, a process of forming an n-channel TFT and a p-channel TFT is shown, but it is easy to assume that a capacitor element and a resistor element are formed by this process, and are omitted. Further, the size of the TFT (channel length / channel width) necessary for circuit formation and the layout thereof should be considered by the practitioner.
[0138]
[Example 9]
The breakdown voltage required for the TFT of the stick driver provided on the source line side is about 12V, but the operating frequency is required to be 50 MHz or more (for example, 65 MHz) at 3V. In this embodiment, a method for manufacturing a TFT suitable for this purpose will be described.
[0139]
A crystalline semiconductor film that forms a channel formation region of a TFT is required to have high field effect mobility and low subthreshold coefficient (S value) realizable quality. That is, there is a demand for a crystalline semiconductor film having properties such as a defect level serving as a trap center or a recombination center and a low grain boundary potential. FIG. 19 shows an example of a method for manufacturing such a crystalline semiconductor film.
[0140]
In FIG. 19A, any substrate that can withstand heat treatment at 600 ° C. (preferably 950 ° C.) and has an insulating surface may be used as the substrate 401. Quartz substrates are suitable for quality and surface finish accuracy. The semiconductor film 402 having an amorphous structure formed in close contact with the substrate 401 is formed with a thickness of 25 to 100 nm by a plasma CVD method or a low pressure CVD method. As a typical example of a semiconductor film having an amorphous structure, an amorphous silicon (a-Si) film, an amorphous silicon-germanium (a-SiGe) film, an amorphous silicon carbide (a-SiC) film, There are crystalline silicon tin (a-SiSn) films, and any of them can be applied. Then, a layer containing a catalytic element that can lower the crystallization temperature of the amorphous semiconductor film is formed. In FIG. 19A, although formed over the semiconductor film 402 having an amorphous structure, it may be formed on the substrate side. The applicable catalytic element here is the same as in Embodiment 2, and is formed by the same method.
[0141]
Then, heat treatment is performed at 500 to 600 ° C. for 1 to 12 hours in an atmosphere such as nitrogen or argon to crystallize the semiconductor film having an amorphous structure. Prior to crystallization at this temperature, it is also necessary to release the hydrogen contained in the film by performing a heat treatment at 400 to 500 ° C. for about 1 hour. As a typical condition, a dehydrogenation treatment is performed at 450 ° C. for 1 hour, followed by a heat treatment at 570 ° C. for 8 hours. By such a thermal crystallization method, a crystalline semiconductor film 404 having a crystal structure is formed from the amorphous silicon film (FIG. 19B).
[0142]
However, the concentration of the catalytic element remaining in the crystalline semiconductor film 404 is approximately 5 × 10 16 ~ 2x10 18 atoms / cm 2 It is. The catalytic element is effective for crystallization of the semiconductor film, but becomes unnecessary for the purpose of using it as a functional material for forming a TFT thereafter. The catalytic element remaining in the crystalline semiconductor film forms a defect level as an impurity, forms a trap center or a recombination center, or causes a semiconductor junction failure. FIG. 19B illustrates a gettering process for removing the catalyst element. The concentration of the catalyst element in the crystalline semiconductor film is set to 1 × 10. 17 atms / cm Three Or less, preferably 1 × 10 16 atms / cm Three The purpose is to reduce it to a minimum.
[0143]
First, a mask insulating film 405 is formed with a thickness of 150 nm using a silicon oxide film or the like on the surface of the crystalline semiconductor film 404. Then, an opening 406 is provided outside the region where the active layer is formed to form a region where the surface of the crystalline semiconductor film is exposed. Then, phosphorus (P) is added by ion doping or ion implantation to selectively form a phosphorus (P) added region 407 in the crystalline semiconductor film. In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the phosphorus (P) added region 407 functions as a gettering site, and the crystalline semiconductor film 404 is formed. The remaining catalyst element can be segregated in the phosphorus (P) addition region 407.
[0144]
Thereafter, the mask insulating film 405 and the phosphorus (P) -added region 407 are removed by etching, so that the concentration of the catalytic element is 1 × 10 6. 17 atms / cm Three A crystalline semiconductor film 408 reduced to the following can be obtained (FIG. 19C).
[0145]
FIG. 20 shows another example of a method for forming a crystalline semiconductor film. In FIG. 20A, a substrate 410 and a semiconductor film 411 having an amorphous structure are similar to those described in FIG. A mask insulating film 412 is formed over the semiconductor film 411 having an amorphous structure, and an opening 414 is selectively formed. Thereafter, a solution containing 1 to 100 ppm of the catalyst element in terms of weight is applied to form the catalyst element-containing layer 413. The catalyst element-containing layer 413 has a structure in contact with the semiconductor film 411 having an amorphous structure only through the opening 414.
[0146]
Next, heat treatment is performed at 500 to 650 ° C. for 1 to 24 hours, for example, 600 ° C. for 12 hours to form a crystalline semiconductor film. In this crystallization process, crystallization proceeds from the semiconductor film 415 in contact with the catalytic element, and crystallization proceeds in a direction parallel to the surface of the substrate 410 (lateral direction). The crystalline semiconductor film formed in this way is made up of a collection of rod-like or needle-like crystals, and each crystal grows with a specific direction when viewed macroscopically, so that the crystallinity is uniform. There are advantages.
[0147]
After the crystalline semiconductor film is formed, a gettering process for removing the catalytic element from the crystalline semiconductor film is performed as in FIG. Phosphorus (P) is added from the previously formed opening 414 to form a phosphorus (P) added region 416 in the crystalline semiconductor film. In this state, heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours to segregate the catalyst element remaining in the crystalline semiconductor film in the phosphorus (P) addition region 416 ( FIG. 20 (C)).
[0148]
Thereafter, the mask insulating film 412 and the phosphorus (P) -added region 416 are removed by etching, so that the concentration of the catalytic element is 1 × 10 6. 17 atms / cm Three A crystalline semiconductor film 417 reduced to the following can be obtained (FIG. 20D).
[0149]
Both the crystalline semiconductor film 408 shown in FIG. 19C and the crystalline semiconductor film 417 shown in FIG. 20D are suitable for use in forming an active layer of a TFT. In FIG. 21A, semiconductor films 420 to 423 which are separated from such a crystalline semiconductor film in an island shape are formed. FIG. 21A shows four semiconductor layers for convenience. In the following description, it is assumed that TFTs of a circuit driven at a low voltage such as a shift register circuit are formed in the semiconductor layers 420 and 421, and TFTs driven at a high frequency such as a latch circuit are formed in the semiconductor layers 422 and 423, respectively. explain. In the latter case, the gate insulating film is formed thin in order to enable high-speed driving. For this purpose, a two-stage film formation process is performed.
[0150]
The gate insulating film formed over the semiconductor layer is formed with a different thickness even if the TFT is formed over the same substrate in consideration of circuit drive voltage. Therefore, a two-stage film formation process is required. First, an insulating film such as a silicon oxide film or a silicon oxynitride film is formed with a thickness of 20 to 50 nm, for example, 40 nm. Such an insulating film is formed by a plasma CVD method or a thermal CVD method. An example of manufacturing conditions in the thermal CVD method is SiH Four And N 2 A dense film can be formed by using O, at 800 ° C. and 40 Pa, and with an appropriate gas mixing ratio. After that, the insulating film formed over the semiconductor layers 422 and 423 is removed by etching with hydrofluoric acid or the like, so that the first insulating film 424 is formed. Further, the surface is washed cleanly, and an oxide film is formed in an atmosphere containing halogen (typically chlorine) at 800 to 1000 ° C. (preferably 950 ° C.).
The oxide film is formed to have a thickness of 30 to 50 nm (for example, 40 nm) in the semiconductor layers 422 and 423. As a result, an insulating film having a thickness of 80 nm is formed in the semiconductor layers 420 and 421. By forming an oxide film in a halogen atmosphere, a small amount of metal impurities and the like are removed, and a favorable insulating film in which the interface state density with the semiconductor film is reduced can be formed. Thus, the second insulating film 425 having different thicknesses is formed between the semiconductor layers 420 and 421 and the semiconductor layers 422 and 423, and this insulating film is used as a gate insulating film (FIG. 21B).
[0151]
Further, in FIG. 21B, a first conductive film 426 and a second conductive film 427 for forming a gate electrode are formed over the second insulating film 425. These conductive films are manufactured in the same manner as in the first embodiment. The first conductive film 426 is formed of a TaN film with a thickness of 50 to 100 nm, and the second conductive film 427 is formed of a W film with a thickness of 100 to 100 nm. It is formed to a thickness of 300 nm.
[0152]
Subsequent steps are performed in the same manner as in the second embodiment, and an n-channel TFT and a p-channel TFT are formed. The gate electrode is formed by a two-stage etching process. FIG. 21C illustrates a first shape conductive layers 429 to 432 (first conductive layers 429a to 432a and second conductive layer 429b) formed by a first etching process in which a resist mask 428 is formed and a taper etching process is performed. To 432b) are shown. In FIG. 21D, second shape conductive layers 433 to 436 (first conductive layers 433a to 436a and second conductive layers 433b to 436b) are formed by the second etching process by anisotropic etching. It shows the state that was done.
[0153]
The impurity regions of the n-channel TFT and the p-channel TFT are formed in a self-aligned manner using the second shape conductive layer. Two types of impurity regions having different concentrations are formed in the n-channel TFT. FIG. 21E shows the first impurity regions 437 to 440 formed by the first doping process (conditions for high acceleration voltage and low dose), and the conditions for the second doping process (low acceleration voltage and high dose). The second impurity regions 441 to 44 formed by As shown in FIG. 21F, the impurity region of the p-channel TFT is formed by forming a resist mask 445 so as to protect the region where the n-channel TFT is formed, and the p-type TFT by the third doping process. Regions 446 to 449 to which the impurity element to be added is added are formed.
[0154]
After these impurity regions are formed, a first interlayer insulating film 450 is formed, and a heat treatment at 400 to 700 ° C. is performed to activate the impurity elements. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the semiconductor layer and reduce the density of defect states. The second interlayer insulating film 451 is formed with an average film thickness of 1.0 to 2.0 μm using an inorganic insulating material such as silicon oxide or silicon oxynitride or an organic insulating material. The wirings 452 to 459 are formed of Al, Ti, or the like.
[0155]
As described above, a driver circuit having p-channel TFTs 460 and 462 and n-channel TFTs 461 and 463 can be formed. The gate insulating films of the p-channel TFT 462 and the n-channel TFT 463 are formed thinner than the gate insulating films of the p-channel TFT 460 and the n-channel TFT 461, and are driven at a high speed with a low voltage. The former TFT is suitable for forming a latch circuit that is driven at a low voltage of 3 to 5V, and the latter TFT is suitable for forming a shift register circuit that is driven at 5 to 12V.
[0156]
The channel length of these TFTs is 0.3 to 1 μm (preferably 0.6 μm) at the low voltage portion and 0.6 to 1.5 μm (preferably 0.9 μm) at the medium voltage portion. Accordingly, the design rules to be applied are required to have an accuracy of about 0.3 to 1.5 μm for line and space (interval between line width and adjacent line) and about 0.9 μm for contact holes.
[0157]
The TFT manufactured in this embodiment is suitable for forming a stick driver on the source line side. In particular, a latch circuit or the like that is driven at a frequency of several tens of MHz at 3 V is formed using a p-channel TFT 462 and an n-channel TFT 463 shown in FIG. Further, a p-channel TFT 460 and an n-channel TFT 461 are preferably used for a shift register circuit or the like. Here, a process of forming an n-channel TFT and a p-channel TFT is shown, but it is easy to assume that a capacitor element and a resistor element are formed by this process, and are omitted. Further, the size of the TFT (channel length / channel width) necessary for circuit formation and the layout thereof should be considered by the practitioner.
[0158]
[Example 10]
Another example of a method for manufacturing a TFT suitable for a stick driver provided on the source line side will be described. The step of forming the crystalline semiconductor film for forming the active layer of the TFT is the same as that of the third embodiment. In FIG. 22A, a quartz substrate that can withstand heat treatment at 600 ° C. (preferably 950 ° C.) and has an insulating surface is preferable as the substrate 901. The semiconductor film 902 having an amorphous structure formed in close contact with the substrate 401 is formed with a thickness of 40 to 100 nm, for example, 70 nm by a plasma CVD method or a low pressure CVD method. In order to form a high-quality crystalline semiconductor film on a quartz substrate, it is necessary to increase the thickness of the amorphous semiconductor film formed as the start film to some extent. If the film thickness is 30 nm or less, there is a concern that crystallization cannot be sufficiently achieved with the underlying substrate due to lattice mismatch or the like. The semiconductor film having an amorphous structure is the same as the material shown in Embodiment Mode 2 or 3, and typically amorphous silicon is used. Then, a layer 903 containing a catalytic element that can lower the crystallization temperature of the amorphous semiconductor film is formed.
[0159]
For crystallization, dehydrogenation is performed by heat treatment at 450 ° C. for 1 hour, followed by heat treatment at 600 ° C. for 12 hours. As shown in FIG. 22B, a mask insulating film 905 is formed over the crystalline semiconductor film 904 thus obtained, and phosphorus (P) is added from the opening 906 to obtain a phosphorus (P) added region. 907 is formed. The gettering treatment for removing the catalyst element is performed by performing heat treatment in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, and removing the catalyst element remaining in the crystalline semiconductor film 904. The phosphorus (P) addition region 907 is segregated. Thereafter, the mask insulating film 905 and the phosphorus (P) -added region 907 are removed by etching, so that the concentration of the catalytic element is 1 × 10 6. 17 atms / cm Three A crystalline semiconductor film 908 reduced to the following is obtained. Since the amorphous semiconductor film is densified by crystallization, its volume shrinks by about 1 to 10%, and the film thickness slightly decreases.
[0160]
FIG. 22C shows a step of oxidizing the crystalline semiconductor film thus formed by heat treatment. In thermal oxidation, an oxide film is formed in an atmosphere containing halogen (typically chlorine) at 800 to 1000 ° C. (preferably 950 ° C.). By this treatment, the crystalline semiconductor film 908 is thinned by the formation of the oxide film 909 and is reduced from the initial thickness. For example, by forming an oxide film to a thickness of 60 nm, the semiconductor film can be reduced by approximately 30 nm, and a 40 nm crystalline semiconductor film can be left (FIG. 22C).
[0161]
The crystalline semiconductor film 908 thus formed is subjected to an etching process, and then semiconductor films 911 to 914 formed in an island shape are formed. The gate insulating film formed over the semiconductor film is formed with a different thickness even if the TFT is formed over the same substrate in consideration of the driving voltage of the circuit. 22D and 22E show the process. First, an insulating film such as a silicon oxide film or a silicon oxynitride film is formed with a thickness of 20 to 50 nm, for example, 40 nm. These insulating films are formed by a plasma CVD method or a thermal CVD method. An example of manufacturing conditions in the thermal CVD method is SiH Four And N 2 A dense film can be formed by using O, at 800 ° C. and 40 Pa, and with an appropriate gas mixing ratio. After that, the insulating film formed over the semiconductor layers 913 and 914 is removed by etching with hydrofluoric acid or the like to form the first insulating film 915. Further, the surface is washed cleanly, and an oxide film is formed in an atmosphere containing halogen (typically chlorine) at 800 to 1000 ° C. (preferably 950 ° C.). The oxide film is formed to have a thickness of 30 to 50 nm (for example, 40 nm) in the semiconductor layers 913 and 914. On the other hand, in the semiconductor layers 911 and 912, an insulating film having a thickness of 80 nm is formed. By forming an oxide film in a halogen atmosphere, a small amount of metal impurities and the like are removed, and a favorable insulating film in which the interface state density with the semiconductor film is reduced can be formed. Thus, a second insulating film 916 having a different thickness is formed between the semiconductor layers 911 and 912 and the semiconductor layers 913 and 914, and this insulating film is used as a gate insulating film.
[0162]
Note that the gate electrode formed on the gate insulating film has a thin gate insulating film. Of course, it is also possible to use a metal conductive film material formed by sputtering or vapor deposition, but more preferably, the first layer in contact with the gate insulating film is a phosphorus (P) -doped multi-layer formed by low pressure CVD. A crystalline silicon film is desirable. The phosphorus (P) doped polycrystalline silicon film is made of SiH. Four And PH Three And He, H as dilution gas 2 And heated to 450 to 500 ° C. to form a thickness of 100 to 200 nm, preferably 150 nm. Further, a silicide metal or the like is formed on the upper layer in order to reduce the resistance value of the gate electrode. The applicable silicide metal such as tungsten silicide (WSix) or titanium silicide (Ti) is not limited, and is formed to a thickness of 100 to 200 nm, preferably 150 nm, by sputtering or the like.
[0163]
As shown in FIG. 22F, gate electrodes 917 to 920 (first conductive layers 917a to 920a and first conductive layers 917a to 920a) are formed from the state in which the first conductive layer and the second conductive layer are separately formed as described above. Second conductive layers 917b to 920b) are formed.
[0164]
Next, a first doping process for forming an LDD region of the n-channel TFT is performed. As a typical method of doping, phosphine (PH Three The first impurity regions 921 to 924 are formed in a self-aligning manner using the gate electrode as a mask. The phosphorus (P) concentration in this region is 2 × 10 16 ~ 5x10 19 atoms / cm Three (FIG. 23A).
[0165]
Further, a second doping process is performed to form second impurity regions 927 and 928 to which n-type impurities are added. This impurity region forms a source region and a drain region of the n-channel TFT, and a resist mask 926 is formed in order to form it in a region outside the gate electrode. Further, a resist mask 925 is formed so that phosphorus (P) is not added to the semiconductor layer for forming the p-channel TFT. Phosphorus (P) is used for the impurity element imparting n-type, and its concentration is 1 × 10. 20 ~ 1x10 twenty one atoms / cm Three The phosphine (PH Three ) Is performed by an ion doping method using (FIG. 23B).
[0166]
Then, as shown in FIG. 23C, third impurity regions 930 and 931 for forming a source region and a drain region are formed in a semiconductor layer for forming a p-channel TFT. Using the gate electrode 612 as a mask, diborane (B 2 H 6 And the third impurity region is formed in a self-aligning manner. At this time, the entire surface of the semiconductor layer for forming the n-channel TFT is covered with a resist mask 929. The boron (B) concentration in this region is 3 × 10 20 ~ 3x10 twenty one atoms / cm Three To be.
[0167]
After these impurity regions are formed, a first interlayer insulating film 932 made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like is formed, and the temperature is 400 to 950 ° C., preferably 800 to 900 ° C. The impurity element is activated by performing a heat treatment for 5 minutes. By this heat treatment, the impurity element is diffused to the gate electrode side, so that overlap regions 533 to 536 are formed (FIG. 23D). The second interlayer insulating film 937 is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride or an organic insulating material with an average film thickness of 1.0 to 2.0 μm. The wirings 938 to 945 are formed of Al, Ti, or the like. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, and the semiconductor layer is hydrogenated to reduce the density of defect states (FIG. 23E). .
[0168]
As described above, a driver circuit including p-channel TFTs 946 and 948 and n-channel TFTs 947 and 949 can be formed. The gate insulating films of the p-channel TFT 948 and the n-channel TFT 949 are formed thinner than the gate insulating films of the p-channel TFT 946 and the n-channel TFT 947 and are driven at a high speed with a low voltage. The former TFT is suitable for forming a latch circuit that is driven at a low voltage of 3 to 5V, and the latter TFT is suitable for forming a shift register circuit that is driven at 5 to 12V.
[0169]
The p-channel TFTs 946 and 948 have a single drain structure in which channel formation regions 950 and 955 and source or drain regions 946 and 956 each including a third impurity region are formed. In the n-channel TFTs 947 and 949, channel formation regions 952 and 957, LDD regions 953 and 958 formed by the first impurity region, and source or drain regions 954 and 959 formed by the second impurity region are formed. ing. The LDD region formed in the n-channel TFT is formed with a length of 0.2 to 1 μm, and about 0.1 is diffused inside the gate electrode by activation heat treatment and overlaps with the gate electrode. It has become. With this structure, deterioration of characteristics due to the hot carrier effect is prevented, and high speed operation is possible with the parasitic capacitance being minimized.
[0170]
The channel length of these TFTs is 0.3 to 1 μm (preferably 0.6 μm) at the low voltage portion and 0.6 to 1.5 μm (preferably 0.9 μm) at the medium voltage portion. Accordingly, the design rules to be applied are required to have an accuracy of about 0.3 to 1.5 μm for line and space (interval between line width and adjacent line) and about 0.9 μm for contact holes.
[0171]
The TFT manufactured in this embodiment is suitable for forming a stick driver on the source line side. In particular, a latch circuit or the like that is driven at a frequency of several tens of MHz at 3 V is formed using a p-channel TFT 948 and an n-channel TFT 949 shown in FIG. Further, a p-channel TFT 946 and an n-channel TFT 947 are preferably formed for a shift register circuit or the like. Here, a process of forming an n-channel TFT and a p-channel TFT is shown, but it is easy to assume that a capacitor element and a resistor element are formed by this process, and are omitted. Further, the size of the TFT (channel length / channel width) necessary for circuit formation and the layout thereof should be considered by the practitioner.
[0172]
[Example 11]
A driving circuit for the stick driver on the scanning line side or the source line side can be formed by using the TFT manufactured by any one of the methods in Embodiments 8 to 10. Input / output terminals provided in such a stick driver are formed on the same layer as the source or drain wiring as shown in FIG. FIG. 24 shows a state where the input / output terminals 2400 and 2401 are formed at the end of the stick substrate. Since surface passivation is required for mounting on the first substrate on which the pixel region is formed by the face-down COG method, the surface is passivated by the insulating layer 2402. Such an input / output terminal portion can be applied to the stick substrate manufactured in the second to fourth embodiments.
[0173]
Further, in order to mount a stick driver by COG, it is necessary to form bumps on the input / output terminals. The bump may be formed by a known method, and an example thereof will be described with reference to FIG. In FIG. 25A, reference numeral 2403 denotes an input / output terminal formed on the same layer as the source or drain wiring, and a barrier metal layer 2405 in which Ti and Pd or Cr and Cu are stacked is formed thereon. The barrier metal layer is formed by sputtering or vapor deposition. Then, a resist mask 2406 for plating is formed.
[0174]
Then, as shown in FIG. 25B, a bump 2407 made of Au is formed to a thickness of 5 to 20 μm by electrolytic plating. Then, the resist mask 2406 that is no longer needed is removed, a resist is newly applied over the bumps, and a resist mask 2408 for etching the barrier metal layer 2405 is formed. Since the photolithography process for forming this resist mask is performed through bumps, high resolution cannot be obtained. The resist mask 2408 is formed so as to cover the bump and its periphery. By etching the barrier metal layer using this resist mask 2408, a barrier metal layer 2409 as shown in FIG. 25D is formed. Thereafter, heat treatment is performed at 200 to 300 ° C. in order to improve the adhesion between the bump and the barrier metal layer. In this manner, a stick driver that can be mounted on another substrate can be completed.
[0175]
[Example 12]
As described above, the stick driver can be used as a method for mounting a driving circuit of a liquid crystal display device. FIG. 26 shows a block diagram of such a display device. The pixel region 1601 has an active matrix structure in which a plurality of scanning lines and source lines are formed to intersect with each other and an inverted staggered TFT as shown in Embodiments 1 to 7 is provided. A scanning line stick driver 1602 and a source line stick driver 1603 are provided in the peripheral area. The clock signal and data signal 1607 and the image quality signal 1608 input from the outside are input to the control circuit 1605 for conversion to the input specifications of the stick driver, and are converted into respective timing specifications. A power source 1609 and a power source circuit 1606 including an operational amplifier are covered by an external circuit. When the control circuit 1605 and the power supply circuit 1606 are mounted by the TAB method, the display device can be downsized.
[0176]
Signals are output from the control circuit 1605 to the scanning line side and the source line side, respectively, but a signal dividing circuit 1604 is provided on the source line side, and an input digital signal is divided into m pieces and supplied. The division number m is a natural number of 2 or more. In this case, if the number of input digital signal lines 1610 is n, the number of modified digital signal lines 1620 is n × m. Although depending on the pixel density, at least a plurality of stick drivers on the source line side are provided, and the load of the stick driver is reduced by reducing the frequency of the input digital signal to 1 / m by the signal dividing circuit. The signal dividing circuit may be mounted with an IC chip formed with a semiconductor integrated circuit, or may be formed with a chip similar to a stick driver in which an integrated circuit is formed with TFTs as shown in the third or fourth embodiment. is there.
[0177]
[Example 13]
FIG. 27 shows an example of a signal dividing circuit. In this embodiment, for convenience, the number n of input digital signal lines is 1 and the number m of signal divisions is 4. The latch circuit front stages 1301 to 1304 and the latch rear stages 1305 to 1308 are respectively configured by two inverters 1372 and 1374 and four clocked inverters 1371, 1373, 1375, and 1376 as shown in FIG. The signal input unit 1381 corresponds to 1361, the signal output unit 1382 corresponds to 1362, and the clock signal input units 1383 and 1384 correspond to 1363 and 1364, respectively.
[0178]
Clock signals of the clock signal line 1322 and the inverted clock signal line 1323 are input to the counter circuit 1309, and an input from the reset signal 1326 is received and an output is sent to the corrected clock signal line 1324 and the inverted corrected clock signal line 1325. The input digital signal is input from 1321 and sequentially transferred from the latch circuit pre-stages 1301 to 1302 for each cycle of the clock signal. Then, when the corrected clock signal is inverted, the potential information of the input digital signal held in the previous stage of the latch circuit is moved to the subsequent stage of the latch circuit. For example, the potential information of the latch circuit front stage 1301 is transferred to the latch circuit rear stage 1305. By such an operation, a corrected digital signal is transmitted from each of the corrected digital signal lines 1331 to 1334 connected to the output units of the latch circuit subsequent stages 1305 to 1308. Here, since the division number m = 4, the frequency of the modified digital signal is ¼ of the frequency of the input digital signal. Of course, the number of divisions is not limited to four, and can be freely selected in the range of 2 to 32 (practically 4 to 16).
[0179]
[Example 14]
FIG. 28 shows an example of the circuit configuration of the stick driver provided on the source line side shown in FIG. As for the circuit configuration, a shift register circuit 1801, latch circuits 1804 and 1805, a level shifter circuit 1806, and a D / A conversion circuit 1807 are provided from the input side. When an input digital signal expresses information of one pixel with n bits and performs RGB display, if this input digital signal is divided into m, m × 3 × n latch circuits 1804 and 1805 are required, M × 3 level shifters 1806 and D / A conversion circuits 1807 are required.
[0180]
FIG. 21 shows a typical example of a latch circuit, FIG. 29A shows an example using a clocked inverter, FIG. 29B shows an SRAM type, and FIG. 29C shows a DRAM type. It is. These are representative examples, and other configurations are possible.
[0181]
The shift register circuit and the latch circuit have a driving voltage of 3 V, and are boosted to 10 V by the level shifter circuit and send a signal to the D / A conversion circuit. As the D / A conversion circuit, a resistance division type or a switched capacitor type can be adopted.
[0182]
The TFTs forming the shift register circuit and the latch circuit are the p-channel TFT 462 and the n-channel TFT 463 shown in FIG. 21G in Embodiment 3 or the p-channel TFT 548 shown in FIG. 23E in Embodiment 4. And an n-channel TFT 549 is preferably used.
[0183]
[Example 15]
FIG. 30 is a diagram schematically showing how the liquid crystal display device is assembled using the stick driver of the present invention. A pixel region 803, an external input / output terminal 804, and a connection wiring 805 are formed on the first substrate. The pixel region 803 is formed using the inverted staggered TFT described in Embodiment 1. A region surrounded by a dotted line is a stick driver bonding region 801 on the scanning line side and a stick driver bonding region 802 on the source line side. A counter electrode 809 is formed over the second substrate 808 and is bonded to the first substrate 800 with a sealant 810. Liquid crystal is sealed inside the sealant 810 to form a liquid crystal layer 811. The first substrate and the second substrate are bonded to each other with a predetermined interval. The nematic liquid crystal has a thickness of 3 to 8 μm, and the smectic liquid crystal has a thickness of 1 to 4 μm.
[0184]
As described in the second embodiment, the stick drivers 806 and 807 have different circuit configurations on the source line side and the scanning line side. The third substrate 814 is not particularly distinguished, but in any case, it is assumed that the third substrate 814 is a stick driver adapted to the driving circuit on the scanning line side or the source line side. The stick driver is mounted on the first substrate, and the method is described in Embodiment 1 with reference to FIGS. As the stick driver mounted on the scanning line side, the one shown in Embodiment 8 is suitable, and a drive circuit is formed on a glass substrate. The stick driver mounted on the data line side is required to have a TFT characteristic that can cope with a high signal frequency even if divided driving is assumed. Therefore, the stick driver formed on the quartz substrate shown in Example 9 or 10 is suitable. ing. An FPC (Flexible Printed Circuit) 812 for inputting power and control signals from the outside is attached to the external input / output terminal 804. In order to increase the adhesive strength of the FPC 812, a reinforcing plate 813 may be provided. Thus, a liquid crystal display device can be completed. If the stick driver is subjected to electrical inspection before being mounted on the first substrate, the yield in the final process of the liquid crystal display device can be improved and the reliability can be improved.
[0185]
[Example 16]
FIG. 31 shows an example of a method for mounting a display device mounted with a stick driver on an electro-optical device as shown in the fifteenth embodiment. In the display device, a stick driver 710 is mounted on an end portion of a substrate 701 on which a pixel region 702 is mounted. Then, it is bonded to the counter substrate 703 by a sealing agent 707 including a spacer 706, and polarizing plates 708 and 709 are further provided. Then, it is fixed to the housing 724 by the connecting member 723.
[0186]
The stick driver 710 is connected to an input wiring 714 formed on the substrate 701 with a resin 713 containing conductive particles 712 at the input / output terminal 711. One end of the input / output wiring 714 is bonded with a resin 716 including conductive particles 715 on a flexible printed circuit (FPC). The FPC is connected to a printed circuit board 719 provided with a signal processing circuit, an amplifier circuit, a power supply circuit, and the like in the same manner (resin 722 including conductive particles 721), and a stick driver mounts signals necessary for image display. Is transmitted to the display device. If the display device is a transmissive liquid crystal display device, a light source and a light guide are provided on the counter substrate 703 side, and a backlight 718 is provided.
[0187]
The mounting method of the display device shown here is an example, and the display device is appropriately assembled according to the form of the electro-optical device.
[0188]
[Example 17]
From the viewpoint of the productivity of the stick driver, a method of taking out as many as possible from one substrate in one process using a large area substrate is suitable. A glass substrate or a quartz substrate is used as a substrate, but in any case, when a large-area substrate is divided, how to eliminate processing loss becomes a first problem. In terms of processing accuracy, a dicing apparatus is suitable. However, in order to directly process a substrate used in a liquid crystal line such as 300 × 400 mm, 550 × 650 mm, or 960 × 1000 mm, the scale of the apparatus increases. Rather, it uses a glass scriber that can easily cut a large-area substrate although it is inferior in processing accuracy, thereby dividing the large-area substrate into a plurality of steps, and using a dicing apparatus from the divided substrate. It is more suitable to carry out by dividing into the second stage of dividing into individual stick drivers.
[0189]
For example, a plurality of groups 902 each having a side of 100 to 200 mm are formed on a 300 × 400 mm large-area substrate used in the first liquid crystal line, and a stick having a short side length of 1 to 6 mm is formed therein. Arrange multiple drivers. The distance between each group is 3 to 10 mm, and the glass scriber is used to divide the large area substrate along the processing line 904. The stick drivers in the group can be arranged with a cutting margin of 0.5 to 1 mm and divided by a dicing device. By using such a processing method, 360 2 × 20 mm stick drivers can be formed in a 127 × 127 mm group, and 2160 stick drivers can be taken out from one substrate.
[0190]
A second problem for forming a large number of stick drivers on a large-area substrate is an exposure technique. The design rule of the stick driver is 0.3 to 2 μm, preferably 0.35 to 1 μm. With such a design rule, it is necessary to perform exposure with high throughput. In the exposure method, the proximity method and the projection method are advantageous for improving the throughput, but a large-sized high-definition mask is required, and there is a drawback that it is difficult to obtain high resolution and overlay accuracy. On the other hand, in the stepper method, for example, a 44 mm square region or a 54 × 30 mm region can be exposed at a time with a resolution of 0.7 μm using i-line (365 nm). Correspondingly, if the length of the long side of the stick driver is set within this exposure range, even a submicron pattern can be exposed efficiently.
[0191]
A pixel region of a liquid crystal display device or the like does not necessarily require a sub-micron design rule, so a proximity method or a projection method that can expose a large area at a time is considered a suitable method. Therefore, performing the driving circuit portion and the pixel region by different exposure methods not only improves productivity, but also by mounting a stick driver as in the present invention, the peripheral portion (frame region) of a large-screen display device. ) Can be reduced.
[0192]
[Example 18]
In this embodiment, a semiconductor device incorporating a display device having the structure as in Embodiment 8 will be described. Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS.
[0193]
FIG. 33A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. As the display device 9004, a liquid crystal display device in which a stick driver is mounted around a pixel region using the inverted staggered TFT of the present invention can be used.
[0194]
FIG. 33B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. As the display device 9102, a liquid crystal display device in which a stick driver is mounted around a pixel region using an inverted staggered TFT of the present invention can be used.
[0195]
FIG. 33C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. As the display device 9205, a liquid crystal display device in which a stick driver is mounted around a pixel region using an inverted staggered TFT of the present invention can be used.
[0196]
FIG. 33D illustrates a television set including a main body 9401, a speaker 9402, a display device 9403, a receiving device 9404, an amplifying device 9405, and the like. As the display device 9403, a liquid crystal display device in which a stick driver is mounted around a pixel region using the inverted staggered TFT of the present invention can be used.
[0197]
FIG. 33E illustrates a portable book, which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506. Data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. As the direct-view display devices 9502 and 9503, a liquid crystal display device in which a stick driver is mounted around the pixel region using the inverted staggered TFT of the present invention can be used.
[0198]
FIG. 34A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display device 9603, and a keyboard 9604. As the display device 9603, a liquid crystal display device in which a stick driver is mounted around a pixel region using the inverted staggered TFT of the present invention can be used.
[0199]
FIG. 34B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, a speaker portion 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. As the display device 9702, a liquid crystal display device in which a stick driver is mounted around a pixel region using the inverted staggered TFT of the present invention can be used.
[0200]
FIG. 34C illustrates a digital camera, which includes a main body 9801, a display device 9802, an eyepiece unit 9803, an operation switch 9804, and an image receiving unit (not shown). As the display device 9802, a liquid crystal display device in which a stick driver is mounted around a pixel region using the inverted staggered TFT of the present invention can be used.
[0201]
【The invention's effect】
As described above, according to the present invention, a pixel TFT having an inverted staggered n-channel TFT and a pixel region of a liquid crystal display device including a storage capacitor can be formed using three photomasks. As a result, the manufacturing process can be simplified. Similarly, a reflective liquid crystal display device in which the surface of the pixel electrode is uneven by using three photomasks can be manufactured.
[0202]
In addition, when mounting a stick driver on a liquid crystal display device having an inverted staggered pixel TFT and a storage capacitor manufactured by three photomasks, the drive circuit is configured with a stick driver longer than a conventional IC chip. By mounting, the number required for one pixel region can be reduced. As a result, it is possible to improve the manufacturing yield of the liquid crystal display device and reduce the manufacturing cost.
[0203]
On the other hand, the advantage of the stick driver from the viewpoint of the manufacturing process is that the pixel area that does not necessarily require submicron design rules is designed using a proximity method or projection method that can expose a large area at a time. A stick driver requiring a rule can be divided into production means such as exposing by a stepper method. Productivity can be increased by using such means.
[0204]
[Brief description of the drawings]
FIG. 1 is a top view illustrating a pixel structure of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a terminal portion.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a terminal portion.
FIG. 4 is a top view illustrating a manufacturing process of a pixel TFT and a storage capacitor.
FIG. 5 is a top view illustrating a manufacturing process of a pixel TFT and a storage capacitor.
FIG. 6 is a diagram illustrating the arrangement of a pixel area and a stick driver.
FIG. 7 is a block diagram illustrating a circuit configuration of a pixel area and a stick driver.
FIG. 8 is a cross-sectional view illustrating a configuration of a stick driver.
FIG. 9 is a diagram for explaining an example of a stick driver mounting method;
FIG. 10 illustrates an example of a stick driver mounting method.
FIG. 11 is a top view and a cross-sectional view of an input terminal portion.
FIG. 12 is a cross-sectional view illustrating the structure of a pixel TFT, a storage capacitor, and a terminal portion.
FIG. 13 illustrates a configuration of a multi-chamber manufacturing apparatus.
FIG. 14 is a diagram illustrating a configuration of a single chamber continuous film formation manufacturing apparatus.
FIG. 15 is a cross-sectional structure diagram of a reflective liquid crystal display device.
FIG. 16 is a top view of a pixel of a reflective liquid crystal display device.
FIG. 17 illustrates a manufacturing process of a TFT that forms a driver circuit of a stick driver.
18A and 18B illustrate a manufacturing process of a TFT that forms a driver circuit of a stick driver.
19A and 19B illustrate a manufacturing process of a TFT that forms a driver circuit of a stick driver.
20A and 20B illustrate a manufacturing process of a TFT that forms a driver circuit of a stick driver.
FIG. 21 illustrates a manufacturing process of a TFT that forms a driver circuit of a stick driver.
22A and 22B illustrate a manufacturing process of a TFT that forms a driver circuit of a stick driver.
FIG. 23 illustrates a manufacturing process of a TFT that forms a driver circuit of a stick driver.
FIG. 24 is a cross-sectional view illustrating a configuration of a terminal portion of the stick driver.
FIG. 25 is a manufacturing process diagram of bumps formed on the input / output terminal portion of the stick driver.
FIG 26 is a block diagram illustrating a circuit structure of a display device.
FIG 27 illustrates a structure of a signal dividing circuit.
FIG. 28 is a diagram illustrating a configuration of a drive circuit of a stick driver connected to a source line.
FIG 29 illustrates a specific example of a latch circuit.
FIG. 30 is an assembly diagram of a liquid crystal display device on which a stick driver is mounted.
FIG. 31 is a diagram illustrating an example in which a display device is mounted on a housing of an electro-optical device.
FIG. 32 is a conceptual diagram of an active matrix display device on which a stick driver is mounted.
FIG. 33 illustrates an example of a semiconductor device.
FIG. 34 illustrates an example of a semiconductor device.

Claims (9)

  1. A plurality of scanning lines and a plurality of source lines are provided so as to intersect with each other through an insulating layer, and a first region having a pixel region in which inverted staggered thin film transistors having an amorphous semiconductor are provided in a matrix at the intersections. A substrate of
    A second substrate provided with a counter electrode facing the pixel region;
    A scanning line side stick driver and a source line side stick driver provided outside the pixel region;
    In the semiconductor device in which a liquid crystal layer is sandwiched between the first substrate and the second substrate,
    Wherein each of the plurality of scanning lines is electrically connected to any one of the plurality of first wirings, the plurality of first wirings were collected in accordance with the pitch of output terminals of the scanning line side stick drivers Provided in the state,
    Wherein each of the plurality of source lines are electrically connected to any one of the plurality of second wirings, the plurality of second wirings were collected in accordance with the pitch of output terminals of the source line side stick drivers Provided in the state,
    The source line side stick driver is provided more than the scanning line side stick driver, and the design rule is reduced compared to the scanning line side stick driver,
    The scanning line side stick driver has a buffer circuit including a first thin film transistor and a first shift register circuit including a second thin film transistor,
    The gate insulating film of the first thin film transistor is thicker than the gate insulating film of the second thin film transistor,
    The source line side stick driver has a second shift register circuit including a third thin film transistor and a latch circuit including a fourth thin film transistor,
    The semiconductor device according to claim 3, wherein a gate insulating film of the third thin film transistor is thicker than a gate insulating film of the fourth thin film transistor.
  2. In claim 1 ,
    The gate insulating film of the first thin film transistor comprises a stack of a first insulating film and a second insulating film,
    The gate insulating film of the second thin film transistor is composed of the second insulating film,
    The gate insulating film of the third thin film transistor comprises a stack of a third insulating film and a fourth insulating film,
    The gate insulating film of the fourth thin film transistor is composed of the fourth insulating film.
  3. In claim 1 or claim 2 ,
    A semiconductor device comprising means for reducing the frequency of a data signal input to the source line side stick driver.
  4. In any one of Claim 1 thru | or 3 ,
    The scanning line side stick driver is electrically connected to the first wiring via conductive particles,
    The first wiring includes a first conductive film made of the same material as the gate electrode of the pixel region, and a second conductive made of the same material as the pixel electrode of the pixel region provided on the first conductive film. Having a membrane,
    The semiconductor device, wherein the conductive film is in contact with the second conductive film.
  5. In any one of Claim 1 thru | or 3 ,
    The source line side stick driver is electrically connected to the second wiring via conductive particles,
    The second wiring includes a first conductive film made of the same material as the gate electrode of the pixel region, and a second conductive made of the same material as the pixel electrode of the pixel region provided on the first conductive film. Having a membrane,
    The semiconductor device, wherein the conductive film is in contact with the second conductive film.
  6. In any one of Claim 1 thru | or 3 ,
    The scanning line side stick driver is electrically connected to the first wiring via first conductive particles,
    The source line side stick driver is electrically connected to the second wiring via second conductive particles,
    The first wiring includes a first conductive film made of the same material as the gate electrode of the pixel region, and a second conductive made of the same material as the pixel electrode of the pixel region provided on the first conductive film. Having a membrane,
    The second wiring includes a third conductive film made of the same material as the gate electrode of the pixel region, and a fourth conductive made of the same material as the pixel electrode of the pixel region provided on the third conductive film. Having a membrane,
    The second conductive film is in contact with the first conductive particles,
    The semiconductor device, wherein the second conductive particles are in contact with the fourth conductive film.
  7. In any one of Claims 1 thru | or 6 ,
    The scanning line side stick driver and the source line side stick driver each have a crystalline semiconductor layer.
  8. In any one of Claims 1 thru | or 6 ,
    The scanning line side stick driver and the source line side stick driver each include a single crystal semiconductor layer.
  9. In any one of Claims 1 thru | or 8 ,
    The semiconductor device is one selected from a mobile phone, a video camera, a mobile computer, a portable book, a digital camera, a personal computer, a DVD player, and a television.
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US09/566,723 US6709901B1 (en) 2000-03-13 2000-05-09 Semiconductor device having stick drivers and a method of manufacturing the same
TW90105033A TW480731B (en) 2000-03-13 2001-03-05 Semiconductor device and a method of manufacturing the same
KR1020010012853A KR100828441B1 (en) 2000-03-13 2001-03-13 Semiconductor device and a method of manufacturing the same
US10/388,656 US6806499B2 (en) 2000-03-13 2003-03-17 Semiconductor device and a method of manufacturing the same
US10/932,113 US7995183B2 (en) 2000-03-13 2004-09-02 Semiconductor device and a method of manufacturing the same
US13/205,029 US8300201B2 (en) 2000-03-13 2011-08-08 Semiconductor device and a method of manufacturing the same
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