CN112259453A - Method for slotting surface of chip and chip - Google Patents
Method for slotting surface of chip and chip Download PDFInfo
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- CN112259453A CN112259453A CN202011140415.0A CN202011140415A CN112259453A CN 112259453 A CN112259453 A CN 112259453A CN 202011140415 A CN202011140415 A CN 202011140415A CN 112259453 A CN112259453 A CN 112259453A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 32
- 230000001681 protective effect Effects 0.000 claims description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000002360 preparation method Methods 0.000 abstract description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000011049 filling Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QVRVXSZKCXFBTE-UHFFFAOYSA-N n-[4-(6,7-dimethoxy-3,4-dihydro-1h-isoquinolin-2-yl)butyl]-2-(2-fluoroethoxy)-5-methylbenzamide Chemical compound C1C=2C=C(OC)C(OC)=CC=2CCN1CCCCNC(=O)C1=CC(C)=CC=C1OCCF QVRVXSZKCXFBTE-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
The invention discloses a method for slotting the surface of a chip and the chip, which increases the number of grooves by utilizing the self-aligning preparation characteristic of an isolation layer, further increases the surface area in the grooves by etching undercut characteristic, and finally realizes the purpose of maximally increasing the total groove number and the total effective area of a transistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for grooving the surface of a chip and the chip.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the development of ICs, the functional density, i.e., the number of interconnected devices per chip area, is generally increased, while the geometry, i.e., the smallest device or interconnect line that is fabricated by the fabrication process, is reduced. That is, improvements in IC performance are achieved primarily by the ever shrinking size of integrated circuit devices to increase their speed. At present, in the production and manufacture of metal-oxide semiconductor field effect transistors (MOS-FETs) and Insulated Gate Bipolar Transistors (IGBTs), the trench slotting process is carried out on the transistors, so that the current passing and high-voltage and high-current bearing capacity are improved.
At present, in the groove process of MOS-FET and IGBT transistors, when the surface area and the thickness of a transistor tube chip are constant, the number of grooves which can be etched on the surface is limited, namely the effective contact area of the wall of a single groove formed on the surface of the whole monocrystalline silicon is limited, so that the static current passing and the high-voltage bearing capacity of the single groove are limited, and the integral performance of the transistor is restricted.
Disclosure of Invention
The invention provides a method for grooving the surface of a chip and the chip, which aim to solve the problem that the number of grooves generated in the unit area of the chip is small in the prior art.
In a first aspect, the present invention provides a method for grooving a chip surface, the method comprising: the method comprises the steps that a plurality of mask structures are arranged at preset positions on the surface of a chip, a groove is formed between every two mask structures and comprises a first groove and a second groove, the first groove and the second groove are sequentially and alternately arranged, and the width between the mask structures is the exposure limit of exposure equipment.
Optionally, the first trench width is greater than the second trench width, and the first trench width is an exposure limit of an exposure apparatus, and the width of the second trench plus the interval between the second trench and the first trench is equal to the exposure limit.
Optionally, the first trench width is equal to the second trench width, and the first trench width, the second trench width, plus the spacing between the second trench and the first trench is equal to two of the exposure limits.
Optionally, the setting of a plurality of mask structures at a preset position on the surface of the chip includes:
and arranging side walls on the surface of the chip corresponding to the first groove, and arranging the mask structures on two sides of the side walls.
Optionally, disposing the mask structure on two sides of the sidewall includes:
carrying out oxidation treatment on the surface of the chip to generate a first protective film with a first preset thickness;
etching the first protective film, and reserving the first protective film with the preset width on two sides of the side wall;
and depositing a second protective film with a second preset thickness on the surface of the chip, etching the second protective film, and reserving the second protective film on the first protective film to obtain the mask structure.
Optionally, the first protective film is a silicon oxide protective film; the second protective film is a silicon nitride protective film.
Optionally, the etching the first protection film to retain the first protection film with a predetermined width on both sides of the sidewall includes: depositing a developer on the first protective film, defining a pattern by development, and etching the first protective film by a yellow light process, leaving a predetermined width of the first protective film on both sides of the sidewall.
Optionally, after the plurality of mask structures are disposed at the predetermined position on the chip surface, before a trench is disposed between every two mask structures, the method further includes: and carrying out isotropic etching on the positions of two side walls of the first groove or one side wall of the first groove and the positions of two side walls of the second groove or one side wall of the second groove according to the preset voltage bearing capacity to form an undercut structure.
Optionally, after one trench is disposed between every two mask structures, the method further includes:
and etching the chip substrate part after the undercut treatment and the chip substrate at the side wall position by using the mask structure to obtain the first groove and the second groove with preset depths, and removing the mask structure.
In a second aspect, the present invention provides a chip, wherein the chip is prepared by using any one of the above methods for grooving the surface of the chip.
The invention has the following beneficial effects:
according to the invention, the mask structure is set as the isolation layer between the grooves, the grooves are etched by utilizing the self-alignment characteristic of the mask structure, and the dimension between the mask structures is set as the exposure limit of the exposure equipment, so that the maximization of the number of the grooves in the unit area of the chip is realized, the problem of less number of the grooves generated in the unit area of the existing chip is effectively solved, and the current passing capacity and the high-voltage bearing capacity of the chip are effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a chip surface grooving method according to a first embodiment of the present invention;
FIG. 2 is a schematic illustration of a first embodiment of the present invention providing a slot in comparison to a prior art slot;
FIG. 3 is a schematic view of a sidewall provided in accordance with a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a mask structure provided in a first embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a chip with silicon oxide formed on the surface thereof according to a first embodiment of the present invention;
FIG. 6 is a schematic structural diagram after etching silicon oxide by development according to the first embodiment of the present invention;
FIG. 7 is a schematic diagram of a SiN covered structure according to a first embodiment of the present invention;
FIG. 8 is a schematic structural view of an undercut provided by the first embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a mask structure according to a first embodiment of the present invention;
fig. 10 is a schematic view of the overall structure of a trench according to a first embodiment of the present invention;
the attached drawings are as follows: 1 first trench, 2 second trench, 3 mask structure, 4 existing trench, 5 first protection film, 6 sidewalls, 7 chip.
Detailed Description
Aiming at the problem that the number of grooves generated by the existing chip per unit area is small, the embodiment of the invention maximizes the number of grooves per unit area by setting the mask structures and enabling the width between the mask structures to be the exposure limit of exposure equipment, thereby improving the current passing capacity and the high-voltage bearing capacity of the chip. The present invention will be described in further detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
A first embodiment of the present invention provides a method for grooving a chip surface, as shown in fig. 1, the method including: the method comprises the steps that a plurality of mask structures 3 are arranged at preset positions on the surface of a chip 7, a groove is formed between every two mask structures, the groove comprises a first groove 1 and a second groove 2, the first groove 1 and the second groove 2 are sequentially and alternately arranged, and the width between the mask structures 3 is the exposure limit of exposure equipment.
That is, in the embodiment of the present invention, the mask structure 3 is set as an isolation layer between trenches, the trenches are etched by using the self-alignment characteristic of the mask structure 3, and the dimension between the mask structures 3 is set as the exposure limit of the exposure device (i.e., the maximum width value that the exposure device can expose), so that the maximization of the number of trenches per unit area of a chip is achieved, and further, the problem of the existing chip that the number of trenches generated per unit area is small is effectively solved, and the current passing capability and the high voltage carrying capability of the chip are effectively improved.
In specific implementation, the width of the first trench 1 is larger than the width of the second trench 2, the width of the first trench 1 is the exposure limit of the exposure apparatus, and the width of the second trench 2 plus the interval between the second trench 2 and the first trench 1 is equal to the exposure limit. Alternatively, by setting the width of the first trench 1 to be equal to the width of the second trench 2, the width of the first trench 1, the width of the second trench 2, and the interval between the second trench 2 and the first trench 1 are equal to two exposure limits.
That is, in the embodiment of the present invention, the width of the first trench 1 is the exposure limit of the exposure apparatus, and the width of the second trench 2 plus the interval between the second trench 2 and the first trench 1 is equal to the width of the first trench 1. Alternatively, the width of the first trench 1 may be set to be slightly smaller than the exposure limit, and the width of the second trench 2 may be enlarged, that is, in a specific implementation, the specific widths of the first trench 1 and the second trench 2 may be adjusted according to actual needs, as long as it is ensured that trenches are arranged within each exposure limit and an effective interval between trenches is ensured, which is not specifically limited in the embodiment of the present invention.
In other words, the widths of the first trench 1 and the second trench 2 in the embodiment of the present invention need to be set according to the exposure limit of the exposure apparatus, and the sizes of the first trench 1 and the second trench 2 may be adjusted according to specific situations.
It should be noted that, since the trenches in the embodiment of the present invention are exposed and etched according to the exposure limit of the exposure apparatus, the trenches in the embodiment of the present invention achieve the theoretical maximum trench density in a strict sense.
Generally speaking, the embodiment of the invention maximizes the number of trenches per unit area by setting the mask structures 3 and setting the width between the mask structures 3 as the exposure limit of the exposure equipment, and by setting the first exposure limit corresponding to a first trench 1 that is relatively wide and the second exposure limit corresponding to a second trench 2 that is slightly narrow, i.e. the second exposure limit corresponding to a second trench 2 and the interval between two trenches, thereby improving the current passing capability and the high voltage carrying capability of the chip 7.
It can also be understood that, in order to obtain a larger effective area of the trench of the transistor in the same package volume, the embodiment of the present invention utilizes the self-aligned characteristic of the mask structure 3, i.e., the isolation layer (Spacer), to increase the number of trenches and the effective area of the transistor, thereby increasing the current carrying capacity and the high voltage capacity of the transistor by several times.
As shown in fig. 2, the upper trench in the figure is the existing trench 4 formed on the chip 7 by the existing method, and the lower trench is the trench prepared by the method of the present invention.
Further, in the embodiment of the present invention, a plurality of mask structures are disposed at predetermined positions on the surface of the chip 7, specifically, a plurality of mask structures 3 are disposed at predetermined positions on the surface of the chip 7 according to a predetermined arrangement rule.
Since the embodiment of the present invention utilizes the self-aligned characteristics of the mask structure 3 to set the trenches, i.e., the mask structure 3 isolates each trench, thereby realizing the maximum quantization of the trenches, in the specific implementation, the embodiment of the present invention presets the positions of the trenches on the surface of the chip 7, and configures the mask structure 3 according to a certain interval rule, and the specific interval rule can be determined according to the specific power-on capability of the chip 7, the exposure limit of the exposure device, and the production conditions of other devices.
In specific implementation, in the embodiment of the present invention, the setting of the plurality of mask structures 3 at the preset position on the surface of the chip 7 according to the preset setting rule includes: a side wall 6 is arranged on the surface of the chip 7 corresponding to the position of the first trench 1, the mask structures 3 are arranged on two sides of the side wall 6, and the second trench 2 is arranged on the surface of the chip 7 between the two side walls 6, wherein the side wall 6 of the embodiment of the invention is specifically shown in fig. 3.
Specifically, in the embodiment of the present invention, the mask structure 3 is prepared by using the sidewall 6, and specifically, the mask structure 3 is disposed on two sides of the sidewall 6, including: performing an oxidation process on the surface of the chip 7 to generate a first protection film 5 with a first predetermined thickness, specifically, as shown in fig. 3, removing the first protection film 5 on the surface of the chip 7, and leaving the first protection film 5 with a predetermined width on both sides of the sidewall 6; and integrally depositing a second protective film with a second preset thickness on the surface of the chip 7, etching the second protective film on the surface of the chip 7, and reserving the second protective film on the first protective film 5 to obtain the mask structure 3, which is specifically shown in fig. 4.
That is, the embodiment of the present invention is to form the mask structure 3 on both sides of the sidewall 6, and the mask structure 3 is formed by two protective films. Although the first protective film 5 is a silicon oxide protective film and the second protective film is a silicon nitride protective film, in the specific implementation, a person skilled in the art may also set the mask structure 3 of the present invention in other ways according to actual needs, which is not limited in this respect.
It should be noted that, in the embodiment of the present invention, the first predetermined thickness is
The predetermined width is
The second preset thickness is
Of course, the above numerical range is only an example, and in the implementation, the skilled person can set the range arbitrarily according to the actual needs, and the present invention is not limited to this.
In addition, after the mask structure 3 is obtained, the sidewall 6 needs to be removed for the next trench etching operation.
In specific implementation, in the embodiment of the present invention, the removing the first protection film 5 on the surface of the chip 7 and retaining the first protection film 5 with a predetermined width on both sides of the sidewall 6 includes: the ethyl silicate oxide is deposited on the first protective film 5, and a pattern is defined by development, and the first protective film 5 is etched by a yellow light process, leaving only the first protective film 5 of a predetermined width on both sides of the sidewall 6.
Specifically, the embodiment of the present invention defines the pattern by developing, and etches the first protective film 5 by the yellow light process, the etching is stopped at the position of the first protective film 5, and only the first protective film 5 with the predetermined width at both sides of the sidewall 6 is remained.
In general, the final mask structure 3 is prepared by using a silicon oxide film and a silicon nitride film in the embodiment of the present invention.
Further, in the embodiment of the present invention, after the plurality of mask structures 3 are disposed at the predetermined positions on the surface of the chip 7, before a trench is disposed between every two mask structures 3, the method further includes: and carrying out isotropic etching on one or two of two side walls of the first groove 1, two side walls of the second groove 2, one side wall of the first groove 1 and one side wall of the second groove 2 according to a preset voltage bearing capacity to form an undercut structure.
That is, in the embodiments of the present invention, the undercut process may be performed on two sidewalls of one trench, all sidewalls of two trenches, or one sidewall of one trench, so as to obtain an undercut structure, and further increase the surface area of the trench through the undercut structure.
It should be noted that, in the embodiment of the present invention, the width of the first trench 1 is set to be x, and the interval between the first trench 1 and the second trench 2 is y, so that the width of the second trench 2 is x-2 y.
In addition, the radius of the undercut structure etching is z, and in order to avoid the etching communication between the first trench 1 and the second trench 2, in the embodiment of the invention, y is set to be larger than 2 z.
After a trench is arranged between every two mask structures 3, the embodiment of the invention further comprises: and etching the substrate part of the chip 7 subjected to the undercut treatment and the substrate of the chip 7 at the position of the side wall 6 by using the mask to obtain the first groove 1 and the second groove 2 with preset depths, and removing the mask structure 3. And then carrying out subsequent treatment on the obtained groove, and finally obtaining the finally needed transistor.
Specifically, the embodiment of the invention specifically comprises the steps of obtaining an undercut structure through isotropic etching, obtaining a corresponding groove through anisotropic etching, placing the chip 7 in an oxidation furnace tube for oxidation operation after the groove is obtained through preparation, and generating the thickness of the undercut inner side wall and the groove
Depositing adulterant by low-pressure chemical vapor deposition LPCVD, filling the groove, chemically and mechanically polishing Poly CMP by polysilicon or etching Poly Etch by polysilicon, removing Poly outside the groove completely, growing silicon Oxide SAC Oxide by CVD, removing SAC Oxide to purify the surface of the wafer, developing photoresist PR on the yellow light process to define the pattern, and treating in a thermal oxidation furnace tube to obtain the gateAnd (3) forming a Gate Oxide, developing and defining patterns through PR (pattern matching) on a yellow light process, finishing a Gate structure through polysilicon, finishing the process and the structure for increasing the effective area of the groove of the MOSFET, and finally obtaining the final transistor.
The method for grooving the surface of the chip according to the embodiment of the present invention will be explained and explained in detail with reference to fig. 5 to 10:
in the embodiment of the present invention, before performing various processes, the surface of the chip needs to be cleaned to remove impurities on the surface of the chip, and after the cleaning is completed, the following processes are sequentially performed on the chip:
s101, placing the chip in a furnace tube, and generating a layer of silicon Oxide (Thermal Oxide SiO) on the chip through heat treatment2) The structure of the processed chip is shown in fig. 5, that is, a layer of silicon oxide is generated on the whole surface of the chip;
s102, depositing and generating oxidized tetraethoxysilane TEOS Oxide on silicon Oxide through a vapor deposition method CVD;
s103, developing and defining a pattern on the oxidized tetraethoxysilane through PR (photo-lithography), etching TEOS (tetraethyl orthosilicate) to form a side wall Dummy, and stopping etching on the thin silicon oxide film, wherein the specific process is shown in figure 6;
s104, depositing silicon nitride by CVD, namely, covering with SiN, specifically, as shown in FIG. 7, coating SiN on original silicon oxide remained after etching and an original chip;
s105, generating a SiN Spacer structure by anisotropic dry etching of SiN, wherein the etching is stopped at SiO2；
S106, dry etching a Silicon wafer Silicon through isotropic etching to form an undercut structure, specifically a semicircular structure shown in FIG. 8, namely the undercut structure;
s107, removing the TEOS on the side wall between the masks through wet etching, namely removing Dummy wafers between the masks, and forming a mask structure with the self-alignment preparation characteristic of the SiN isolation layer after etching, as shown in FIG. 9 specifically;
s108, dry etching the Silicon wafer Silicon to form a groove through anisotropic etching, as shown in FIG. 10;
s109, placing the etched chip in an oxidation furnace tube for oxidation treatment, and generating the thickness of the silicon chip groove and the inner side wall of the groove undercut structure to be
A silicon oxide protective layer of (a);
s1010, depositing doped polycrystalline silicon polysilicon by a low-pressure chemical vapor deposition (LPCVD) method, and filling the groove Poly-Si Plug;
s1011, performing a Poly CMP chemical mechanical polishing process or a Poly Etch to completely remove Poly outside the trench;
s1012, CVD long sacrificial silicon Oxide SAC Oxide and Remove SAC Oxide purify the surface of the wafer;
s1013, PR on the yellow light process, developing to define a pattern, and heating an oxygen furnace tube Gate Oxide;
s1014, carrying out PR on the yellow light process, developing to define a pattern and Polysilicon, and finishing a Gate structure;
s1015, depositing CVD TEOS ILD (interlayer electronic induced Denp.);
s1016, completing the process and structure for increasing the effective area of the trench of the MOSFET.
Generally speaking, in order to obtain more transistor trench effective areas in the same package body/area, the embodiment of the invention utilizes the self-alignment preparation characteristic of the isolation layer, so that the number of trenches is increased, the surface area in the trenches is further increased through the etching undercut characteristic, and finally the purpose of maximally increasing the total number of trenches and the total effective area of the transistor is achieved.
A second embodiment of the present invention provides a chip, which is prepared by using any one of the methods for grooving a surface of a chip according to the first embodiment of the present invention.
The relevant content of the embodiments of the present invention can be understood by referring to the first embodiment of the present invention, and will not be discussed in detail herein.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, and the scope of the invention should not be limited to the embodiments described above.
Claims (10)
1. A method of grooving a surface of a chip, comprising:
the method comprises the steps that a plurality of mask structures are arranged at preset positions on the surface of a chip, a groove is formed between every two mask structures and comprises a first groove and a second groove, the first groove and the second groove are sequentially and alternately arranged, and the width between the mask structures is the exposure limit of exposure equipment.
2. The method of claim 1,
the first groove width is larger than the second groove width, the first groove width is the exposure limit of exposure equipment, and the width of the second groove plus the width of the interval between the second groove and the first groove is equal to the exposure limit.
3. The method of claim 1,
the first trench width is equal to the second trench width, and the first trench width, the second trench width, plus a spacing width between the second trench and the first trench, is equal to two of the exposure limits.
4. The method of claim 1, wherein the disposing a plurality of mask structures at predetermined locations on the surface of the chip comprises:
and arranging side walls on the surface of the chip corresponding to the first groove, and arranging the mask structures on two sides of the side walls.
5. The method of claim 4, wherein disposing the mask structure on both sides of the sidewall comprises:
carrying out oxidation treatment on the surface of the chip to generate a first protective film with a first preset thickness;
etching the first protective film, and reserving the first protective films on two sides of the side wall;
and depositing a second protective film with a second preset thickness on the surface of the chip, etching the second protective film, and reserving the second protective film on the first protective film to obtain the mask structure.
6. The method of claim 5,
the first protective film is a silicon oxide protective film;
the second protective film is a silicon nitride protective film.
7. The method of claim 5, wherein the etching the first protective film, leaving the first protective film on both sides of the sidewall, comprises:
depositing a developer on the first protective film, defining a pattern by development, and etching the first protective film by a yellow light process, leaving a predetermined width of the first protective film on both sides of the sidewall.
8. The method according to any one of claims 1-7, wherein after disposing a plurality of mask structures at predetermined locations on the surface of the chip, before disposing a trench between each two mask structures, the method further comprises:
and carrying out isotropic etching on the positions of two side walls of the first groove or one side wall of the first groove and the positions of two side walls of the second groove or one side wall of the second groove according to the preset voltage bearing capacity to form an undercut structure.
9. The method of claim 8, wherein after one trench is disposed between every two mask structures, the method further comprises:
and etching the chip substrate part subjected to the undercut treatment and the chip substrate at the side wall position by using the mask structure to obtain the first groove and the second groove, and removing the mask structure.
10. A chip prepared by the method of grooving a surface of a chip according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011140415.0A CN112259453A (en) | 2020-10-22 | 2020-10-22 | Method for slotting surface of chip and chip |
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| CN202011140415.0A CN112259453A (en) | 2020-10-22 | 2020-10-22 | Method for slotting surface of chip and chip |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN110349906A (en) * | 2018-04-03 | 2019-10-18 | 长鑫存储技术有限公司 | A kind of forming method of autoregistration groove |
| CN110783189A (en) * | 2019-09-23 | 2020-02-11 | 珠海格力电器股份有限公司 | Preparation method of chip groove and preparation method of chip |
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2020
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| US5068202A (en) * | 1988-12-15 | 1991-11-26 | Sgs-Thomson Microelectronics S.R.L. | Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures |
| US20030129837A1 (en) * | 2002-01-10 | 2003-07-10 | Gerhard Enders | Method for processing a substrate to form a structure |
| CN1638053A (en) * | 2004-01-08 | 2005-07-13 | 三星电子株式会社 | Method of adjusting deviation of critical dimension of patterns |
| CN103000533A (en) * | 2012-12-24 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacturing method of self-aligned super junction power transistor |
| CN110349906A (en) * | 2018-04-03 | 2019-10-18 | 长鑫存储技术有限公司 | A kind of forming method of autoregistration groove |
| CN110783189A (en) * | 2019-09-23 | 2020-02-11 | 珠海格力电器股份有限公司 | Preparation method of chip groove and preparation method of chip |
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