CN110349906A - A kind of forming method of autoregistration groove - Google Patents
A kind of forming method of autoregistration groove Download PDFInfo
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- CN110349906A CN110349906A CN201810289842.1A CN201810289842A CN110349906A CN 110349906 A CN110349906 A CN 110349906A CN 201810289842 A CN201810289842 A CN 201810289842A CN 110349906 A CN110349906 A CN 110349906A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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Abstract
The present invention provides a kind of forming method of autoregistration groove, comprising: in formation ion barrier layer, mask layer and patterned photoresist layer in semiconductor substrate；In forming mask structure on ion barrier layer, there is the first opening of exposure ion barrier layer between adjacent mask structure；Ion implanting is carried out to the side wall of mask structure, doped sidewalls is formed in its two sides, there is undoped exposure mask convex block between doped sidewalls, doped sidewalls are greater than exposure mask convex block to the etching selection ratio of ion barrier layer to the etching selection ratio of ion barrier layer；First time etching is carried out to resulting structures based on the first opening, forms pre- groove in semiconductor substrate；Exposure mask convex block is removed simultaneously to form the second opening；Above-mentioned resulting structures are performed etching based on pre- groove and the second opening, form first groove and second groove in semiconductor substrate；And doped sidewalls and ion barrier layer are removed, form autoregistration groove.Solve the problems, such as that existing method step is complicated, at high cost through the invention.
Description
Technical field
The present invention relates to semiconductor fields, more particularly to a kind of forming method of autoregistration groove.
Background technique
A kind of mode that IC designer manufactures faster smaller integrated circuit is to reduce each member including integrated circuit
Separation distance between part, this method for increasing circuits on substrates component density commonly referred to as " scale " or increase device integration degree；
And vertical transistor structure design can effectively reduce active region consumption and improve integrated level, generally by deep trench every
From transistor, shallow trench isolation source-drain area.
And existing deep trench and the forming method of shallow trench are generally as shown in Figure 1 to 11, specific forming process include: as
Shown in Fig. 1, semi-conductive substrate 101 is provided, buffer layer 102, etching stop layer are sequentially formed in Yu Suoshu semiconductor substrate 101
103, ion barrier layer 104, mask layer 105 and photoresist layer, and photoetching is carried out to the photoresist layer, it is patterned to be formed
Photoresist layer 106；Later as shown in Figures 2 and 3, by patterned photoresist layer 106 successively to the mask layer 105 and institute
Ion barrier layer 104 is stated to perform etching；Later as shown in Figure 4 and Figure 5, in the ion barrier layer 104 of reservation and mask layer 105
Surface forms first medium layer 107, and removes the first medium layer of 105 upper surface of ion barrier layer 104 and mask layer of reservation
107, to form the first opening；Later as shown in Figure 6 and Figure 7, by the first opening successively to etching stop layer 103, buffer layer
102 and semiconductor substrate 101 perform etching, to form first groove 108 in the semiconductor substrate 101, and in described the
The first filled layer 109 is formed in one groove 108；Later as shown in Figure 8 and Figure 9,103 upper surface of etching stop layer is removed
The ion barrier layer 104 and the first medium layer 107, and in the etching stop layer 103 and first filled layer 109
Surface forms second dielectric layer 110, to form the second opening；Later as shown in Figure 10, by the second opening successively to the quarter
Erosion stop-layer 103, buffer layer 102 and the semiconductor substrate 101 perform etching, to be formed in the semiconductor substrate 101
Second groove 111；It is last as shown in figure 11, the second filled layer 112 is formed in Yu Suoshu second groove 111.As it can be seen that above-mentioned formation
Method is mainly performed etching by using mask plate twice, to be respectively formed deep trench and shallow trench；Therefore, using above-mentioned shape
When at the different groove of method preparation depth, step is complicated, production cost is higher.
In consideration of it, it is necessary to design a kind of forming method of new autoregistration groove with to solve the above technical problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of formation sides of autoregistration groove
Method, step complexity and higher cost when for solving the problem of to prepare the groove of different depth using existing forming method.
In order to achieve the above objects and other related objects, the present invention provides a kind of forming method of autoregistration groove, described
Forming method includes:
S1: provide semi-conductive substrate, and in sequentially formed in the semiconductor substrate ion barrier layer from bottom to up,
Mask layer and patterned photoresist layer；
S2: performing etching the mask layer using the patterned photoresist layer, is located at ion resistance to be formed
A plurality of mask structures on interlayer, have the first opening between the adjacent mask structure, and first opening exposes institute
State the first position of ion barrier layer；
S3: carrying out ion implanting to the side wall of the mask structure, to form doped sidewalls in the mask structure two sides,
There is undoped exposure mask convex block, wherein etching of the doped sidewalls to the ion barrier layer between the doped sidewalls
It selects than being greater than the exposure mask convex block to the etching selection ratio of the ion barrier layer；
S4: first time etching is carried out to S3 step resulting structures based on first opening, the first time etching is at least
The first position of the ion barrier layer and the semiconductor substrate under the first position are removed, in institute
It states and forms pre- groove in semiconductor substrate；The exposure mask convex block of the removal between the adjacent doped sidewalls simultaneously, in
The second opening is formed between the doped sidewalls；Wherein, second opening exposes the second position of the ion barrier layer；
S5: being carried out second to S4 step resulting structures and etched based on the pre- groove and second opening, and described the
The secondarily etched second position at least removing the ion barrier layer and described under the second position are partly led
Body substrate, to form first groove in the semiconductor substrate, wherein the semiconductor substrate corresponds to the pre- groove
Position is formed as second groove, and the depth of the second groove is different from the depth of the first groove；And
S6: the doped sidewalls and the ion barrier layer are removed other than the first position and the second position
Third position, to form the autoregistration groove.
Optionally, second of etching further includes at least removing the semiconductor lining for being located at the pre- channel bottom
Bottom, to form the second groove in the semiconductor substrate；Wherein, the depth of the second groove is greater than the pre- groove
Depth and be greater than the first groove depth.
Optionally, the first time etching and second of etching are implemented to be continuous.
Optionally, the second groove is formed in the semiconductor substrate by first time etching, removed simultaneously
The part exposure mask convex block between the adjacent doped sidewalls；Wherein, the depth of the second groove is equal to described pre-
The depth of groove.
Optionally, the first time etching and second of etching are discontinuous implementation, the forming method further include:
Filled layer is formed in S4-1: the Yu Suoshu second groove between S4 step and S5 step, and is removed and be located at the adjacent doping
The part exposure mask convex block between side wall, with the second position of the exposure ion barrier layer.
Optionally, the forming method further include: the S4-1-1 between S4 step and S4-1 step: described in removal part
Doped sidewalls make the height of the doped sidewalls retained be equal to the height of the exposure mask convex block retained.
Optionally, the depth of the second groove is greater than the depth of the first groove.
Optionally, the depth of the second groove is less than the depth of the first groove.
Optionally, ion note is carried out using side wall of the tilt angle ion implantation technology to the mask structure in S3 step
Enter.
Optionally, the thickness of the tilt angle of the tilt angle ion implantation technology and the mask structure is positively correlated,
It is negatively correlated with the width of first opening.
Optionally, the range of tilt angles of the tilt angle ion implantation technology is between 10 degree~80 degree, the inclination
Angle is the angular deflection relative to the positive ion implanting direction of the upper surface of the vertical semiconductor substrate.
Optionally, the material of the mask layer includes carbon-coating；The material of the doped sidewalls is different from the exposure mask convex block
Material includes boron.
Optionally, the injection gas of the ion implanting is selected from by diborane and the constituted group of boron trifluoride wherein
One of.
Optionally, in the doped sidewalls atomic percent of boron between 5atom%~25atom%.
Optionally, for the doped sidewalls to the etching selection ratio of the ion barrier layer between 20~30, the exposure mask is convex
Block to the etching selection ratio of the ion barrier layer between 10~15 so that the doped sidewalls are still after S4 step and S5 step
Remain in the semiconductor substrate, the residual altitude of the doped sidewalls is more than or equal to the doping after S3 step after S4 step
The half of the formation height of side wall.
Optionally, S1 step further include sequentially formed between the semiconductor substrate and the ion barrier layer from down toward
On buffer layer and etching stop layer the step of.
As described above, the forming method of autoregistration groove of the invention, has the advantages that
Forming method of the present invention carries out ion implanting by the side wall to the mask structure, makes the doped sidewalls
Exposure mask convex block is greater than to the etching selection ratio of ion barrier layer, by using an exposure mask to the etching selection ratio of ion barrier layer
The preparation of different depth groove can be realized in version, i.e., realizes the preparation of second groove by mask plate, carried out by doped sidewalls
The preparation of first groove is realized in autoregistration, also reduces production cost while simplifying processing step.
Forming method of the present invention can also increase the adjustable of first groove depth by the selection to mask layer thickness
Section property, expands application range.
Detailed description of the invention
Fig. 1 to Figure 11 is shown as the structural schematic diagram of each step in existing different depth groove forming method.
Figure 12 to Figure 17 is shown as the structural schematic diagram of each step in forming method described in the embodiment of the present invention one.
Figure 18 to Figure 27 is shown as the structural schematic diagram of each step in forming method described in the embodiment of the present invention two.
Figure 28 is shown as the structural schematic diagram of autoregistration groove described in the embodiment of the present invention three.
Component label instructions
101 semiconductor substrate, 102 buffer layer
103 etching stop layer, 104 ion barrier layer
The patterned photoresist layer of 105 mask layer 106
107 first medium layer, 108 first groove
109 first filled layer, 110 second dielectric layer
111 second groove, 112 second filled layer
201 semiconductor substrate, 202 buffer layer
203 etching stop layer, 204 ion barrier layer
The patterned photoresist layer of 205 mask layer 206
207 mask structures 208 first opening
209 exposure mask convex block, 210 doped sidewalls
211 pre- grooves 212 second are open
213 second groove, 214 first groove
301 semiconductor substrate, 302 buffer layer
303 etching stop layer, 304 ion barrier layer
The patterned photoresist layer of 305 mask layer 306
307 mask structures 308 first opening
309 exposure mask convex block, 310 doped sidewalls
311 pre- 312 encapsulant layers of groove
313 filled layers 314 second opening
315 first grooves
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book is understood other advantages and efficacy of the present invention easily.
Figure 12 is please referred to Figure 28.It should be clear that this specification structure depicted in this specification institute accompanying drawings, ratio, size etc., are only used
To cooperate the revealed content of specification, so that those skilled in the art understands and reads, being not intended to limit the invention can
The qualifications of implementation, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
It is whole, in the case where not influencing the effect of present invention can be generated and the purpose that can reach, it should all still fall in disclosed skill
Art content obtains in the range of capable of covering.Meanwhile in this specification it is cited as "upper", "lower", "left", "right", " centre " and
The term of " one " etc. is merely convenient to being illustrated for narration, rather than to limit the scope of the invention, relativeness
It is altered or modified, under the content of no substantial changes in technology, when being also considered as the enforceable scope of the present invention.
Embodiment one
As shown in Figure 12 to Figure 17, the present embodiment provides a kind of forming method of autoregistration groove, the forming method packet
It includes:
S1: semi-conductive substrate 201 is provided, and in sequentially forming ion from bottom to up in the semiconductor substrate 201
Barrier layer 204, mask layer 205 and patterned photoresist layer 206；
S2: performing etching the mask layer 205 using the patterned photoresist layer 206, to be formed positioned at described
A plurality of mask structures 207 on ion barrier layer 204 have the first opening 208, institute between the adjacent mask structure 207
State the first position that the first opening 208 exposes the ion barrier layer 204；
S3: ion implanting is carried out to the side wall of the mask structure 207, is mixed with being formed in 207 two sides of mask structure
Miscellaneous side wall 210 has undoped exposure mask convex block 209 between the doped sidewalls 210, wherein 210 pairs of institutes of the doped sidewalls
The etching selection ratio for stating ion barrier layer 204 is greater than the exposure mask convex block 209 to the etching selection of the ion barrier layer 204
Than；
S4: first time etching is carried out based on first opening, 208 pairs of S3 step resulting structures, the first time is etched to
The first position of the ion barrier layer 204 and the semiconductor substrate under the first position are removed less
201, to form pre- groove 211 in the semiconductor substrate 201；Removal is between the adjacent doped sidewalls 210 simultaneously
The exposure mask convex block 209, between the doped sidewalls 210 formed second opening 212；Wherein, second opening 212
Expose the second position of the ion barrier layer 201；
S5: carrying out second based on 212 pairs of S4 step resulting structures of the pre- groove 211 and second opening and etch,
Second of etching at least removes the second position of the ion barrier layer 204 and under the second position
The semiconductor substrate 201, to form first groove 214 in the semiconductor substrate 201, wherein the semiconductor substrate
201 positions for corresponding to the pre- groove 211 are formed as second groove 213, and the depth of the second groove 213 is different from described
The depth of first groove 214；And
S6: the doped sidewalls 210 and the ion barrier layer 204 are removed in the first position and the second position
Third position in addition, to form the autoregistration groove.
Figure 12 is please referred to below to be described in detail to Figure 17 forming method described in the present embodiment.
As shown in figure 12, semi-conductive substrate 201 is provided, and in sequentially formed in the semiconductor substrate 201 from down toward
On ion barrier layer 204, mask layer 205 and patterned photoresist layer 206.
As an example, as shown in figure 12, S1 step further includes in the semiconductor substrate 201 and the ion barrier layer
The step of buffer layer 202 and etching stop layer 203 from bottom to up are sequentially formed between 204.
Specifically, the material of the semiconductor substrate 201 includes silicon (Si) layer；It is partly led using high temperature oxidation process in described
Buffer layer 202 is formed in body substrate 201, the material of the buffer layer 202 includes silica (SiO2) layer, the buffer layer
202 thickness range is between 3nm (nanometer)~15nm；Using high temperature furnace pipe deposition or chemical vapor deposition process in the buffering
Etching stop layer 203 is formed on layer 202, the material of the etching stop layer 203 includes silicon nitride (SiN) layer, the etch-stop
Only the thickness range of layer 203 is between 30nm~150nm；Using chemical vapor deposition process in shape on the etching stop layer 203
At ion barrier layer 204, the material of the ion barrier layer 204 includes silica (SiO2) layer, the ion barrier layer 204
Thickness range between 30nm~100nm；Using chemical vapor deposition process in forming mask layer on the ion barrier layer 204
205, the material of the mask layer 205 includes carbon (C) layer, and the thickness range of the mask layer 205 is between 20nm~200nm.
As shown in Figure 12 and Figure 13, the mask layer 205 is performed etching using the patterned photoresist layer 206,
To form a plurality of mask structures 207 being located on the ion barrier layer 204, have between the adjacent mask structure 207
First opening 208, first opening 208 expose the first position of the ion barrier layer 204.
As an example, the method for forming the mask structure 207 include: in spin coating photoresist on the mask layer 205, and
The photoresist is patterned by mask plate, the mask layer 205 is carried out using patterned photoresist 206 later
Etching, to form the mask structure 207.It should be noted that the width D of first opening 208 is to be subsequently formed
The width of the second groove 213, therefore in the production process, the width D of first opening 208 can according to actual needs really
It is fixed.
As shown in figure 14, ion implanting is carried out to the side wall of the mask structure 207, in 207 liang of the mask structure
Side forms doped sidewalls 210, has undoped exposure mask convex block 209 between the doped sidewalls 210, wherein the doped side
Wall 210 is greater than the exposure mask convex block 209 to the ion barrier layer 204 to the etching selection ratio of the ion barrier layer 204
Etching selection ratio.
It should be noted that the width of the exposure mask convex block 209 is the width for the first groove 214 being subsequently formed
Degree, therefore in the production process, the width of the exposure mask convex block 209 can determine according to actual needs, thus convex according to the exposure mask
The width of block 209 determines the width of the doped sidewalls 210, and then determines the energy and dosage of ion implanting.
As an example, carrying out ion implanting using side wall of the tilt angle ion implantation technology to the mask structure 207.
Specifically, the thickness positive of the tilt angle of the tilt angle ion implantation technology and the mask structure 207
It closes, it is negatively correlated with the width D of first opening 208；That is, the mask structure 207 is thicker, using tilt angle from
Tilt angle when sub- injection technology is bigger；First opening, 208 wider, inclining when using tilt angle ion implantation technology
Rake angle is smaller.Therefore during actual fabrication, the thickness and described first for needing to comprehensively consider the mask structure 207 are open
208 width D, and then determine the tilt angle.Preferably, in the present embodiment, the tilt angle ion implantation technology
Tilt angle theta range between 10 degree~80 degree, the tilt angle theta is relative to the upper of the vertical semiconductor substrate 201
The angular deflection in the positive ion implanting direction on surface.
As an example, the injection gas of the ion implanting is selected from by its of diborane and the constituted group of boron trifluoride
One of；Wherein, in the doped sidewalls 210 atomic percent of boron between 5atom%~25atom%, i.e. doped sidewalls
It is 5%~25% that the number of boron atom, which accounts for the percentage of all total atom numbers, in 210.
As an example, the material of the exposure mask convex block 209 includes carbon, the material of the doped sidewalls 210 is covered different from described
The material of film convex block 209 includes boron；The doped sidewalls 210 to the etching selection ratio of the ion barrier layer 204 between 20~
30, the exposure mask convex block 209 to the etching selection ratio of the ion barrier layer 204 between 10~15 so that in S4 step and S5
The doped sidewalls 210 still remain in the semiconductor substrate 201 after step, and the doped sidewalls 210 is residual after S4 step
The half of the formation height of the doped sidewalls 210 after staying height to be more than or equal to S3 step.
As shown in figure 15, first time etchings are carried out based on first opening, 208 pairs of S3 step resulting structures, described first
Secondary etching at least removes the first position of the ion barrier layer 204 and described under the first position is partly led
Body substrate 201, to form pre- groove 211 in the semiconductor substrate 201；Removal is located at the adjacent doped sidewalls simultaneously
The exposure mask convex block 209 between 210, to form the second opening 212 between the doped sidewalls 210；Wherein, described second
Opening 212 exposes the second position of the ion barrier layer 204.
It should be noted that the present embodiment utilizes the etch rate of the exposure mask convex block 209 under identical etching condition
It is to form the second opening 212 between the adjacent doped sidewalls 210, i.e., logical greater than the etch rate of the doped sidewalls 210
The etching window that the second opening 212 defines the first groove 214 is crossed, realizes autoregistration.
As shown in figure 16, second is carried out based on 212 pairs of S4 step resulting structures of the pre- groove 211 and second opening
Secondary etching, second of etching at least remove the second position of the ion barrier layer 204 and positioned at described second
The semiconductor substrate 201 under position, to form first groove 214 in the semiconductor substrate 201, wherein described half
The position that conductor substrate 201 corresponds to the pre- groove 211 is formed as second groove 213.
It should be noted that in the manufacturing process of Subsequent semiconductor device, it can according to actual needs, to first ditch
Slot 214 and the second groove 213 carry out the filling of respective material, to realize its corresponding function.Such as in the first groove 214
Interior filling conductive material, to form notched gates；In fill insulant in the second groove 213, to form isolation structure etc..
As an example, second of etching further includes at least removing described partly the leading for being located at pre- 211 bottom of groove
Body substrate 201, to form the second groove 213 in the semiconductor substrate 201；Wherein, the depth of the second groove 213
Degree is greater than the depth of the pre- groove 211 and is greater than the depth of the first groove 214.Preferably, in the present embodiment, institute
It states etching for the first time and second of etching is implemented to be continuous；The first groove 214 as described in being formed using dry etch process
And the second groove 213, wherein 1 range of depth H of the first groove 214 is between 100nm~200nm, second ditch
2 range of depth H of slot 213 is between 200nm~300nm.
As shown in figure 17, the doped sidewalls 210 and the ion barrier layer 204 are removed in the first position and described
Third position other than second position, to form the autoregistration groove.
The autoregistration groove structure prepared by above-mentioned forming method is as shown in figure 17, the autoregistration groove packet
It includes:
Semiconductor substrate 201；And
The first groove 214 and second groove 213 being formed in the semiconductor substrate 201, wherein the second groove
213 depth is greater than the depth of the first groove 214.
As an example, as shown in figure 17, the autoregistration groove further include: be formed in the semiconductor substrate 201
Buffer layer 202 and etching stop layer 203.
Specifically, the material of the semiconductor substrate 201 includes silicon (Si) layer；The material of the buffer layer 202 includes two
Silica (SiO2) layer, the thickness range of the buffer layer 202 is between 3nm~15nm；The material packet of the etching stop layer 203
Silicon nitride comprising (SiN) layer, the thickness range of the etching stop layer 203 is between 30nm~150nm.
Specifically, the first groove 214 and the second groove 213 are spaced apart from each other arrangement, the first groove 214
1 range of depth H is between 100nm~200nm, and 2 range of depth H of the second groove 213 is between 200nm~300nm.
Embodiment two
As shown in Figure 18 to Figure 27, a kind of forming method of autoregistration groove, the forming method are present embodiments provided
Include:
S1: semi-conductive substrate 301 is provided, and in sequentially forming ion from bottom to up in the semiconductor substrate 301
Barrier layer 304, mask layer 305 and patterned photoresist layer 306；
S2: performing etching the mask layer 305 using the patterned photoresist layer 306, to be formed positioned at described
A plurality of mask structures 307 on ion barrier layer 304 have the first opening 308, institute between the adjacent mask structure 307
State the first position that the first opening 308 exposes the ion barrier layer 304；
S3: ion implanting is carried out to the side wall of the mask structure 307, is mixed with being formed in 307 two sides of mask structure
Miscellaneous side wall 310 has undoped exposure mask convex block 309 between the doped sidewalls 310, wherein 310 pairs of institutes of the doped sidewalls
The etching selection ratio for stating ion barrier layer 304 is greater than the exposure mask convex block 309 to the etching selection of the ion barrier layer 304
Than；
S4: first time etching is carried out based on first opening, 308 pairs of S3 step resulting structures, the first time is etched to
The first position of the ion barrier layer 304 and the semiconductor substrate under the first position are removed less
301, to form pre- groove 311 in the semiconductor substrate 301；Removal is between the adjacent doped sidewalls 310 simultaneously
The exposure mask convex block 309, between the doped sidewalls 310 formed second opening 314；Wherein, second opening 314
Expose the second position of the ion barrier layer 304；
S5: carrying out second based on 314 pairs of S4 step resulting structures of the pre- groove 311 and second opening and etch,
Second of etching at least removes the second position of the ion barrier layer 304 and under the second position
The semiconductor substrate 301, to form first groove 315 in the semiconductor substrate 301, wherein the semiconductor substrate
301 positions for corresponding to the pre- groove 311 are formed as second groove, and the depth of the second groove is different from first ditch
The depth of slot；And
S6: the doped sidewalls 310 and the ion barrier layer 304 are removed in the first position and the second position
Third position in addition, to form the autoregistration groove.
Figure 18 is please referred to below to be described in detail to Figure 26 forming method described in the present embodiment.
As shown in figure 18, semi-conductive substrate 301 is provided, and in sequentially formed in the semiconductor substrate 301 from down toward
On ion barrier layer 304, mask layer 305 and patterned photoresist layer 306.
As an example, as shown in figure 18, S1 step further includes in the semiconductor substrate 301 and the ion barrier layer
The step of buffer layer 302 and etching stop layer 303 from bottom to up are sequentially formed between 304.
Specifically, the material of the semiconductor substrate 301 includes silicon (Si) layer；It is partly led using high temperature oxidation process in described
Buffer layer 302 is formed in body substrate 301, the material of the buffer layer 302 includes silica (SiO2) layer, the buffer layer
302 thickness range is between 3nm~15nm；Using high temperature furnace pipe deposition or chemical vapor deposition process in the buffer layer 302
Upper formation etching stop layer 303, the material of the etching stop layer 303 include silicon nitride (SiN) layer, the etching stop layer
303 thickness range is between 30nm~150nm；Using chemical vapor deposition process in formed on the etching stop layer 303 from
Sub- barrier layer 304, the material of the ion barrier layer 304 include silica (SiO2) layer, the thickness of the ion barrier layer 304
Range is spent between 30nm~100nm；Using chemical vapor deposition process on the ion barrier layer 304 formed mask layer 305,
The material of the mask layer 305 includes carbon (C) layer, and the thickness range of the mask layer 305 is between 20nm~200nm.
As shown in Figure 18 and Figure 19, the mask layer 305 is performed etching using the patterned photoresist layer 306,
To form a plurality of mask structures 307 being located on the ion barrier layer 304, have between the adjacent mask structure 307
First opening 308, first opening 308 expose the first position of the ion barrier layer 304.
As an example, the method for forming the mask structure 307 include: in spin coating photoresist on the mask layer 305, and
The photoresist is patterned by mask plate, the mask layer 305 is carried out using patterned photoresist 306 later
Etching, to form the mask structure 307.It should be noted that the width D of first opening 308 is to be subsequently formed
The width of the second groove, therefore in the production process, the width D of first opening 308 can be determine according to actual needs.
As shown in figure 20, ion implanting is carried out to the side wall of the mask structure 307, in 307 liang of the mask structure
Side forms doped sidewalls 310, has undoped exposure mask convex block 309 between the doped sidewalls 310, wherein the doped side
Wall 310 is greater than the exposure mask convex block 309 to the ion barrier layer 304 to the etching selection ratio of the ion barrier layer 304
Etching selection ratio.
It should be noted that the width of the exposure mask convex block 309 is the width for the first groove 315 being subsequently formed
Degree, therefore in the production process, the width of the exposure mask convex block 309 can determine according to actual needs, thus convex according to the exposure mask
The width of block 309 determines the width of the doped sidewalls 310, and then determines the energy and dosage of ion implanting.
As an example, carrying out ion implanting using side wall of the tilt angle ion implantation technology to the mask structure 307.
Specifically, the thickness positive of the tilt angle of the tilt angle ion implantation technology and the mask structure 307
It closes, it is negatively correlated with the width D of first opening 308；That is, the mask structure 307 is thicker, using tilt angle from
Tilt angle when sub- injection technology is bigger；First opening, 308 wider, inclining when using tilt angle ion implantation technology
Rake angle is smaller.Therefore during actual fabrication, the thickness and described first for needing to comprehensively consider the mask structure 307 are open
308 width D, and then determine the tilt angle.Preferably, in the present embodiment, the tilt angle ion implantation technology
Tilt angle theta range between 10 degree~80 degree, the tilt angle theta is relative to the upper of the vertical semiconductor substrate 301
The angular deflection in the positive ion implanting direction on surface.
As an example, the injection gas of the ion implanting is selected from by its of diborane and the constituted group of boron trifluoride
One of；Wherein, in the doped sidewalls 310 atomic percent of boron between 5atom%~25atom%, i.e. doped sidewalls
It is 5%~25% that the number of boron atom, which accounts for the percentage of all total atom numbers, in 210.
As an example, the material of the exposure mask convex block 309 includes carbon, the material of the doped sidewalls 310 is covered different from described
The material of film convex block 309 includes boron；The doped sidewalls 310 to the etching selection ratio of the ion barrier layer 304 between 20~
30, the exposure mask convex block 309 to the etching selection ratio of the ion barrier layer 304 between 10~15 so that in S4 step and S5
The doped sidewalls 310 still remain in the semiconductor substrate 301 after step, and the doped sidewalls 310 is residual after S4 step
The half of the formation height of the doped sidewalls 310 after staying height to be more than or equal to S3 step.
As shown in Figure 21 to Figure 25, first time etching, institute are carried out based on first opening, 308 pairs of S3 step resulting structures
It states and etches the first position at least removing the ion barrier layer 304 and the institute under the first position for the first time
Semiconductor substrate 301 is stated, to form pre- groove 311 in the semiconductor substrate 301；Removal is located at the adjacent doping simultaneously
The exposure mask convex block 309 between side wall 310, to form the second opening 314 between the doped sidewalls 310；Wherein, described
Second opening 314 exposes the second position of the ion barrier layer 304.
It should be noted that the present embodiment utilizes the etch rate of the exposure mask convex block 309 under identical etching condition
It is to form the second opening 314 between the adjacent doped sidewalls 310, i.e., logical greater than the etch rate of the doped sidewalls 310
The etching window that the second opening 314 defines the first groove 315 is crossed, realizes autoregistration.
As an example, as shown in figure 21, described the is formed in the semiconductor substrate 301 by first time etching
Two grooves, while removing the part exposure mask convex block 309 between the adjacent doped sidewalls 310；Wherein, described second
The depth of groove is equal to the depth of the pre- groove 311.That is, the present embodiment be directly by the first time etching in
The second groove is formed in the semiconductor substrate 301, while being retained described in part between the adjacent doped sidewalls 310
Exposure mask convex block 309.
As an example, as shown in figure 22, the forming method further include: the S4-1- between S4 step and S4-1 step
1: the removal part doped sidewalls 310 make the height of the doped sidewalls 310 retained be equal to the exposure mask convex block retained
309 height.
Specifically, surface planarisation processing is carried out to the doped sidewalls 310 by chemical mechanical milling tech, so as to protect
The height for the doped sidewalls 310 stayed is equal to the height of the exposure mask convex block 309 retained.
As an example, as shown in Figure 23 to Figure 25, the forming method further include: the first time etching and described second
Secondary etching is discontinuous implementation, forms filled layer 313 in S4-1: the Yu Suoshu second groove between S4 step and S5 step,
And the part exposure mask convex block 309 between the adjacent doped sidewalls 310 is removed, with the exposure ion barrier layer
304 second position.
Specifically, as shown in figure 23 and figure 24, the method for forming the filled layer 313 includes: using chemical vapor deposition
Technique in the second groove, encapsulant layer 312 is formed on the doped sidewalls 310 and the exposure mask convex block 309, and adopt
Surface planarisation processing is carried out to the encapsulant layer 312 with chemical mechanical milling tech, exposes the exposure mask convex block
309, form the filled layer 313.The material of the filled layer 313 includes insulating materials；Preferably, in the present embodiment, institute
The material for stating insulating materials includes silica (SiO2) layer；It is filled with silica (SiO2) layer second groove as half
The isolation structure of conductor device.Certainly, the material of the filled layer 313 can also choose other materials according to actual needs
Material, to form the other structures in semiconductor devices.
As shown in figure 26, second is carried out based on 314 pairs of S4 step resulting structures of the pre- groove 311 and second opening
Secondary etching, second of etching at least remove the second position of the ion barrier layer 304 and positioned at described second
The semiconductor substrate 301 under position, to form first groove 315 in the semiconductor substrate 301, wherein described half
The position that conductor substrate 301 corresponds to the pre- groove 311 is formed as second groove.
As an example, forming the first groove 315 using dry etch process, wherein the depth of the second groove
Greater than the depth of the first groove 315.Preferably, in the present embodiment, 1 range of depth H of the first groove 315 between
100nm~300nm, 2 range of depth H of the second groove is between 200nm~300nm.
It should be noted that in the manufacturing process of Subsequent semiconductor device, it can according to actual needs, to first ditch
Slot 315 carries out the filling of respective material, to realize its corresponding function, such as notched gates.
As shown in figure 27, the doped sidewalls 310 and the ion barrier layer 304 are removed in the first position and described
Third position other than second position, to form the autoregistration groove.
As an example, as shown in figure 27, the present embodiment further includes removing 304 top of ion barrier layer and side-walls
The step of filled layer 313.
The autoregistration groove structure prepared by above-mentioned forming method is as shown in figure 27, the autoregistration groove packet
It includes:
Semiconductor substrate 301；And
The first groove 315 and second groove being formed in the semiconductor substrate 301, wherein the second groove
Depth is greater than the depth of the first groove 315；And
The filled layer 313 being formed in the second groove.
As an example, as shown in figure 27, the autoregistration groove further include: be formed in the semiconductor substrate 301
Buffer layer 302 and etching stop layer 303.
Specifically, the material of the semiconductor substrate 301 includes silicon (Si) layer；The material of the buffer layer 302 includes two
Silica (SiO2) layer, the thickness range of the buffer layer 302 is between 3nm~15nm；The material packet of the etching stop layer 303
Silicon nitride comprising (SiN) layer, the thickness range of the etching stop layer 303 is between 30nm~150nm；The material of the filled layer 313
Matter includes silica (SiO2) layer, the thickness range of the filled layer 313 is between 200nm~300nm.
Specifically, the first groove 315 and the second groove are spaced apart from each other arrangement, the depth of the first groove 315
H1 range is spent between 100nm~300nm, and 2 range of depth H of the second groove is between 200nm~300nm.
Embodiment three
As shown in figure 28, the difference of forming method described in forming method described in the present embodiment and embodiment two is described the
The depth of one groove 315 is different, and in the present embodiment, the depth of the first groove 315 is greater than the depth of the second groove.
As an example, the first groove and the second groove are spaced apart from each other arrangement, the depth H 1 of the first groove
Range is between 200nm~400nm, and 2 range of depth H of the second groove is between 200nm~300nm.
In embodiment two and embodiment three, since first groove and second groove are individually disposable formation, therefore
When forming the first groove, it can realize by the thickness of the adjusting mask layer and increase the adjustable of the first groove depth
Section property, can the depth according to actual needs to the first groove be adjusted；In conjunction with the embodiments two and embodiment three it is found that
The depth adjustable extent of first groove of the present invention is 100nm~400nm.
In conclusion the forming method of autoregistration groove of the invention, has the advantages that
Forming method of the present invention carries out ion implanting by the side wall to the mask structure, makes the doped sidewalls
Exposure mask convex block is greater than to the etching selection ratio of ion barrier layer, by using an exposure mask to the etching selection ratio of ion barrier layer
The preparation of different depth groove can be realized in version, i.e., realizes the preparation of second groove by mask plate, carried out by doped sidewalls
The preparation of first groove is realized in autoregistration, also reduces production cost while simplifying processing step.
Forming method of the present invention can also increase the adjustable of first groove depth by the selection to mask layer thickness
Section property, expands application range.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (16)
1. a kind of forming method of autoregistration groove, which is characterized in that the forming method includes:
S1: semi-conductive substrate is provided, and in sequentially forming ion barrier layer, exposure mask from bottom to up in the semiconductor substrate
Layer and patterned photoresist layer；
S2: performing etching the mask layer using the patterned photoresist layer, is located at the ion barrier layer to be formed
On a plurality of mask structures, there is between the adjacent mask structure the first opening, first opening expose it is described from
The first position of sub- barrier layer；
S3: carrying out ion implanting to the side wall of the mask structure, described to form doped sidewalls in the mask structure two sides
There is undoped exposure mask convex block, wherein etching selection of the doped sidewalls to the ion barrier layer between doped sidewalls
Than being greater than the exposure mask convex block to the etching selection ratio of the ion barrier layer；
S4: first time etching is carried out to S3 step resulting structures based on first opening, the first time etching at least removes
The first position of the ion barrier layer and the semiconductor substrate under the first position, in described half
Pre- groove is formed in conductor substrate；The exposure mask convex block of the removal between the adjacent doped sidewalls simultaneously, in described
The second opening is formed between doped sidewalls；Wherein, second opening exposes the second position of the ion barrier layer；
S5: being carried out second to S4 step resulting structures and etched based on the pre- groove and second opening, and described second
Etching at least removes the second position of the ion barrier layer and the semiconductor lining under the second position
Bottom, to form first groove in the semiconductor substrate, wherein the semiconductor substrate corresponds to the position of the pre- groove
Be formed as second groove, the depth of the second groove is different from the depth of the first groove；And
S6: the third of the doped sidewalls and the ion barrier layer other than the first position and the second position is removed
Position, to form the autoregistration groove.
2. the forming method of autoregistration groove according to claim 1, which is characterized in that second etching further includes
The semiconductor substrate for being located at the pre- channel bottom is removed, at least to form second ditch in the semiconductor substrate
Slot；Wherein, the depth of the second groove is greater than the depth of the pre- groove and is greater than the depth of the first groove.
3. the forming method of autoregistration groove according to claim 2, which is characterized in that first time etching and described
Second of etching is implemented to be continuous.
4. the forming method of autoregistration groove according to claim 1, which is characterized in that by the first time etching in
The second groove is formed in the semiconductor substrate, while being removed and being covered described in the part between the adjacent doped sidewalls
Film convex block；Wherein, the depth of the second groove is equal to the depth of the pre- groove.
5. the forming method of autoregistration groove according to claim 4, which is characterized in that first time etching and described
Second etching is discontinuous implementation, the forming method further include: S4-1: Yu Suoshu the between S4 step and S5 step
Filled layer is formed in two grooves, and removes the part exposure mask convex block between the adjacent doped sidewalls, to expose
State the second position of ion barrier layer.
6. the forming method of autoregistration groove according to claim 5, which is characterized in that the forming method further include:
S4-1-1 between S4 step and S4-1 step: the removal part doped sidewalls make the height of the doped sidewalls retained
Degree is equal to the height of the exposure mask convex block retained.
7. the forming method of autoregistration groove according to claim 5, which is characterized in that the depth of the second groove is big
In the depth of the first groove.
8. the forming method of autoregistration groove according to claim 5, which is characterized in that the depth of the second groove is small
In the depth of the first groove.
9. the forming method of autoregistration groove according to claim 1, which is characterized in that use tilt angle in S3 step
Ion implantation technology carries out ion implanting to the side wall of the mask structure.
10. the forming method of autoregistration groove according to claim 9, which is characterized in that the tilt angle ion note
The thickness of the tilt angle and the mask structure that enter technique is positively correlated, negatively correlated with the width of first opening.
11. the forming method of autoregistration groove according to claim 9, which is characterized in that the tilt angle ion note
Enter the range of tilt angles of technique between 10 degree~80 degree, the tilt angle is relative to the upper of the vertical semiconductor substrate
The angular deflection in the positive ion implanting direction on surface.
12. the forming method of autoregistration groove according to claim 1, which is characterized in that the material packet of the mask layer
It is carbon-containing bed；The material of the doped sidewalls includes boron different from the material of the exposure mask convex block.
13. the forming method of autoregistration groove according to claim 12, which is characterized in that the injection of the ion implanting
Gas is selected from by one of diborane and the constituted group of boron trifluoride.
14. the forming method of autoregistration groove according to claim 12, which is characterized in that boron in the doped sidewalls
Atomic percent is between 5atom%~25atom%.
15. the forming method of autoregistration groove according to claim 14, which is characterized in that the doped sidewalls are to described
The etching selection ratio of ion barrier layer between 20~30, the exposure mask convex block to the etching selection ratio of the ion barrier layer between
10~15, so that the doped sidewalls still remain in the semiconductor substrate after S4 step and S5 step, institute after S4 step
State half of the residual altitude more than or equal to the formation height of the doped sidewalls after S3 step of doped sidewalls.
16. the forming method of autoregistration groove according to claim 1, which is characterized in that S1 step further includes in described
The step of buffer layer and etching stop layer from bottom to up is sequentially formed between semiconductor substrate and the ion barrier layer.
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| CN202110750889.5A CN113488430B (en) | 2018-04-03 | 2018-04-03 | Forming method of self-aligned groove |
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| CN111211090A (en) * | 2019-12-11 | 2020-05-29 | 合肥晶合集成电路有限公司 | Groove manufacturing method and semiconductor isolation structure manufacturing method |
| CN112259453A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Method for slotting surface of chip and chip |
| CN113496944A (en) * | 2020-04-08 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113675141A (en) * | 2020-05-15 | 2021-11-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2021249171A1 (en) * | 2020-06-12 | 2021-12-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| CN116364658A (en) * | 2023-05-31 | 2023-06-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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| WO2024148747A1 (en) * | 2023-01-11 | 2024-07-18 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
| CN116364658A (en) * | 2023-05-31 | 2023-06-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN113488430A (en) | 2021-10-08 |
| CN113488430B (en) | 2023-04-25 |
| CN110349906B (en) | 2021-11-09 |
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