CN116364658B - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Method for manufacturing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN116364658B
CN116364658B CN202310631116.4A CN202310631116A CN116364658B CN 116364658 B CN116364658 B CN 116364658B CN 202310631116 A CN202310631116 A CN 202310631116A CN 116364658 B CN116364658 B CN 116364658B
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layer
dielectric
substrate
forming
side wall
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CN116364658A (en
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郭哲劭
刘哲儒
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
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Abstract

The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a preparation substrate, wherein the preparation substrate comprises a substrate, a dielectric structure layer, a hard mask layer and a plurality of first dielectric parts which are arranged at intervals; forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the materials of the side wall structures to the materials of the first medium parts is different; removing part of the first medium part, taking the side wall structures as masks, and removing the rest of the first medium part, part of the hard mask layer, part of the medium structure layer and part of the substrate, wherein a groove formed between one group of side wall structures is a first preparation groove, and a groove formed between any two adjacent groups of side wall structures is a second preparation groove; and removing the side wall structure and the residual hard mask layer to form a first groove and a second groove, wherein the depth of the second groove is larger than that of the first groove. The method solves the problem that the performance of the device is affected due to the existence of double slopes in double-trench isolation in the prior art.

Description

Method for manufacturing semiconductor structure and semiconductor structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
In the process of CMOS (Complementary Metal Oxide Semiconductor ) image sensor, in order to improve the Full-Well Capacity (FWC) of the image sensor and reduce lattice defects caused in the process, a dual trench isolation process is introduced, in which the trench isolation depth of the photosensitive region is reduced, so that defects and impurity interference can be reduced, and at the same time, FWC is increased. However, the conventional dual trench isolation process is prone to cause the problem of dual slope of shallow trench isolation (Shallow Trench Isolation, STI for short) to affect device performance and increase the load of subsequent chemical mechanical polishing.
Disclosure of Invention
The present disclosure is directed to a method for manufacturing a semiconductor structure and a semiconductor structure, and aims to solve the problem that in the prior art, dual-slope dual-trench isolation affects device performance.
To achieve the above object, according to one aspect of the present application, there is provided a method for manufacturing a semiconductor structure, including: providing a preparation substrate, wherein the preparation substrate comprises a substrate, a dielectric structure layer and a hard mask layer which are sequentially stacked, and the preparation substrate further comprises a plurality of first dielectric parts which are arranged at intervals, and the first dielectric parts are positioned on part of the surface, far away from the dielectric structure layer, of the hard mask layer; forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the materials of the side wall structures to the materials of the first medium parts is different; removing part of the first dielectric part, taking the side wall structures as masks, and removing the rest of the first dielectric part, part of the hard mask layer, part of the dielectric structure layer and part of the substrate, wherein grooves formed between one group of side wall structures are first preparation grooves, and grooves formed between any two adjacent groups of side wall structures are second preparation grooves; and removing the side wall structure and the residual hard mask layer, so that the first preparation groove forms a first groove and the second preparation groove forms a second groove, the depth of the second groove is larger than that of the first groove, and the residual substrate and the residual dielectric structure layer form a substrate.
Further, forming a plurality of sets of sidewall structures on two sides of the plurality of first dielectric portions, including: forming a second dielectric layer on the exposed surface of each first dielectric part and the hard mask layer; and removing the second dielectric layers on the surfaces of the first dielectric parts far away from the hard mask layer and the surfaces of the hard mask layer far away from the dielectric structure layer, wherein the second dielectric layers on the side walls of the first dielectric parts form the side wall structure.
Further, a preliminary substrate is provided, comprising: providing the substrate; forming the dielectric structure layer on the exposed surface of the substrate; forming the hard mask layer and the first dielectric layer which are sequentially overlapped on the exposed surface of the dielectric structure layer; and removing part of the first dielectric layer, wherein the rest first dielectric layers form a plurality of first dielectric parts which are arranged at intervals, and the hard mask layers on two sides of the first dielectric parts are exposed.
Further, forming the dielectric structure layer on the exposed surface of the substrate includes: forming a first oxide layer on the exposed surface of the substrate; and forming an etching barrier layer on the exposed surface of the first oxide layer, wherein the first oxide layer and the etching barrier layer form the dielectric structure layer.
Further, removing a portion of the first dielectric layer, the remaining first dielectric layer forming a plurality of first dielectric portions disposed at intervals, including: forming a mask structure layer on the exposed surface of the first dielectric layer; forming a patterned photoresist layer on the exposed surface of the mask structure layer; removing part of the mask structure layer and part of the first dielectric layer through the patterned photoresist layer, so that part of the hard mask layer is exposed; and removing the residual patterned photoresist layer and the residual mask structure layer to form a plurality of first medium parts which are arranged at intervals.
Further, forming a mask structure layer on the exposed surface of the first dielectric layer, including: forming a second oxide layer on the exposed surface of the first dielectric layer; forming a carbon layer on the exposed surface of the second oxide layer; and forming a silicon oxynitride layer on the exposed surface of the carbon layer, wherein the second oxide layer, the carbon layer and the silicon oxynitride layer form the mask structure layer.
Further, forming a patterned photoresist layer on the exposed surface of the mask structure layer, including: spin-coating photoresist on the exposed surface of the mask structure layer to form a photoresist layer; and patterning the photoresist layer to form the patterned photoresist layer.
Further, the thickness of the first dielectric portion ranges from 800 a to 1200 a.
Further, the material of the first dielectric portion includes one of silicon, silicon oxide, and silicon nitride.
According to another aspect of the present application, a semiconductor structure is provided, and the semiconductor structure is manufactured by any one of the manufacturing methods of the semiconductor structure, and the semiconductor structure includes a substrate, a plurality of first trenches, and a plurality of second trenches, wherein the substrate includes a substrate and a dielectric structure layer stacked in sequence; the first grooves penetrate through the dielectric structure layer and are arranged in the substrate at intervals; and one second groove is arranged between any two adjacent first grooves, the second grooves penetrate through the dielectric structure layer to the substrate, and the depth of the second grooves is larger than that of the first grooves.
In the technical scheme of the application, firstly, a preparation substrate is provided, the preparation substrate comprises a substrate, a dielectric structure layer and a hard mask layer which are sequentially overlapped, the preparation substrate further comprises a plurality of first dielectric parts which are arranged at intervals, and the first dielectric parts are positioned on the surface of a part of the hard mask layer, which is far away from the dielectric structure layer; forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the materials of the side wall structures to the materials of the first medium parts is different; removing part of the first dielectric part, taking the side wall structures as masks, and removing the rest of the first dielectric part, part of the hard mask layer, part of the dielectric structure layer and part of the substrate, wherein grooves formed between one group of side wall structures are first preparation grooves, and grooves formed between any two adjacent groups of side wall structures are second preparation grooves; and removing the side wall structure and the residual hard mask layer, so that the first preparation groove forms a first groove and the second preparation groove forms a second groove, the depth of the second groove is larger than that of the first groove, and the residual substrate and the residual dielectric structure layer form a substrate. According to the method, the first dielectric part and the side wall structures are formed, part of the first dielectric part is removed, so that a certain thickness of the first dielectric part remains between each group of side wall structures, when the side wall structures are used as masks, different etching heights are generated relative to the remaining first dielectric part and the exposed hard mask layer, therefore, grooves with different depths can be generated through one etching, the side walls of the grooves are smooth, and the problem that the performance of a device is affected due to the fact that double slopes exist in double groove isolation in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 illustrates a flow chart of a method of fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 2 shows a schematic structural view of a preliminary substrate according to one embodiment of the present application;
FIG. 3 illustrates a schematic view of a semiconductor structure after forming a patterned photoresist layer according to one embodiment of the present application;
FIG. 4 illustrates a schematic diagram of a semiconductor structure after etching a portion of a first dielectric layer in accordance with one embodiment of the present application;
fig. 5 shows a schematic view of a semiconductor structure after forming a first dielectric portion according to an embodiment of the present application;
figure 6 illustrates a schematic diagram of a semiconductor structure after forming a second dielectric layer in accordance with one embodiment of the present application;
figure 7 illustrates a schematic diagram of a semiconductor structure after forming a sidewall structure in accordance with one embodiment of the present application;
FIG. 8 illustrates a schematic view of a semiconductor structure after etching a portion of a first dielectric portion in accordance with one embodiment of the present application;
fig. 9 shows a schematic view of a semiconductor structure after forming a first preliminary trench and a second preliminary trench according to an embodiment of the present application;
fig. 10 shows a schematic view of a semiconductor structure after forming a first trench and a second trench according to one embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a dielectric structural layer; 30. a hard mask layer; 40. a first medium section; 41. a first dielectric layer; 42. a mask structure layer; 43. a patterned photoresist layer; 50. a side wall structure; 51. a second dielectric layer; 61. a first trench; 62. a second trench; 63. a first preliminary trench; 64. a second preliminary trench; 201. a first oxide layer; 202. etching the barrier layer; 421. a second oxide layer; 422. a carbon layer; 423. a silicon oxynitride layer.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the dual-trench isolation in the prior art has a dual slope to affect the performance of the device, and in order to solve the above problem, the present application proposes a method for manufacturing a semiconductor structure and a semiconductor structure.
According to an embodiment of the application, a method for manufacturing a semiconductor structure is provided.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, providing a preparation substrate, as shown in fig. 5, where the preparation substrate includes a substrate 10, a dielectric structure layer 20, and a hard mask layer 30 stacked in sequence, and the preparation substrate further includes a plurality of first dielectric portions 40 disposed at intervals, where the first dielectric portions 40 are located on a portion of a surface of the hard mask layer 30 away from the dielectric structure layer 20;
step S102, as shown in fig. 7, forming a set of sidewall structures 50 on both sides of each of the first dielectric portions 40, where the etching selectivity of the material of the sidewall structures 50 is different from that of the material of the first dielectric portions 40;
step S103, as shown in fig. 8, of removing a portion of the first dielectric portion 40, and removing the remaining first dielectric portion 40, a portion of the hard mask layer 30, a portion of the dielectric structure layer 20, and a portion of the substrate 10, using the sidewall structures 50 as masks, wherein a trench formed between one set of the sidewall structures 50 is a first preliminary trench 63, and a trench formed between any two adjacent sets of the sidewall structures 50 is a second preliminary trench 64;
in step S104, as shown in fig. 9 and 10, the sidewall structure 50 and the remaining hard mask layer 30 are removed, so that the first preliminary trench 63 forms a first trench 61 and the second preliminary trench 64 forms a second trench 62, the depth of the second trench 62 is greater than the depth of the first trench 61, and the remaining substrate 10 and the remaining dielectric structure layer 20 form a base.
In the method for manufacturing the semiconductor structure, firstly, a preparation substrate is provided, wherein the preparation substrate comprises a substrate, a dielectric structure layer, a hard mask layer and a plurality of first dielectric parts which are arranged at intervals, the substrate, the dielectric structure layer and the hard mask layer are sequentially overlapped, and the first dielectric parts are positioned on the partial surface of the hard mask layer, which is far away from the dielectric structure layer; then, forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the material of the side wall structures to the material of the first medium parts is different; then, removing part of the first dielectric part, taking the side wall structures as masks, and removing the rest of the first dielectric part, part of the hard mask layer, part of the dielectric structure layer and part of the substrate, wherein a groove formed between one group of side wall structures is a first preparation groove, and a groove formed between any two adjacent groups of side wall structures is a second preparation groove; and finally, removing the side wall structure and the rest of the hard mask layer to enable the first preparation groove to form a first groove and the second preparation groove to form a second groove, wherein the depth of the second groove is larger than that of the first groove, and the rest of the substrate and the rest of the dielectric structure layer form a substrate. According to the method, the first dielectric part and the side wall structures are formed, part of the first dielectric part is removed, so that a certain thickness of the first dielectric part remains between each group of side wall structures, when the side wall structures are used as masks, different etching heights are generated relative to the remaining first dielectric part and the exposed hard mask layer, therefore, grooves with different depths can be generated through one etching, the side walls of the grooves are smooth, and the problem that the performance of a device is affected due to the fact that double slopes exist in double groove isolation in the prior art is solved.
In practical application, since the etching selection ratio of the material of the side wall structure to the material of the first dielectric portion is different, a part of the first dielectric portion can be removed conveniently without affecting the side wall structure, so that the position of the remaining first dielectric portion becomes an opening position for forming the first trench, and the position of the exposed hard mask layer between any two adjacent sets of side wall structures becomes an opening position for forming the second trench.
In order to define the location where the first trench is subsequently formed, in another embodiment of the present application, a preparation substrate is provided, including: as shown in fig. 2, the above substrate 10 is provided; forming the dielectric structure layer 20 on the exposed surface of the substrate 10; forming the hard mask layer 30 and the first dielectric layer 41 stacked in order on the exposed surface of the dielectric structure layer 20; as shown in fig. 2 and 5, a portion of the first dielectric layer 41 is removed, a plurality of first dielectric portions 40 are formed on the remaining first dielectric layer 41 at intervals, and the hard mask layers 30 on both sides of the first dielectric portions 40 are exposed. After forming the plurality of spaced first dielectric portions, the opening position of the first trench may be determined according to the position of the first dielectric portions.
In another embodiment of the present application, forming the dielectric structure layer on the exposed surface of the substrate includes: as shown in fig. 2, a first oxide layer 201 is formed on the exposed surface of the substrate 10; an etch stopper layer 202 is formed on the exposed surface of the first oxide layer 201, and the first oxide layer 201 and the etch stopper layer 202 form the dielectric structure layer 20. The dielectric structure layer plays a role of an etching barrier layer in the subsequent process.
In practical applications, the dielectric structure layer may be a single cladding layer or a stack structure formed by a plurality of cladding layers, and in the above embodiment, the dielectric structure layer includes a first oxide layer and an etching barrier layer, which may be formed by chemical vapor deposition.
In order to conveniently and rapidly form the first dielectric portion, and enable the sidewall of the first dielectric portion to be even and smooth, thereby being beneficial to the subsequent preparation process and improving the device performance, in another embodiment of the application, a part of the first dielectric layer is removed, and the remaining first dielectric layer forms a plurality of first dielectric portions arranged at intervals, including: as shown in fig. 3, a mask structure layer 42 is formed on the exposed surface of the first dielectric layer 41; forming a patterned photoresist layer 43 on the exposed surface of the mask structure layer 42; as shown in fig. 3 and fig. 4, a portion of the mask structure layer 42 and a portion of the first dielectric layer 41 are removed through the patterned photoresist layer 43, so that a portion of the hard mask layer 30 is exposed; as shown in fig. 4 and 5, the remaining patterned photoresist layer 43 and the remaining mask structure layer 42 are removed to form a plurality of first dielectric portions 40 disposed at intervals.
In another embodiment of the present application, forming a mask structure layer on the exposed surface of the first dielectric layer includes: as shown in fig. 3, a second oxide layer 421 is formed on the exposed surface of the first dielectric layer 41; forming a carbon layer 422 on the exposed surface of the second oxide layer 421; a silicon oxynitride layer 423 is formed on the exposed surface of the carbon layer 422, and the second oxide layer 421, the carbon layer 422, and the silicon oxynitride layer 423 form the mask structure layer 42. The mask structure layer formed by the second oxide layer, the carbon layer and the silicon oxynitride layer has good etching resistance and good planarization property, and the silicon oxynitride layer is also called an dielectric reflection layer, so that the reflection phenomenon of a wide light source on the surface of the silicon oxynitride layer can be reduced, and the deformation or the size deviation of a photoresist pattern can be reduced.
Specifically, the second oxide layer, the carbon layer, and the silicon oxynitride layer may be formed by a chemical vapor deposition method, and in practical application, a plurality of mask layers and an anti-reflection layer may be deposited on the surface of the first dielectric layer, which may be selected by those skilled in the art according to practical requirements.
In order to form a flat and uniform photoresist layer, in another embodiment of the present application, forming a patterned photoresist layer on the exposed surface of the mask structure layer includes: spin-coating photoresist on the exposed surface of the mask structure layer to form a photoresist layer; patterning the photoresist layer to form the patterned photoresist layer.
In another embodiment of the present application, forming a plurality of sets of sidewall structures on two sides of a plurality of first dielectric portions includes: as shown in fig. 6, a second dielectric layer 51 is formed on the exposed surfaces of the first dielectric portion 40 and the hard mask layer 30; as shown in fig. 6 and 7, the second dielectric layer 51 on the surface of each of the first dielectric portions 40 away from the hard mask layer 30 and on the surface of each of the hard mask layers 30 away from the dielectric structure layer 20 is removed, and the second dielectric layer 51 on the sidewall of each of the first dielectric portions 40 forms the sidewall structure 50. The opening of the second groove can be defined through the side wall structures, and the position between any two adjacent groups of side wall structures is the opening position of the second groove.
In practical applications, atomic layer deposition or chemical vapor deposition may be used to form a second dielectric layer on the exposed surface of each of the first dielectric portions and the hard mask layer.
In order to better control the depth of the first trench, in another embodiment of the present application, the thickness of the first dielectric portion ranges from 800 a to 1200 a. And when the first dielectric part between the side wall structures is etched subsequently, the thickness of the remaining first dielectric part can directly influence the depth of the formed first groove.
In another embodiment of the present application, the material of the first dielectric portion includes one of silicon, silicon oxide, and silicon nitride. The material of the side wall structure may be, but not limited to, silicon oxide and silicon nitride, and the etching selectivity of the material of the first dielectric portion is different from that of the material of the side wall structure, so that the first dielectric portion can be removed without affecting the side wall structure.
According to another aspect of the present application, there is provided a semiconductor structure fabricated by any one of the above-mentioned fabrication methods, as shown in fig. 10, where the semiconductor structure includes a substrate, a plurality of first trenches 61, and a plurality of second trenches 62, and the substrate includes a substrate 10 and a dielectric structure layer 20 stacked in sequence; a plurality of first trenches 61 arranged at intervals, wherein the first trenches 61 penetrate through the dielectric structure layer 20 to the substrate 10; one second trench 62 is disposed between any two adjacent first trenches 61, the second trench 62 penetrates through the dielectric structure layer 20 to the substrate 10, and the depth of the second trench 62 is greater than the depth of the first trench 61.
The semiconductor structure comprises a substrate, a plurality of first grooves and a plurality of second grooves, wherein the substrate comprises a substrate and a dielectric structure layer which are sequentially stacked; a plurality of first trenches are arranged at intervals, and penetrate through the dielectric structure layer to the substrate; and one second groove is arranged between any two adjacent first grooves, the second groove penetrates through the dielectric structure layer to the substrate, and the depth of the second groove is larger than that of the first grooves. The semiconductor structure is provided with a plurality of grooves with different depths, and the side walls of the grooves are flat, so that the problem that the performance of a device is influenced due to the existence of double slopes in double groove isolation in the prior art is solved.
In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the technical solutions of the present application will be described in detail below with reference to specific embodiments.
Examples
The manufacturing method of the semiconductor structure in the embodiment comprises the following steps:
firstly, providing a preparation substrate, wherein the preparation substrate comprises a substrate, a dielectric structure layer, a hard mask layer and a plurality of first dielectric parts which are arranged at intervals, and the specific manufacturing process comprises the following steps: as shown in fig. 2, the above substrate 10 is provided; as shown in fig. 2, a first oxide layer 201 is formed on the exposed surface of the substrate 10; forming an etching barrier layer 202 on the exposed surface of the first oxide layer 201, wherein the first oxide layer 201 and the etching barrier layer 202 form the dielectric structure layer 20; forming the hard mask layer 30 and the first dielectric layer 41 stacked in order on the exposed surface of the dielectric structure layer 20; as shown in fig. 3, a second oxide layer 421 is formed on the exposed surface of the first dielectric layer 41; forming a carbon layer 422 on the exposed surface of the second oxide layer 421; forming a silicon oxynitride layer 423 on an exposed surface of the carbon layer 422, wherein the second oxide layer 421, the carbon layer 422, and the silicon oxynitride layer 423 form the mask structure layer 42; forming a patterned photoresist layer 43 on the exposed surface of the mask structure layer 42; as shown in fig. 3 and fig. 4, a portion of the mask structure layer 42 and a portion of the first dielectric layer 41 are removed through the patterned photoresist layer 43, so that a portion of the hard mask layer 30 is exposed; as shown in fig. 5, the remaining patterned photoresist layer 43 and the remaining mask structure layer 42 are removed to form a plurality of first dielectric portions 40 disposed at intervals.
In practical applications, the dielectric structure layer 20 may be a single cladding layer or a stack structure formed by a plurality of cladding layers, and in the embodiment, the dielectric structure layer includes a first oxide layer and an etching stop layer, which may be formed by chemical vapor deposition. The thickness range of the first dielectric portion is 800 a-1200 a, when the first dielectric portion between the side wall structures is etched subsequently, the thickness of the remaining first dielectric portion can directly influence the depth of the formed first groove, the material of the first dielectric portion comprises one of silicon, silicon oxide and silicon nitride, and the etching selection ratio of the material of the first dielectric portion is different from that of the material of the side wall structures, so that the first dielectric portion can be removed under the condition that the side wall structures are not influenced. The mask structure layer formed by the second oxide layer, the carbon layer and the silicon oxynitride layer has good etching resistance and good planarization characteristics, and the silicon oxynitride layer is also called an dielectric reflection layer, so that the reflection phenomenon of a wide light source on the surface of the silicon oxynitride layer can be reduced, the phenomenon of deformation or dimensional deviation of a photoresist pattern can be reduced, and a person skilled in the art can select materials according to actual requirements.
Then, forming a plurality of groups of side wall structures on two sides of the first dielectric parts, including: as shown in fig. 6, a second dielectric layer 51 is formed on the exposed surfaces of the first dielectric portion 40 and the hard mask layer 30; as shown in fig. 6 and 7, the second dielectric layer 51 on the surface of each of the first dielectric portions 40 away from the hard mask layer 30 and on the surface of each of the hard mask layers 30 away from the dielectric structure layer 20 is removed, and the second dielectric layer 51 on the sidewall of each of the first dielectric portions 40 forms the sidewall structure 50. The opening of the second groove can be defined through the side wall structures, and the position between any two adjacent groups of side wall structures is the opening position of the second groove.
Then, as shown in fig. 8, a part of the first dielectric portion 40 is removed, and the sidewall structures 50 are used as masks, and as shown in fig. 8 and 9, the remaining first dielectric portion 40, part of the hard mask layer 30, part of the dielectric structure layer 20 and part of the substrate 10 are removed, wherein a trench formed between one set of the sidewall structures 50 is a first preliminary trench 63, and a trench formed between any two adjacent sets of the sidewall structures 50 is a second preliminary trench 64;
finally, as shown in fig. 9 and 10, the sidewall structure 50 and the remaining hard mask layer 30 are removed, so that the first preliminary trench 63 forms a first trench 61 and the second preliminary trench 64 forms a second trench 62, and the depth of the second trench 62 is greater than the depth of the first trench 61, and the remaining substrate 10 and the remaining dielectric structure layer 20 form a base.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing the semiconductor structure, firstly, a preparation substrate is provided, the preparation substrate comprises a substrate, a dielectric structure layer, a hard mask layer and a plurality of first dielectric parts which are arranged at intervals, wherein the substrate, the dielectric structure layer and the hard mask layer are sequentially overlapped, and the first dielectric parts are positioned on part of the surface of the hard mask layer, which is far away from the dielectric structure layer; then, forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the material of the side wall structures to the material of the first medium parts is different; then, removing part of the first dielectric part, taking the side wall structures as masks, and removing the rest of the first dielectric part, part of the hard mask layer, part of the dielectric structure layer and part of the substrate, wherein a groove formed between one group of side wall structures is a first preparation groove, and a groove formed between any two adjacent groups of side wall structures is a second preparation groove; and finally, removing the side wall structure and the rest of the hard mask layer to enable the first preparation groove to form a first groove and the second preparation groove to form a second groove, wherein the depth of the second groove is larger than that of the first groove, and the rest of the substrate and the rest of the dielectric structure layer form a substrate. According to the method, the first dielectric part and the side wall structures are formed, part of the first dielectric part is removed, so that a certain thickness of the first dielectric part remains between each group of side wall structures, when the side wall structures are used as masks, different etching heights are generated relative to the remaining first dielectric part and the exposed hard mask layer, therefore, grooves with different depths can be generated through one etching, the side walls of the grooves are smooth, and the problem that the performance of a device is affected due to the fact that double slopes exist in double groove isolation in the prior art is solved.
2) The semiconductor structure comprises a substrate, a plurality of first grooves and a plurality of second grooves, wherein the substrate comprises a substrate and a dielectric structure layer which are sequentially stacked; a plurality of first trenches are arranged at intervals, and penetrate through the dielectric structure layer to the substrate; and one second groove is arranged between any two adjacent first grooves, the second groove penetrates through the dielectric structure layer to the substrate, and the depth of the second groove is larger than that of the first grooves. The semiconductor structure is provided with a plurality of grooves with different depths, and the side walls of the grooves are flat, so that the problem that the performance of a device is influenced due to the existence of double slopes in double groove isolation in the prior art is solved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a preparation substrate, wherein the preparation substrate comprises a substrate, a dielectric structure layer and a hard mask layer which are sequentially stacked, and the preparation substrate further comprises a plurality of first dielectric parts which are arranged at intervals, and the first dielectric parts are positioned on part of the surface, far away from the dielectric structure layer, of the hard mask layer;
forming a group of side wall structures on two sides of each first medium part, wherein the etching selection ratio of the materials of the side wall structures to the materials of the first medium parts is different;
removing part of the first dielectric part, taking the side wall structures as masks, and removing the rest of the first dielectric part, part of the hard mask layer, part of the dielectric structure layer and part of the substrate, wherein grooves formed between one group of side wall structures are first preparation grooves, and grooves formed between any two adjacent groups of side wall structures are second preparation grooves;
and removing the side wall structure and the residual hard mask layer, so that the first preparation groove forms a first groove and the second preparation groove forms a second groove, the depth of the second groove is larger than that of the first groove, and the residual substrate and the residual dielectric structure layer form a substrate.
2. The method of claim 1, wherein forming a plurality of sets of sidewall structures on both sides of a plurality of the first dielectric portions comprises:
forming a second dielectric layer on the exposed surface of each first dielectric part and the hard mask layer;
and removing the second dielectric layers on the surfaces of the first dielectric parts far away from the hard mask layer and the surfaces of the hard mask layer far away from the dielectric structure layer, wherein the second dielectric layers on the side walls of the first dielectric parts form the side wall structure.
3. The method of claim 1, wherein providing a preliminary substrate comprises:
providing the substrate;
forming the dielectric structure layer on the exposed surface of the substrate;
forming the hard mask layer and the first dielectric layer which are sequentially overlapped on the exposed surface of the dielectric structure layer;
and removing part of the first dielectric layer, wherein the rest first dielectric layers form a plurality of first dielectric parts which are arranged at intervals, and the hard mask layers on two sides of the first dielectric parts are exposed.
4. A method according to claim 3, wherein forming the dielectric structure layer on the exposed surface of the substrate comprises:
forming a first oxide layer on the exposed surface of the substrate;
and forming an etching barrier layer on the exposed surface of the first oxide layer, wherein the first oxide layer and the etching barrier layer form the dielectric structure layer.
5. The method of claim 3, wherein removing a portion of the first dielectric layer, the remaining first dielectric layer forming a plurality of spaced apart first dielectric portions, comprises:
forming a mask structure layer on the exposed surface of the first dielectric layer;
forming a patterned photoresist layer on the exposed surface of the mask structure layer;
removing part of the mask structure layer and part of the first dielectric layer through the patterned photoresist layer, so that part of the hard mask layer is exposed;
and removing the residual patterned photoresist layer and the residual mask structure layer to form a plurality of first medium parts which are arranged at intervals.
6. The method of claim 5, wherein forming a masking structure layer on the exposed surface of the first dielectric layer comprises:
forming a second oxide layer on the exposed surface of the first dielectric layer;
forming a carbon layer on the exposed surface of the second oxide layer;
and forming a silicon oxynitride layer on the exposed surface of the carbon layer, wherein the second oxide layer, the carbon layer and the silicon oxynitride layer form the mask structure layer.
7. The method of claim 5, wherein forming a patterned photoresist layer on the exposed surface of the mask structure layer comprises:
spin-coating photoresist on the exposed surface of the mask structure layer to form a photoresist layer;
and patterning the photoresist layer to form the patterned photoresist layer.
8. The method of any one of claims 1 to 7, wherein the first dielectric portion has a thickness in a range of 800 a to 1200 a.
9. The method of any of claims 1 to 7, wherein the material of the first dielectric portion comprises one of silicon, silicon oxide, and silicon nitride.
10. A semiconductor structure fabricated by the method of any of claims 1 to 9, the semiconductor structure comprising:
the substrate comprises a substrate and a dielectric structure layer which are sequentially overlapped;
the first grooves penetrate through the dielectric structure layer to the substrate;
and one second groove is arranged between any two adjacent first grooves, the second grooves penetrate through the dielectric structure layer to the substrate, and the depth of the second grooves is larger than that of the first grooves.
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Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000021259A (en) * 1998-09-28 2000-04-25 윤종용 Method of fabricating field effect transistor with trench isolation
CN101127319A (en) * 2006-08-15 2008-02-20 上海华虹Nec电子有限公司 Method for reducing STI edge current leakage
CN101599419A (en) * 2008-06-03 2009-12-09 中芯国际集成电路制造(北京)有限公司 The formation method of groove
JP2013089801A (en) * 2011-10-19 2013-05-13 Elpida Memory Inc Method of manufacturing semiconductor device
CN103943549A (en) * 2014-04-28 2014-07-23 上海华力微电子有限公司 Removing method of shallow groove oxide hole and floating gate polycrystalline silicon concave point
WO2017052559A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ild)
CN107799542A (en) * 2017-10-24 2018-03-13 武汉新芯集成电路制造有限公司 A kind of deep trench isolation method of cmos image sensor
CN110349906A (en) * 2018-04-03 2019-10-18 长鑫存储技术有限公司 A kind of forming method of autoregistration groove
CN112447603A (en) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 Method for forming semiconductor memory
US11069559B1 (en) * 2020-05-20 2021-07-20 Nexchip Semiconductor Corporation Semiconductor structure and method of forming same
CN113224099A (en) * 2021-04-28 2021-08-06 华虹半导体(无锡)有限公司 Method for forming deep groove isolation structure of CMOS optical sensor
CN115346911A (en) * 2022-08-31 2022-11-15 上海华力微电子有限公司 Method for optimizing deeper groove etching morphology in double-groove process based on light transmittance
CN115985773A (en) * 2023-02-14 2023-04-18 苏州聚谦半导体有限公司 Manufacturing method of self-aligned trench gate and source region contact IGBT
CN116013850A (en) * 2022-11-09 2023-04-25 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN116169091A (en) * 2021-11-24 2023-05-26 长鑫存储技术有限公司 Preparation method of semiconductor structure, semiconductor structure and semiconductor memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12046615B2 (en) * 2020-05-22 2024-07-23 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including deep trench isolation structure comprising dielectric structure and copper structure and method of making the same

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000021259A (en) * 1998-09-28 2000-04-25 윤종용 Method of fabricating field effect transistor with trench isolation
CN101127319A (en) * 2006-08-15 2008-02-20 上海华虹Nec电子有限公司 Method for reducing STI edge current leakage
CN101599419A (en) * 2008-06-03 2009-12-09 中芯国际集成电路制造(北京)有限公司 The formation method of groove
JP2013089801A (en) * 2011-10-19 2013-05-13 Elpida Memory Inc Method of manufacturing semiconductor device
CN103943549A (en) * 2014-04-28 2014-07-23 上海华力微电子有限公司 Removing method of shallow groove oxide hole and floating gate polycrystalline silicon concave point
WO2017052559A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ild)
CN107799542A (en) * 2017-10-24 2018-03-13 武汉新芯集成电路制造有限公司 A kind of deep trench isolation method of cmos image sensor
CN113488430A (en) * 2018-04-03 2021-10-08 长鑫存储技术有限公司 Method for forming self-aligned trench
CN110349906A (en) * 2018-04-03 2019-10-18 长鑫存储技术有限公司 A kind of forming method of autoregistration groove
CN112447603A (en) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 Method for forming semiconductor memory
US11069559B1 (en) * 2020-05-20 2021-07-20 Nexchip Semiconductor Corporation Semiconductor structure and method of forming same
CN113224099A (en) * 2021-04-28 2021-08-06 华虹半导体(无锡)有限公司 Method for forming deep groove isolation structure of CMOS optical sensor
CN116169091A (en) * 2021-11-24 2023-05-26 长鑫存储技术有限公司 Preparation method of semiconductor structure, semiconductor structure and semiconductor memory
CN115346911A (en) * 2022-08-31 2022-11-15 上海华力微电子有限公司 Method for optimizing deeper groove etching morphology in double-groove process based on light transmittance
CN116013850A (en) * 2022-11-09 2023-04-25 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN115985773A (en) * 2023-02-14 2023-04-18 苏州聚谦半导体有限公司 Manufacturing method of self-aligned trench gate and source region contact IGBT

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