WO2017052559A1

WO2017052559A1 - Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ild)

Info

Publication number: WO2017052559A1
Application number: PCT/US2015/052003
Authority: WO
Inventors: Kanwaljit SINGH; Kevin Lin; Jasmeet S. CHAWLA; Richard Schenker
Original assignee: Intel Corporation
Priority date: 2015-09-24
Filing date: 2015-09-24
Publication date: 2017-03-30
Also published as: TWI720007B; TW201721742A

Abstract

Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. Other embodiments may be described and/or claimed.

Description

METHODS, APPARATUSES AND SYSTEMS FOR INTEGRATED CIRCUIT STRUCTURES WITH A REPLACEMENT INTER-LAYER DIELECTRIC (ILD)

Field

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to integrated circuit structures with a replacement inter-layer dielectric (ILD).

Background

In interconnect layers of integrated circuits, a low-K dielectric is typically used to minimize line-to-line capacitance and layer-to-layer capacitance. However, low-K dielectrics have high porosity, which can cause problems during patterning of the interconnect layers.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements.

Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 schematically illustrates a top view of an example die in wafer form and in singulated form, in accordance with some embodiments.

FIG. 2 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments.

FIG. 3 is a flow diagram that illustrates a method for forming an IC structure including a replacement inter-layer dielectric (ILD) layer, in accordance with some embodiments.

FIGS. 4A-4G schematically illustrate a cross-section side view of an IC structure during various stages of the method of FIG. 4, in accordance with some embodiments.

FIG. 5 is a flow diagram that illustrates a method for forming an IC structure including a replacement inter-layer dielectric (ILD) layer and using a dual metallization process, in accordance with some embodiments.

FIGS. 6A-6L schematically illustrate a cross-section side view of an IC structure during various stages of the method of FIG. 4, in accordance with some embodiments. FIG. 7 is a flow diagram that illustrates a method for forming an IC structure including a replacement inter-layer dielectric (ILD) layer and using multiple hard mask materials for shorting mitigation, in accordance with some embodiments.

FIGS. 8A-8R schematically illustrate a cross-section side view of an

IC structure during various stages of the method of FIG. 4, in accordance with some embodiments.

FIG. 9 is a flow diagram that illustrates another method for forming an IC structure including a replacement inter-layer dielectric (ILD) layer and using multiple hard mask materials for shorting mitigation, in accordance with some embodiments.

FIGS. 10A-10R schematically illustrate a cross-section side view of an IC structure during various stages of the method of FIG. 4, in accordance with some embodiments.

FIG. 11 schematically illustrates an example system that may include a transistor electrode assembly as described herein, in accordance with some embodiments.

Detailed Description

Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. The second ILD layer may have a higher porosity and/or a lower dielectric constant than the first ILD layer.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The description may use perspective-based descriptions such as top/bottom, side, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The description may use the phrases "in an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

FIG. 1 schematically illustrates a top view of an example die 102 in wafer form 10 and in singulated form 100, in accordance with some embodiments. In some embodiments, the die 102 may be one of a plurality of dies (e.g., dies 102, 103a, 103b) of a wafer 1 1 composed of semiconductor material such as, for example, silicon or other suitable material. The plurality of dies may be formed on a surface of the wafer 1 1 . Each of the dies may be a repeating unit of a semiconductor product that includes one or more IC structures (e.g., IC structure 400, 600, 800, and/or 1000, and/or an IC structure formed using method 300, 500, 700, and/or 900) as described herein. For example, the die 102 may include circuitry having transistor structures 104 such as, for example, one or more channel bodies (e.g., fin structures, nanowires, planar bodies, etc.) that provide a channel pathway for mobile charge carriers of one or more transistor devices or source/drain regions. Transistor electrode assemblies (e.g., terminal contacts) may be formed on and coupled with the one or more transistor structures 104 to route electrical energy to or from the transistor structures 104. For example, terminal contacts may be electrically coupled with a channel body to provide a gate electrode for delivery of a threshold voltage and/or a source/drain current to provide mobile charge carriers for operation of a transistor device. Although the transistor structures 104 are depicted in rows that traverse a substantial portion of the die 102 in FIG. 1 for the sake of simplicity, it is to be understood that the transistor structures 104 may be configured in any of a wide variety of other suitable arrangements on the die 102 in other embodiments, including, for example, vertical and horizontal features having much smaller dimensions than depicted.

After a fabrication process of the semiconductor product embodied in the dies is complete, the wafer 1 1 may undergo a singulation process in which each of the dies (e.g., die 102) is separated from one another to provide discrete "chips" of the semiconductor product. The wafer 1 1 may be any of a variety of sizes. In some embodiments, the wafer 1 1 has a diameter ranging from about 25.4 mm to about 450 mm. The wafer 1 1 may include other sizes and/or other shapes in other embodiments. According to various embodiments, the transistor structures 104 may be disposed on a semiconductor substrate in wafer form 10 or singulated form 100. The transistor structures 104 described herein may be incorporated in a die 102 for logic or memory, or combinations thereof. In some embodiments, the transistor structures 104 may be part of a system-on-chip (SoC) assembly.

FIG. 2 schematically illustrates a cross-section side view of an IC assembly 200, in accordance with some embodiments. In some embodiments, the IC assembly 200 may include one or more dies (hereinafter "die 102") electrically and/or physically coupled with a package substrate 121 . In some embodiments, the package substrate 121 may be electrically coupled with a circuit board 122, as can be seen. In some embodiments, an IC assembly 200 may include one or more of the die 102, package substrate 121 and/or circuit board 122, according to various embodiments. Embodiments described herein for an IC structure may be implemented in any suitable IC device according to various embodiments.

The die 102 may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like used in connection with forming CMOS devices. In some embodiments, the die 102 may be, include, or be a part of a processor, memory, SoC or ASIC. In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of the die 102 and/or die- level interconnect structures 106.

The die 102 can be attached to the package substrate 121 according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate 121 in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, S1 , of the die 102 including circuitry is attached to a surface of the package substrate 121 using die-level interconnect structures 106 such as bumps, pillars, or other suitable structures that may also electrically couple the die 102 with the package substrate 121 . The active side S1 of the die 102 may include active devices such as, for example, transistor devices. An inactive side, S2, may be disposed opposite to the active side S1 , as can be seen. The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter "device layer 102b") and one or more interconnect layers (hereinafter "interconnect layer 102c"). The semiconductor substrate 102a may be substantially composed of a bulk semiconductor material such as, for example silicon, in some embodiments. The device layer 102b may represent a region where active devices such as transistor devices are formed on the semiconductor substrate. The device layer 102b may include, for example, transistor structures such as channel bodies and/or source/drain regions of transistor devices. The interconnect layer 102c may include interconnect structures that are configured to route electrical signals to or from the active devices in the device layer 102b. For example, the interconnect layer 102c may include horizontal lines (e.g., trenches) and/or vertical plugs (e.g., vias) or other suitable features to provide electrical routing and/or contacts. In various embodiments, one or more layers of the interconnect layer 102c may include a replacement ILD as described further below.

In some embodiments, the die-level interconnect structures 106 may be electrically coupled with the interconnect layer 102c and configured to route electrical signals between the die 102 and other electrical devices. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die 102.

In some embodiments, the package substrate 121 is an epoxy- based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate 121 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The package substrate 121 may include electrical routing features configured to route electrical signals to or from the die 102. The electrical routing features may include, for example, pads or traces (not shown) disposed on one or more surfaces of the package substrate 121 and/or internal routing features (not shown) such as, for example, trenches, vias or other interconnect structures to route electrical signals through the package substrate 121 . For example, in some embodiments, the package substrate 121 may include electrical routing features such as pads (not shown) configured to receive the respective die-level interconnect structures 106 of the die 102.

The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board 122 may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR-4), FR-1 , cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures (not shown) such as traces, trenches, or vias may be formed through the electrically insulating layers to route the electrical signals of the die 102 through the circuit board 122. The circuit board 122 may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board 122 is a

motherboard (e.g., motherboard 1 102 of FIG. 1 1 ).

Package-level interconnects such as, for example, solder balls 1 12 may be coupled to one or more pads (hereinafter "pads 1 10") on the package substrate 121 and/or on the circuit board 122 to form corresponding solder joints that are configured to further route the electrical signals between the package substrate 121 and the circuit board 122. The pads 1 10 may be composed of any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple the package substrate 121 with the circuit board 122 may be used in other embodiments.

The IC assembly 200 may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die 102 and other components of the IC assembly 200 may be used in some embodiments.

FIG. 3 is a flow chart to illustrate a method 300 for forming an IC structure with a replacement ILD layer in accordance with various embodiments. FIGS. 4A, 4B, 4C, 4D, 4E, 4F, and 4G schematically illustrate a cross-sectional side view of an IC structure 400 at various stages of the method 300, in

accordance with various embodiments. Accordingly, the method 300 will be described below with reference to FIGS. 4A-4G. Similar fabrication principles to those described herein may be used to form IC structures with other

configurations than that shown in FIGS. 4A-4G. In some embodiments, the IC structure 400 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., trenches or vias).

At block 302, the method 300 may include forming a first ILD layer on an underlying layer. The underlying layer may be any suitable IC layer, such as a device layer, another interconnect layer, or a semiconductor substrate. The first ILD layer may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Additionally, the first ILD layer may include any suitable dielectric material or combination of dielectric materials, including one or more high-K or low-K materials.

For example, the first ILD layer may include silicon oxide (Si0₂), silicon oxynitride (SiO_xN_y), silicon nitride (Si_xN_y) aluminum oxide (AI₂O₃), hafnium oxide (Hf0₂), hafnium aluminum oxide (HfAl_xO_y), hafnium silicon oxide (HfSi_xO_y), zirconium oxide (Zr0₂), zirconium silicon oxide (ZrSi_xO_y), lanthanum oxide

(La₂03), yttrium oxide (Y₂O₃), lanthanum aluminum oxide (LaAl_xO_y), tantalum oxide (Ta₂Os), titanium oxide (Ti0₂), barium strontium titanium oxide (BaSrTi_xO_y), barium titanium oxide (BaTi_xO_y), strontium titanium oxide (SrTi_xO_y), lead scandium tantalum oxide (PbSc_xTa_yO_z), or lead zinc niobate (PbZn_xNb_yO_z), carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements. In some embodiments, an annealing process may be carried out on the first ILD layer to improve its quality when a high-k material is used. Other materials may be used in other embodiments for the first ILD layer.

At block 304, the method 300 may include forming a sacrificial layer on the first ILD layer. In some embodiments, the sacrificial layer may include any suitable material that is wet cleanable, such as a dielectric material or a hard mask material. For example, the sacrificial layer may include titanium nitride (TiN) or amorphous silicon (a-Si).

At block 306, the method 300 may include forming a hard mask layer on the sacrificial layer. The hard mask layer may be a patternable material to allow portions of the hard mask layer to be selectively removed. For example, the hard mask layer may include a dielectric material (such as one or more oxides, nitrides, carbides or mixed oxynitrides, carbon-doped oxides, nitrogen doped carbides etc.) and/or one or more transition metal compounds (such as oxides or nitrides of titanium (Ti), zirconium (Zr), hafnium (Hf) etc).

FIG. 4A illustrates the IC structure 400 subsequent to block 306 of method 300. IC structure 400 includes a first ILD layer 402 formed on an underlying layer 404, a sacrificial material 406 formed on the first ILD layer 402, and a hard mask layer 408 formed on the sacrificial material.

At block 308, the method 300 may include forming trench openings in the hard mask layer and sacrificial layer. The trench openings may extend through the sacrificial layer, to the first ILD layer. The trench openings may be formed by removing portions of the hard mask layer and sacrificial material. In some embodiments, portions of the hard mask layer may first be removed (e.g., by a selective removal process), and then the portions of the sacrificial material disposed below the removed portions of the hard mask layer may be removed. The portions of the sacrificial material may be removed, for example, by an etch process. The etch process may use an etchant that is selective for the sacrificial material compared with the first ILD layer. That is, the first ILD layer may be used as an etch stop layer and may not be removed by the etch process.

FIG. 4B illustrates the IC structure 400 with openings 410a and 410b in the hard mask layer 408 and sacrificial material 406. The openings 410a and 410b in the sacrificial material 406 may correspond to trench openings that will form trenches to route electrical signals horizontally in the IC structure 400.

Accordingly, the openings 410a and 410b may extend horizontally out of the plane shown in FIG. 4B (e.g., into the page and/or out of the page).

At block 310, the method 300 may further include patterning via openings in the first ILD layer below respective portions of the trench openings. Portions of the first ILD layer may be removed to form the via openings. The via openings may extend to the underlying layer to enable vias formed in the via openings (further described below) to conductively couple the corresponding trench to the underlying layer.

FIG. 4C illustrates the IC structure 400 subsequent to block 310 of the method 300. The portion of the first ILD layer in opening 410a has been removed, such that opening 410a extends to the underlying layer 404. As further discussed below, a conductive material may be formed in the opening 410a to form a via. The via may be disposed under only a portion of the corresponding trench, and thus the portion of opening 410a in the first ILD layer 402 (e.g., the via opening) may extend only a small amount in the horizontal direction out of the plane shown in FIG. 4C (e.g., significantly less than the horizontal extension of the portion of opening 410a in the sacrificial layer 406 (e.g., the trench opening)).

At block 312, the method 300 may include forming a metal in the trench openings and the via openings. The metal may be formed in the trench openings and via openings by any suitable deposition technique, including a conformal and/or selective deposition process. For example, the metal may be formed by CVD, ALD, PVD, electroless, electroplating, or suitable combinations of these deposition techniques.

The metal may include any suitable metal. For example, in some embodiments, the metal may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof. In some embodiments, the metal layer may include a metal nitride such as, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof. In some embodiments, the metal may include a metal silicide such as, for example, titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof. In some embodiments, the metal layer may include a metal silicon nitride such as, for example, titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof. In some embodiments, the metal layer may include a metal carbide such as, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AIC), or combinations thereof. In some embodiments, the metal layer may include a metal carbon nitride such as, for example, tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. In some embodiments, the metal layer may include a conductive metal oxide (e.g., ruthenium oxide).

In some embodiments, the top surface of the IC structure may be polished after forming the metal in the trench openings and the via openings. The polishing may remove the remaining portions of the hard mask layer and any excess metal disposed above the trench openings. The polishing process may include, for example, chemical mechanical polishing using a surry solution designed to remove the metals used in the IC structure.

FIG. 4D illustrates the IC structure 400 subsequent to block 312, and shows a metal 412 disposed in the openings 410a-b. In the plane shown in FIG.

4D, the metal 412 forms a trench 414b in the opening 410b, and a trench 414a and a via 416 in the opening 410a. A top surface of the IC structure 400 has been polished to remove the remaining portions of the hard mask layer 408 and any excess metal 412 above the openings 410a-b.

At block 314, the method 300 may include removing the sacrificial layer. The sacrificial layer may be removed by any suitable process, such as wet cleaning.

FIG. 4E illustrates the IC structure 400 subsequent to block 314, and shows that the sacrificial layer 404 has been removed (e.g., between the trenches 414a-b).

At block 316, the method 300 may include forming a second ILD layer on the first ILD layer (e.g., between the trenches formed by the metal). The second ILD layer may have a higher porosity and/or a lower density than the first ILD layer. The second ILD layer may additionally or alternatively have a lower dielectric constant (K) than the first ILD layer. For example, in some

embodiments, the second ILD layer may include a porous, low-K dielectric material, such as a carbon-doped oxide (CDO) of silicon with a controllable porosity, e.g., 50% porosity. In some embodiments, the second ILD layer may have the same material composition as the first ILD layer, but may have a higher porosity and/or a lower density. In other embodiments, the second ILD layer may be a different material from the first ILD layer.

The second ILD layer may be formed on the first ILD layer by any suitable process, such as a spin-on process or a deposition process such as chemical vapor deposition (CVD). In some embodiments, voiding caused by the CVD process may provide a lower K for the resulting second ILD layer. In some embodiments, the openings between the trenches may be filled with an overburden of the ILD material to form the second ILD layer, and then excess ILD material may be polished or recessed to the proper level (e.g., to the height of the trenches).

The first ILD layer may provide structural support for the trenches, while the second ILD layer may prevent/reduce capacitance between the trenches.

FIG. 4F illustrates the IC structure 400 subsequent to block 316. A second ILD layer 418 is disposed on the first ILD layer 402 (e.g., between the trenches 414a-b). The trenches 414a-b may be disposed on the first ILD layer 402 (e.g., except when a via is disposed below the trench). As shown in the plane of FIG. 4F, the trench 414b is disposed on the first ILD layer 402, and the trench 414a is disposed on the via 416.

In some embodiments, at block 318, the method 300 may further include forming one or more additional layers on the second ILD layer and/or trenches. For example, an etch stop layer may be formed on the second ILD layer and/or trenches. Additional layers, such as another interconnect layer, may be formed on the etch stop layer.

FIG. 4G illustrates the IC structure 400 with an etch stop layer 420 disposed on the second ILD layer 418 and trenches 414a-b.

In various embodiments, the process 300 and/or IC structure 400 may provide one or more advantages over prior processes and/or IC structures. In some embodiments, the sacrificial material (e.g., the material of sacrificial layer 406) may have better pattern fidelity than the material of the second ILD layer (e.g., second ILD layer 418). For example, the sacrificial material may be denser than the material of the second ILD layer to enable better pattern fidelity.

Additionally, or alternatively, the process 300 and/or IC structure 400 may not use pore stuffing to stuff the pores of the second ILD layer to preserve the structure of the second ILD layer during patterning and metallization since the second ILD layer is formed after patterning and metallization.

Additionally, or alternatively, having the first ILD layer disposed below the second ILD layer and/or the trenches may be preferable to using a single sacrificial material in place of the sacrificial layer 406 and first ILD layer 402, removing the sacrificial material after forming the trenches and vias, and then backfilling under the trenches and between the trenches with a replacement ILD. For example, the first ILD layer may provide increased structural support for the trenches compared with having the second ILD material under the trenches, may prevent the need to etch and backfill under the trenches which may damage the trenches, and/or may provide an etch stop for formation of the trench openings (e.g., as described with reference to block 308) to enable consistent and controlled depth of the trenches.

In various embodiments, the techniques for using a sacrificial material on a first ILD layer for patterning and metallization of interconnect structures, and then replacing the sacrificial material with a second ILD layer (e.g., as described above with reference to FIGS. 3 and 4) may be combined with other techniques for forming interconnect layers. For example, such techniques may be combined with a dual metallization process in which alternating trenches are patterned and metalized separately and/or with a process that uses multiple hard mask materials on the trenches and/or spacers (e.g., to mitigate shorting between the trenches).

FIG. 5 is a flow chart to illustrate a method 500 for forming an IC structure with a replacement ILD layer using a dual metallization process in which alternating trenches are patterned and metalized separately, in accordance with various embodiments. FIGS. 6A-6L schematically illustrate a cross-sectional side view of an IC structure 600 at various stages of the method 500, in accordance with various embodiments. Accordingly, the method 500 will be described below with reference to FIGS. 6A-6L. For ease of illustration, not every element is labeled with a reference number in every figure of FIGS. 6A-6L.

Similar fabrication principles to those described herein may be used to form IC structures with other configurations than that shown in FIGS. 6A-6L. In some embodiments, the IC structure 600 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., a trench or via).

At block 502, the method 500 may include providing an IC structure including a first ILD layer disposed on an underlying layer, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer. Such an IC structure may be formed, for example, according to blocks 302, 304, and 306 of method 300 as discussed above. FIG. 6A illustrates the IC structure 600 including a first ILD layer 602 formed on an underlying layer 604, a sacrificial layer 606 formed on the first ILD layer 602, and a hard mask layer 608 formed on the sacrificial material.

At block 504, the method 500 may include etching portions of the hard mask layer to form openings in the hard mask layer.

FIG. 6B illustrates the IC structure 600 with portions of the hard mask layer 608 removed by etching to form openings 610a-c.

At block 506, the method 500 may include forming spacers on the sides of the openings in the hard mask layer. The spacers may be coupled with the sidewalls of the hard mask layer in the openings. The spacers may be any suitable etch resistant material that has the required etch selectivity, such as a transition metal oxide or nitride or a dielectric material such as SiN.

FIG. 6C illustrates the IC structure 600 with spacers 612 disposed in the sides of the openings 610a-c.

At block 508, the method 500 may include forming a first set of trench openings in the sacrificial layer for a first set of trenches. The trench openings may be formed, for example, by removing the portion of the sacrificial material between spacers of a given opening. Thus, between the spacers, the openings may be extended down to the first ILD layer.

FIG. 6D illustrates the IC structure 600 with the openings 61 Oa-c extending, between the spacers 612 on the sides of each opening 61 Oa-c, down to the first ILD layer 602.

At block 510, the method 500 may include forming via openings in the first ILD layer below one or more of the first set of trench openings. The via openings may be referred to as a first set of via openings.

FIG. 6E illustrates the IC structure 600 with the portion of the first ILD layer 602 in the opening 610c removed to form a via opening.

At block 512, the method 500 may include forming a metal (e.g., metallization) in the first set of trench openings and the first set of via openings. In some embodiments, a top surface of the IC structure may be polished subsequent to forming the metal. The spacers and/or portions of the hard mask layer may remain after the polishing.

FIG. 6F illustrates the IC structure 600 with a metal 614 formed in the openings 61 Oa-c. At block 514, the method 500 may include forming a second set of trench openings in the sacrificial layer for a second set of trenches. The second set of trench openings may be formed, for example, by removing the remaining portions of the hard mask layer and removing the portions of the sacrificial layer below the remaining portions of the hard mask layer. Accordingly, the second set of trench openings may alternate with the first set of trench openings.

FIG. 6G illustrates the IC structure 600 with openings 616a-d in the sacrificial layer 606.

At block 516, the method 500 may include forming via openings in the first ILD layer below one or more of the second set of trench openings. The via openings may be referred to as a second set of via openings.

FIG. 6H illustrates the IC structure 600 with the portion of the first ILD layer 602 in the opening 616b removed to form a via opening.

At block 518, the method 500 may include forming a metal (e.g., metallization) in the second set of trench openings and the second set of via openings. In some embodiments, a top surface of the IC structure may be polished subsequent to forming the metal. The polishing may remove the spacers and the metal that was formed between the spacers at block 512.

FIG. 6I illustrates the IC structure 600 subsequent to block 518, showing the metal 614 formed in the openings 616a-d. The spacers 612 have been removed (e.g., by polishing).

At block 520, the method 500 may include removing the remaining sacrificial material (e.g., the sacrificial material that was disposed below the spacers). The removal of the sacrificial material may leave openings between the trenches. FIG. 6J illustrates the IC structure 600 with the sacrificial layer 606 removed and showing openings between trenches.

At block 522, the method 500 may include forming a second ILD layer on the first ILD layer between the trenches. FIG. 6K illustrates the IC structure 600 including a second ILD layer 618 between the trenches.

At block 524, the method 500 may include forming an etch stop layer on the second ILD layer and/or the trenches. FIG. 6L illustrates the IC structure 600 including an etch stop layer 620 on the second ILD layer 618.

FIGS. 7A and 7B provide a flow chart to illustrate a method 700 for forming an IC structure with a replacement ILD layer using a process that uses multiple hard mask materials on the trenches and/or spacers, in accordance with various embodiments. The method 700 also uses a dual metallization process similar to the dual metallization process of method 500. FIGS. 8A-8R

schematically illustrate a cross-sectional side view of an IC structure 800 at various stages of the method 700, in accordance with various embodiments. Accordingly, the method 700 will be described below with reference to FIGS. 8A-8R. For ease of illustration, not every element is labeled with a reference number in every figure of FIGS. 8A-8R.

Similar fabrication principles to those described herein may be used to form IC structures with other configurations than that shown in FIGS. 8A-8R. In some embodiments, the IC structure 800 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., trenches or vias).

In various embodiments, blocks 702, 704, 706, 708, 710, 712, 714, and 716 of method 700 may be similar to respective blocks 502, 504, 506, 508, 510, 512, 514, and 516 of method 500. At block 702, the method 700 may include providing an IC structure including a first ILD layer disposed on an underlying layer, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer. Such an IC structure may be formed, for example, according to blocks 302, 304, and 306 of method 300 as discussed above. The sacrificial layer may include a first sacrificial material.

FIG. 8A illustrates the IC structure 800 including a first ILD layer 802 formed on an underlying layer 804, a sacrificial layer 806 formed on the first ILD layer 802, and a hard mask layer 808 formed on the sacrificial material.

At block 704, the method 700 may include etching portions of the hard mask layer to form openings in the hard mask layer.

FIG. 8B illustrates the IC structure 800 with portions of the hard mask layer 808 removed by etching to form openings 810a-c.

At block 706, the method 700 may include forming spacers on the sides of the openings in the hard mask layer. The spacers may be coupled with the sidewalls of the hard mask layer in the openings. The spacers may be any suitable etch resistant material that has the required etch selectivity, such as a transition metal oxide or nitride or a dielectric material such as SiN.

FIG. 8C illustrates the IC structure 800 with spacers 812 disposed in the sides of the openings 810a-c. At block 708, the method 700 may include forming a first set of trench openings in the sacrificial layer for a first set of trenches. The trench openings may be formed, for example, by removing the portion of the sacrificial material between spacers of a given opening. Thus, between the spacers, the openings may be extended down to the first ILD layer.

FIG. 8D illustrates the IC structure 800 with the openings 810a-c extending, between the spacers 812 on the sides of each opening 810a-c, down to the first ILD layer 802.

At block 710, the method 700 may include forming via openings in the first ILD layer below one or more of the first set of trench openings. The via openings may be referred to as a first set of via openings.

FIG. 8E illustrates the IC structure 800 with the portion of the first ILD layer 802 in the opening 810c removed to form a via opening.

At block 712, the method 700 may include forming a metal (e.g., metallization) in the first set of trench openings and the first set of via openings. In some embodiments, a top surface of the IC structure may be polished subsequent to forming the metal. The spacers and/or portions of the hard mask layer may remain after the polishing.

FIG. 8F illustrates the IC structure 800 with a metal 814 formed in the openings 81 Oa-c.

At block 714, the method 700 may include forming a second set of trench openings in the sacrificial layer for a second set of trenches. The second set of trench openings may be formed, for example, by removing the remaining portions of the hard mask layer and removing the portions of the sacrificial layer below the remaining portions of the hard mask layer. Accordingly, the second set of trench openings may alternate with the first set of trench openings.

FIG. 8G illustrates the IC structure 800 with openings 816a-d in the sacrificial layer 806.

At block 716, the method 700 may include forming via openings in the first ILD layer below one or more of the second set of trench openings. The via openings may be referred to as a second set of via openings.

FIG. 8H illustrates the IC structure 800 with the portion of the first ILD layer 802 in the opening 816b removed to form a via opening. At block 718, the method 700 may include forming (e.g., depositing or filling) a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. The second sacrificial material may be used as a mask (e.g., hard mask) for recessing the metal in the first set of trench openings and may be resistant to (e.g., not removed by) the process that is used to recess the metal in block 720 as further discussed below. For example, the second sacrificial material may include a spin- on dielectric such as CDO, or amorphous carbon or a nitride or oxide of a transition metal.

FIG. 8I illustrates the IC structure 800 with a second sacrificial material 818 disposed in openings 816a-d.

At block 720, the method 700 may include recessing the metal that is disposed in the first set of trench openings. For example, a top portion of the metal in the first set of trench openings may be removed by an etch process. The metal may be recessed to a level below a top surface of the sacrificial layer. The second sacrificial material may protect the first ILD layer from the etch process.

FIG. 8J illustrates the IC structure 800 with the metal 814 in openings 810a-c recessed to a level below a top surface of the sacrificial layer 806.

At block 722, the method 700 may include forming a first hard mask material on the recessed metal in the first set of trench openings. The top surface of the IC structure may then be polished to remove the spacers.

FIG. 8K illustrates the IC structure 800 with a first hard mask material 820 disposed on the metal 814 and the top surface polished to remove the spacers 812.

At block 724, the method 700 may include removing the second sacrificial material from the second set of trench openings and the second set of via openings. FIG. 8L illustrates the IC structure 800 with the second sacrificial material 818 removed from the openings 816a-d.

At block 726, the method 700 may include forming a metal in the second set of trench openings and the second set of via openings. FIG. 8M illustrates the IC structure 800 with the metal 814 disposed in the openings 816a-d. At block 728, the method 700 may include recessing the metal that is disposed in the second set of trench openings. For example, a top portion of the metal in the second set of trench openings may be removed by an etch process. FIG. 8N illustrates the IC structure 800 with the metal 814 in the openings 816a-d recessed.

At block 730, the method 700 may include forming a second hard mask material on the metal in the second set of trench openings. The second hard mask material may be deposited with an overfill and then polished so that a top surface of the second hard mask material is substantially co-planar with a top surface of the first hard mask material and/or sacrificial layer. The second hard mask material may have a different etch selectivity than the first hard mask material to enable the second hard mask material to be etched independently from the first hard mask material (e.g., without etching the first hard mask material).

FIG. 80 illustrates the IC structure 800 with a second hard mask material 822 disposed on the metal 814 in the openings 816a-d.

At block 732, the method 700 may include removing the sacrificial layer (e.g., between the trenches). Removal of the sacrificial layer may expose the first ILD layer between the trenches. FIG. 8P illustrates the IC structure 800 with the sacrificial layer 806 removed, and the first ILD layer 802 exposed between the trenches formed by the metal 814.

At block 734, the method 700 may include forming a second ILD layer on the first ILD layer between the trenches. The second ILD layer may be formed and/or recessed so that a top surface of the second ILD layer is

substantially co-planar with a top surface of the trenches. Alternatively, the top surface of the second ILD layer may be higher than the top surface of the trenches. As discussed further herein, the second ILD layer may be more porous than the first ILD layer.

FIG. 8Q illustrates the IC structure 800 with a second ILD layer 824 disposed on the first ILD layer 802 between the trenches formed by the metal 814.

At block 736, the method 700 may include forming a third hard mask material on the second ILD layer. The third hard mask material may have a different etch selectivity than the first and/or second hard mask materials to enable the third hard mask material to be etched (e.g., removed) independently from the first and/or second hard mask materials.

FIG. 8R illustrates the IC structure 800 with a third hard mask material 826 disposed on the second ILD layer 824. The hard mask materials 820, 822, and 826 may facilitate formation of conductive connections with the trenches by subsequent layers of the IC structure 800 while preventing the formation of an unwanted conductive connection (e.g., short) between adjacent trenches. For example, the hard mask material 820 may be removed without removing the hard mask materials 822 and 826 to enable formation of conductive connections with the trenches in the openings 81 Oa-c while access to the trenches in the openings 816a-d is blocked by the hard mask materials 822 and 826. The second hard mask material 822 may subsequently be removed to enable formation of conductive connections to the trenches in the openings 816a-d.

FIGS. 9A and 9B provide a flow chart to illustrate another method 900 for forming an IC structure with a replacement ILD layer using a process that uses multiple hard mask materials on the trenches and/or spacers, in accordance with various embodiments. The method 900 also uses a dual metallization process similar to the dual metallization process of methods 500 and/or 700. FIGS. 10A-10R schematically illustrate a cross-sectional side view of an IC structure 1000 at various stages of the method 900, in accordance with various embodiments. Accordingly, the method 900 will be described below with reference to FIGS. 10A-10R. Similar fabrication principles to those described herein may be used to form IC structures with other configurations than that shown in FIGS. 10A-10R. In some embodiments, the IC structure 1000 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., trenches or vias).

In method 900, a portion of the first ILD layer (e.g., a top portion that may be damaged from other operations of method 900) may be removed. In some embodiments the sacrificial layer may include a wet cleanable hard mask material to facilitate the method 900.

At block 902, the method 900 may include providing an IC structure including a first ILD layer disposed on an underlying layer, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer. Such an IC structure may be formed, for example, according to blocks 302, 304, and 306 of method 300 as discussed above. The sacrificial layer may include a first sacrificial material. In some embodiments, the first sacrificial material may be a wet cleanable hard mask material. For example, the first sacrificial material may be an oxide or nitride of a transition metal, such as titanium nitride (TiN).

FIG. 10A illustrates the IC structure 1000 including a first ILD layer 1002 formed on an underlying layer 1004, a sacrificial layer 1006 formed on the first ILD layer 1002, and a hard mask layer 1008 formed on the sacrificial material.

At block 904, the method 900 may include etching portions of the hard mask layer to form openings in the hard mask layer. FIG. 10B illustrates the IC structure 1000 with portions of the hard mask layer 1008 removed by etching to form openings 1010a-c.

At block 906, the method 900 may include forming spacers on the sides of the openings in the hard mask layer. The spacers may be coupled with the sidewalls of the hard mask layer in the openings. The spacers may be any suitable etch resistant material that has the required etch selectivity, such as a transition metal oxide or nitride or a dielectric material such as SiN.

FIG. 10C illustrates the IC structure 1000 with spacers 1012 disposed in the sides of the openings 1010a-c.

At block 908, the method 900 may include forming a first set of trench openings in the sacrificial layer for a first set of trenches. The trench openings may be formed, for example, by recessing the openings between the spacers through the sacrificial layer and into the first ILD layer. Thus, in a horizontal region defined by the openings between the spacers, the sacrificial layer and a portion of the first ILD layer may be removed.

FIG. 10D illustrates the IC structure 1000 with the openings 1010a-c extending, between the spacers 1012 on the sides of each opening 1010a-c, and down into the first ILD layer 1002 so that the openings 101 Oa-c extend below a top surface of the first ILD layer 1002.

At block 910, the method 900 may include forming via openings in the first ILD layer below one or more of the first set of trench openings. The via openings may be referred to as a first set of via openings. FIG. 10E illustrates the IC structure 1000 with the portion of the first ILD layer 1002 in the opening 1010c removed to form a via opening. At block 912, the method 900 may include forming a metal in the first set of trench openings and the first set of via openings. In some embodiments, a top surface of the IC structure may be polished subsequent to forming the metal. The spacers and/or portions of the hard mask layer may remain after the polishing. FIG. 10F illustrates the IC structure 1000 with a metal 1014 formed in the openings 1010a-c.

At block 914, the method 900 may include forming a second set of trench openings in the sacrificial layer for a second set of trenches. The second set of trench openings may be formed, for example, by removing the remaining portions of the hard mask layer and etching away the sacrificial layer and a portion of the first ILD layer below the remaining portions of the hard mask layer (that were also removed). Accordingly, the second set of trench openings may alternate with the first set of trench openings.

FIG. 10G illustrates the IC structure 1000 with openings 1016a-d in the sacrificial layer 1006 that extend into the first ILD layer 1002 (e.g., the openings 1016a-d extend below a top surface of the first ILD layer 1002).

At block 916, the method 900 may include forming via openings in the first ILD layer below one or more of the second set of trench openings. The via openings may be referred to as a second set of via openings. FIG. 10H illustrates the IC structure 1000 with the portion of the first ILD layer 1002 in the opening 1016b removed to form a via opening.

At block 918, the method 900 may include forming a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. The second sacrificial material may be used as a mask (e.g., hard mask) for recessing the metal in the first set of trench openings and may be resistant to (e.g., not removed by) the process that is used to recess the metal in block 920 as further discussed below. For example, the second sacrificial material may include a dielectric or a carbon- based material.

FIG. 101 illustrates the IC structure 1000 with a second sacrificial material 1018 disposed in openings 1016a-d.

At block 920, the method 900 may include recessing the metal that is disposed in the first set of trench openings. For example, a top portion of the metal in the first set of trench openings may be removed by an etch process. The metal may be recessed to a level below the sacrificial layer (e.g., below a top surface of the first ILD layer.

FIG. 10J illustrates the IC structure 1000 with the metal 1014 in openings 1010a-c recessed to a level below the sacrificial layer 1006 and below a top surface of the first ILD layer 1002.

At block 922, the method 900 may include forming a first hard mask material on the metal in the first set of trench openings. The top surface of the IC structure may then be polished to remove the spacers.

FIG. 10K illustrates the IC structure 1000 with a first hard mask material 1020 disposed on the metal 1014 and the top surface polished to remove the spacers 1012.

At block 924, the method 900 may include removing the second sacrificial material from the second set of trench openings and the second set of via openings.

FIG. 10L illustrates the IC structure 1000 with the second sacrificial material 1018 removed from the openings 1016a-d.

At block 926, the method 900 may include forming a metal in the second set of trench openings and the second set of via openings.

FIG. 10M illustrates the IC structure 1000 with the metal 1014 disposed in the openings 1016a-d.

At block 928, the method 900 may include recessing the metal that is disposed in the second set of trench openings. For example, a top portion of the metal in the second set of trench openings may be removed by an etch process. In some embodiments, the metal in the second set of trench openings may be recessed to a level below a top surface of the first ILD layer (e.g., to a level even with the metal in the first set of trench openings).

FIG. 10N illustrates the IC structure 1000 with the metal 1014 in the openings 1016a-d recessed.

At block 930, the method 900 may include forming a second hard mask material on the metal in the second set of trench openings. The second hard mask material may be deposited with an overfill and then polished so that a top surface of the second hard mask material is substantially co-planar with a top surface of the first hard mask material and/or sacrificial layer. The second hard mask material may have a different etch selectivity than the first hard mask material to enable the second hard mask material to be etched independently from the first hard mask material (e.g., without etching the first hard mask material).

FIG. 10O illustrates the IC structure 1000 with a second hard mask material 1022 disposed on the metal 1014 in the openings 1016a-d.

At block 932, the method 900 may include removing the sacrificial layer (e.g., between the trenches) and etching away a top portion of the first ILD layer below the sacrificial layer. For example, the portion of the first ILD layer below the sacrificial layer may be recessed to be substantially even with a lower surface of the trenches. The sacrificial layer may be removed, for example, by a wet clean process. The top portion of the first ILD layer may be removed, for example, by plasma etch. The top portion of the first ILD layer may be damaged by other operations of the method 900, and removal of the top portion of the first ILD layer may improve the structure of the first ILD layer.

FIG. 10P illustrates the IC structure 1000 with the sacrificial layer 1006 removed, and a top portion of the first ILD layer 1002 (e.g., the portion between the trenches formed by the metal 1014) removed.

At block 934, the method 900 may include forming a second ILD layer on the first ILD layer between the trenches. The second ILD layer may be formed and/or recessed so that a top surface of the second ILD layer is higher than a top surface of the trenches. Alternatively, the top surface of the second ILD layer may be substantially co-planar with a top surface of the trenches. As discussed further herein, the second ILD layer may be more porous than the first ILD layer.

FIG. 10Q illustrates the IC structure 1000 with a second ILD layer 1024 disposed on the first ILD layer 1002 between the trenches formed by the metal 1014.

At block 936, the method 900 may include forming a third hard mask material on the second ILD layer. The third hard mask material may have a different etch selectivity than the first and/or second hard mask materials to enable the third hard mask material to be etched (e.g., removed) independently from the first and/or second hard mask materials. FIG. 10R illustrates the IC structure 1000 with a third hard mask material 1026 disposed on the second ILD layer 1024. The IC structure 1000 shown in FIG. 10R may be similar to the IC structure 800 shown in FIG. 8R.

Various operations of the methods 300, 500, 700, and/or 900 are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.

FIG. 11 schematically illustrates an example system (e.g., computing device 1 100) that may include an IC structure (e.g., IC structure 400, 600, 800, and/or 1000, and/or an IC structure formed using method 300, 500, 700, and/or 900) as described herein, in accordance with some embodiments.

Components of the computing device 1 100 may be housed in an enclosure (e.g., housing 1 108). The motherboard 1 102 may include a number of components, including but not limited to a processor 1 104 and at least one communication chip 1 106. The processor 1 104 may be physically and electrically coupled to the motherboard 1 102. In some implementations, the at least one communication chip 1 106 may also be physically and electrically coupled to the motherboard 1 102. In further implementations, the communication chip 1 106 may be part of the processor 1 104.

Depending on its applications, computing device 1 100 may include other components that may or may not be physically and electrically coupled to the motherboard 1 102. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1 106 may enable wireless communications for the transfer of data to and from the computing device 1 100. The term

"wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1 106 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.1 1 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., LTE-Advanced project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide

Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1 106 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 606 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access

Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 606 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1 106 may operate in accordance with other wireless protocols in other embodiments.

The computing device 1 100 may include a plurality of communication chips 1 106. For instance, a first communication chip 1 106 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1 106 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV- DO, and others. The processor 1 104 of the computing device 1 100 may include a die (e.g., die 102 of FIGS. 1 -2) having an IC structure (e.g., IC structure 400, 600, 800, and/or 1000, and/or an IC structure formed using method 300, 500, 700, and/or 900) as described herein. For example, the die 102 of FIGS. 1 -2 may be mounted in a package assembly that is mounted on a circuit board such as the motherboard 1 102. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1 106 may also include a die (e.g., die 102 of FIGS. 1 -2) having an IC structure (e.g., IC structure 400, 600, 800, and/or 1000, and/or an IC structure formed using method 300, 500, 700, and/or 900) as described herein. In further implementations, another component (e.g., memory device or other integrated circuit device) housed within the computing device 1 100 may contain a die (e.g., die 102 of FIGS. 1 -2) having an IC structure (e.g., IC structure 400, 600, 800, and/or 1000, and/or an IC structure formed using method 300, 500, 700, and/or 900) as described herein.

In various implementations, the computing device 1 100 may be a mobile computing device, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1 100 may be any other electronic device that processes data.

Some non-limiting Examples are provided below.

Example 1 is a method for fabricating an integrated circuit (IC) structure, comprising: providing a stack including a first inter-layer dielectric (ILD) layer disposed on an underlying layer and including a dielectric material, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer; forming trench openings in the sacrificial layer and via openings in the first ILD layer; forming a metal in the trench openings and the via openings to form respective trenches and vias; removing the sacrificial layer; and forming a second ILD layer on the first ILD layer between the trenches. Example 2 is the method of Example 1 , wherein the second ILD layer has a higher porosity than the first ILD layer.

Example 3 is the method of Example 1 , wherein the forming the metal in the trench openings includes depositing the metal on the first ILD layer.

Example 4 is the method of Example 1 , wherein the sacrificial layer includes a wet cleanable dielectric or a wet cleanable hard mask.

Example 5 is the method of any one of Examples 1 to 4, wherein the forming the trench openings and via openings and the forming the metal in the trench openings and the via openings includes: forming a first set of trench openings and a first set of via openings; forming a metal in the first set of trench openings and the first set of via openings to form a first set of trenches and a second set of trenches; after forming the metal in the first set of trench openings and the first via openings, forming a second set of trench openings and a second set of via openings, wherein trench openings of the second set of trench openings alternate with openings of the first set of trench openings in the sacrificial layer; and forming a metal in the second set of trench openings and the second set of via openings to form a second set of trenches and a second set of vias.

Example 6 is the method of Example 5, further comprising: forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the second hard mask material has a different etch selectivity than the first hard mask material.

Example 7 is the method of Example 6, further comprising: forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material has a different etch selectivity than the first and second hard mask materials.

Example 8 is the method of Example 1 , wherein the trench openings extend below a top surface of the first ILD layer.

Example 9 is the method of Example 1 , wherein the first ILD layer has a different material composition than the second ILD layer.

Example 10 is an integrated circuit (IC) comprising: a first inter-layer dielectric (ILD) layer disposed on an underlying layer; a plurality of trenches disposed on the first ILD layer; and a second ILD layer disposed on the first ILD layer between trenches of the plurality of trenches, wherein the second ILD layer has a lower dielectric constant than the first ILD layer. Example 1 1 is the IC of Example 10, further comprising a plurality of vias extending from respective trenches to the underlying layer through the first ILD layer.

Example 12 is the IC of Example 10, wherein a top surface of the first ILD layer is substantially flat.

Example 13 is the IC of Example 10, wherein the second ILD layer is more porous than the first ILD layer.

Example 14 is the IC of Example 10, wherein a lower surface of the second ILD layer is substantially co-planar with lower surfaces of the trenches.

Example 15 is the IC of Example 10, wherein the first ILD layer has a different material composition than the second ILD layer.

Example 16 is a computing device comprising: a circuit board; and a die coupled with the circuit board on a front side of the die. The die includes: a first inter-layer dielectric (ILD) layer disposed on an underlying layer, the first ILD layer including a first dielectric material; a plurality of trenches disposed on the first ILD layer; and a second ILD layer disposed on the first ILD layer between trenches of the plurality of trenches, wherein the second ILD layer includes a second dielectric material that is more porous than the first dielectric material.

Example 17 is the computing device of Example 16, wherein the interconnect layer further includes a plurality of vias extending from respective trenches to the underlying layer through the first ILD layer.

Example 18 is the computing device of Example 16, wherein a lower surface of the second ILD layer is substantially co-planar with lower surfaces of the trenches.

Example 19 is the computing device of Example 16, wherein the first dielectric material has a different material composition from the second dielectric material.

Example 20 is the computing device of any one of Examples 16 to 19, wherein: the die is a processor; and the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera. Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims What is claimed is:

1 . A method for fabricating an integrated circuit (IC) structure, comprising: providing a stack including a first inter-layer dielectric (ILD) layer disposed on an underlying layer and including a dielectric material, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer;

forming trench openings in the sacrificial layer and via openings in the first ILD layer;

forming a metal in the trench openings and the via openings to form respective trenches and vias;

removing the sacrificial layer; and

forming a second ILD layer on the first ILD layer between the trenches.

2. The method of claim 1 , wherein the second ILD layer has a higher porosity than the first ILD layer.

3. The method of claim 1 , wherein the forming the metal in the trench openings includes depositing the metal on the first ILD layer.

4. The method of claim 1 , wherein the sacrificial layer includes a wet cleanable dielectric or a wet cleanable hard mask.

5. The method of any one of claims 1 to 4, wherein the forming the trench openings and via openings and the forming the metal in the trench openings and the via openings includes:

forming a first set of trench openings and a first set of via openings;

forming a metal in the first set of trench openings and the first set of via openings to form a first set of trenches and a second set of trenches;

after forming the metal in the first set of trench openings and the first via openings, forming a second set of trench openings and a second set of via openings, wherein trench openings of the second set of trench openings alternate with openings of the first set of trench openings in the sacrificial layer; and

forming a metal in the second set of trench openings and the second set of via openings to form a second set of trenches and a second set of vias.

6. The method of claim 5, further comprising:

forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the second hard mask material has a different etch selectivity than the first hard mask material.

7. The method of claim 6, further comprising:

forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material has a different etch selectivity than the first and second hard mask materials.

8. The method of claim 1 , wherein the trench openings extend below a top surface of the first ILD layer.

9. The method of claim 1 , wherein the first ILD layer has a different material composition than the second ILD layer.

10. An integrated circuit (IC) comprising:

a first inter-layer dielectric (ILD) layer disposed on an underlying layer; a plurality of trenches disposed on the first ILD layer; and

a second ILD layer disposed on the first ILD layer between trenches of the plurality of trenches, wherein the second ILD layer has a lower dielectric constant than the first ILD layer.

1 1 . The IC of claim 10, further comprising a plurality of vias extending from respective trenches to the underlying layer through the first ILD layer.

12. The IC of claim 10, wherein a top surface of the first ILD layer is substantially flat.

13. The IC of claim 10, wherein the second ILD layer is more porous than the first ILD layer.

14. The IC of claim 10, wherein a lower surface of the second ILD layer is substantially co-planar with lower surfaces of the trenches.

15. The IC of claim 10, wherein the first ILD layer has a different material composition than the second ILD layer.

16. A computing device comprising:

a circuit board; and

a die coupled with the circuit board on a front side of the die, the die having an interconnect layer that includes:

a first inter-layer dielectric (ILD) layer disposed on an underlying layer, the first ILD layer including a first dielectric material;

a plurality of trenches disposed on the first ILD layer; and a second ILD layer disposed on the first ILD layer between trenches of the plurality of trenches, wherein the second ILD layer includes a second dielectric material that is more porous than the first dielectric material.

17. The computing device of claim 16, wherein the interconnect layer further includes a plurality of vias extending from respective trenches to the underlying layer through the first ILD layer.

18. The computing device of claim 16, wherein a lower surface of the second ILD layer is substantially co-planar with lower surfaces of the trenches.

19. The computing device of claim 16, wherein the first dielectric material has a different material composition from the second dielectric material.

20. The computing device of any one of claims 16 to 19, wherein:

the die is a processor; and

the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.