TW201721742A - Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ILD) - Google Patents

Abstract

Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. Other embodiments may be described and/or claimed.

Description

Method, device and system for integrated circuit structure having substituted interlayer dielectric (ILD)

The embodiments of the present invention are generally related to the field of integrated circuits, and more particularly to integrated circuit structures having an inter-layer dielectric (ILD).

In the interconnect layer of integrated circuits, low K dielectrics are commonly used to minimize line-to-line capacitance and layer-to-layer capacitance. However, low K dielectrics have high porosity and may therefore cause problems during the patterning of the interconnect layers.

10‧‧‧ Wafer form

100‧‧‧Single granulation

102, 103a, 103b‧‧‧ grain

11‧‧‧ wafer

400, 600, 800, 1000‧‧‧ integrated circuit structure

104‧‧‧Optical structure

200‧‧‧ integrated circuit assembly

121‧‧‧Package substrate

122‧‧‧ boards

106‧‧‧Grade level interconnect structure

102a‧‧‧Semiconductor substrate

102b‧‧‧Device layer

102c‧‧‧Interconnect layer

1102‧‧‧ motherboard

112‧‧‧ solder balls

110‧‧‧ pads

402, 602, 802, 1002‧‧‧ first interlayer dielectric layer

404, 604, 804, 1004‧‧‧ lower layer

406, 606, 806, 1006‧‧‧ sacrificial materials

408, 608, 808, 1008‧‧‧ hard mask layer

410a, 410b, 610a-c, 616a-d, 810a-c, 816a-d, 1010a-c, 1016a-d‧‧‧ openings

412, 614, 814, 1014‧‧‧ metal

414a, 414b‧‧‧ trench

416‧‧‧through hole

418, 618, 824, 1024‧‧‧Second interlayer dielectric layer

420, 620‧ ‧ etch stop layer

612, 812, 1012‧‧‧ spacers

818, 1018‧‧‧Second sacrificial material

820, 1020‧‧‧ first hard mask material

822, 1022‧‧‧Second hard mask material

826, 1026‧‧‧ Third hard mask material

1100‧‧‧ Computing device

1108‧‧‧ Shell

1104‧‧‧ Processor

1106‧‧‧Communication chip

The embodiments can be readily understood by referring to the detailed description and the drawings. To facilitate the description of the present invention, like reference numerals designate structural elements that are similar. The drawings illustrate the embodiments by way of example and not limitation.

1 is a top plan view showing an example of a wafer in the form of a wafer in a single granulated form, in accordance with certain embodiments.

Figure 2 shows, in schematic form, a cross-sectional side view of an integrated circuit (IC) assembly, in accordance with certain embodiments.

Figure 3 is a flow diagram of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer in accordance with various embodiments.

4A-4G are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

Figure 5 is a flow diagram of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer using a dual metallization process in accordance with certain embodiments.

6A-6L are schematic cross-sectional side views showing an IC structure at various stages of the method of FIG. 4, in accordance with certain embodiments.

7A-B illustrate a flow chart of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer and using a plurality of hard mask materials for short circuit mitigation, in accordance with certain embodiments. .

8A-8R are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

9A-B illustrate a flow of another method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer and using a plurality of hard mask materials for short circuit mitigation, in accordance with certain embodiments Figure.

10A-10R are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

Figure 11 shows an exemplary system in a schematic manner, the exemplary system A transistor electrode assembly of the present invention is included in accordance with certain embodiments.

SUMMARY OF THE INVENTION AND EMBODIMENT

Embodiments of the present invention illustrate techniques and configurations associated with an integrated circuit (IC) structure having a replacement interlayer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer can be formed on the first ILD layer. Patterns of trenches may be created in the sacrificial layer and the trenches are formed such that the trenches are disposed on the first ILD layer. Patterns of vias may be created under the trenches in the first ILD layer and formed into the vias. After the trenches are formed, the sacrificial layer can be removed and the replacement ILD layer (eg, a second ILD layer) can be formed between the trenches on the first ILD layer. The second ILD layer can have a higher porosity and/or a lower dielectric constant than the first ILD layer.

In the following description, reference is made to the accompanying drawings, in which FIG. The figures are shown in the manner of the embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following embodiments are not to be considered as limiting, and the scope of the various embodiments

For convenience of explanation of the present invention, the words "A and/or B" mean (A), (B), or (A and B). For the purpose of illustrating the disclosure of the present invention, the words "A, B, and/or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

This description may use a perspective-based description such as top/bottom, side, and above/under. These descriptions are only used to assist in the discussion, and are not intended to limit the application of the embodiments described herein to any particular orientation.

The description uses the words "in an embodiment," or "in various embodiments," and the terms may mean one or more embodiments of the same or different embodiments, respectively. In addition, when the terms "comprising," "including," and "having" are used, the terms are used synonymously in the context of the embodiments disclosed herein.

The term "coupled to" and its derivatives may be used in the present invention. "Coupled" may mean one or more of the following meanings. "Coupled" may mean that two or more elements are in physical or electrical direct contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or function with each other, and "coupled" may mean that one or more other elements are coupled or connected to being Between these elements, called mutual coupling. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "formed, deposited, or otherwise configured in a first feature on a second feature" may mean forming, depositing, or configuring the second feature over the second feature. a first feature, and at least a portion of the first feature can be in direct contact (eg, physically and/or electrically in direct contact) or indirect contact with at least a portion of the second feature (eg, the first feature and the first feature) There are one or more other features between the two features).

In the usage of the present specification, the term "circuit" may mean an application specific integrated circuit (ASIC), an electronic circuit, a processor that executes one or more software or firmware programs (shared, dedicated, Or a group processor) and/or a memory (common, dedicated, or group memory), a combined logic circuit, and/or a portion of other suitable components that provide the required functionality, or Includes the above items.

1 shows an exemplary die 102 of wafer form 10 and single granulated form 100 in a schematic manner in accordance with certain embodiments. In some embodiments, the die 102 may be one of a plurality of grains (eg, grains 102, 103a, 103b) of a wafer 11 composed of a semiconductor material such as germanium or other suitable material. grain. The plurality of crystal grains may be formed on one surface of the wafer 11. Each of the dies may comprise one or more of the IC structures described herein (eg, IC structures 400, 600, 800, and/or 1000, and/or methods of use 300, 500, 700) And/or one of the semiconductor products of the 900 formed IC structure). For example, the die 102 can include one or more channel paths (eg, fin structures, nanowires) having a mobile charge carrier such as a mobile charge carrier for providing one or more transistor devices or source/drain regions. A circuit of a transistor structure 104 such as a nanowire or a channel body of a planar body. A transistor electrode assembly (eg, a terminal contact) can be formed on the one or more transistor structures 104, and the transistor electrode assemblies can be coupled to the one or more transistor structures 104 to Electrical energy is transferred into or out of the transistor structure 104. For example, the terminal can be electrically contacted Coupled to a channel body to provide a gate electrode for transmitting a threshold voltage and/or a source/drain current to provide mobile charge carriers for operation of the transistor device. Although the transistor structures 104 in each of the columns passing through a substantial portion of the die 102 are shown in FIG. 1 for simplicity, it should be understood that in other embodiments, the die may be The optoelectronic structures 104 are configured on any of a variety of other suitable arrangements (e.g., including some vertical and horizontal features having dimensions that are much smaller than the dimensions shown).

After completing the fabrication of the semiconductor product in the die, the wafer 11 can undergo a dicing process in which each of the dies (e.g., die 102) are separated from each other to provide separation of the semiconductor product. "wafer". Wafer 11 can have any of a variety of sizes. In some embodiments, wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. In other embodiments, wafer 11 may include other sizes and/or other shapes. According to various embodiments, the transistor structures 104 may be disposed on a semiconductor substrate in wafer form 10 or single granulation form 100. The optoelectronic structures 104 of the present invention can be included in one of the dies 102 for logic or memory or a combination of the two. In some embodiments, the transistor structure 104 can be part of a System-on-Chip (SoC) assembly.

FIG. 2 shows a cross-sectional side view of an IC assembly 200 in a schematic manner, in accordance with certain embodiments. In some embodiments, IC assembly 200 can include one or more dies (hereinafter referred to as "die 102") that are electrically and/or physically coupled to a package substrate 121. In some embodiments As shown, the package substrate 121 can be electrically coupled to a circuit board 122. In some embodiments, an IC assembly 200 can include one or more of the die 102, the package substrate 121, and/or the circuit board 122, in accordance with various embodiments. Embodiments of the invention for an IC structure may be implemented in any suitable IC device in accordance with various embodiments.

The die 102 may represent a separate fabrication from a semiconductor material (eg, germanium) using semiconductor techniques such as thin film deposition, lithography, and etching used in connection with forming a complementary metal oxide semiconductor (CMOS) device. product. In some embodiments, the die 102 can be or include a processor, memory, SoC, or ASIC, or can be part of the above. In some embodiments, an electrically insulating material, such as a molding compound or an underfill material (not shown), may encapsulate the die 102 and/or the grain level interconnect structure 106. At least part of it.

The die 102 can be connected to the package substrate 121 in accordance with a variety of suitable configurations including direct coupling to the package substrate 121 in a flip-chip configuration, such as shown. In the flip chip configuration, the active level S1 of one of the included circuits of the die 102 is connected to the die level interconnect structure 106, such as a bump, a pillar, or other suitable structure. A surface of the package substrate 121, wherein the other suitable structures can also electrically couple the die 102 to the package substrate 121. The active surface S1 of the die 102 may comprise an active device such as a transistor device. As shown, a non-active surface S2 can be disposed opposite the active surface S1.

The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter referred to as "device layer 102b"), and one or more interconnect layers (hereinafter referred to as "interconnect layer 102c"). In some embodiments, the semiconductor substrate 102a can be substantially composed of a bulk semiconductor material such as germanium. The device layer 102b may represent an area in which an active device such as a transistor device or the like is formed on the semiconductor substrate. For example, device layer 102b can comprise a transistor structure such as a channel body and/or a source/drain region of a transistor device. Interconnect layer 102c may include interconnect structures configured to carry electrical signals into or out of device layers in device layer 102b. For example, interconnect layer 102c can include vertical lines (eg, trenches), and/or vertical plugs (eg, vias), or other suitable features for providing circuit wiring and/or contacts. In various embodiments, one or more of the interconnect layers 102c can comprise a substituted ILD as will be further described below.

In some embodiments, the grain level interconnect structure 106 can be electrically coupled to the interconnect layer 102c and can be configured to transfer electrical signals between the die 102 and other electrical devices. The electrical signals may include input/output (I/O) signals and/or power/ground signals, such as used in connection with the operation of die 102.

In some embodiments, the package substrate 121 is an epoxy having a core and/or build-up layer, such as Ajinomoto Build-up Film (ABF). A resin laminate substrate. In other embodiments, the package substrate 121 may include other suitable types of substrates including, for example, by glass, A substrate formed of ceramic or semiconductor material.

The package substrate 121 can include circuit routing features configured to carry electrical signals into or out of the die 102. The circuit routing features can include pads or traces (not shown) disposed on one or more surfaces of the package substrate 121, and/or such as for transmitting electrical signals through the package substrate 121. Internal wiring features (not shown) of trenches, vias, or other interconnect structures. For example, in some embodiments, package substrate 121 can include circuit routing features such as pads (not shown) that are configured to accept respective die level interconnect structures 106 of die 102.

The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulating material such as an epoxy laminate. For example, the circuit board 122 may include a phenolic cotton paper material such as polytetrafluoroethylene, Flame Retardant 4 (FR-4), FR-1 tissue paper, or the like, CEM- 1 or some electrical insulating layer composed of an epoxy resin material such as CEM-3 or a woven glass material laminated with an epoxy prepreg material. An interconnect structure (not shown) such as traces, trenches, or vias may be formed through the electrically insulating layers to transfer electrical signals of the die 102 via the circuit board 122. In other embodiments, circuit board 122 may be comprised of other suitable materials. In some embodiments, circuit board 122 is a motherboard (eg, motherboard 1102 of FIG. 11).

Package level interconnects, such as solder balls 112, may be coupled to one or more pads on package substrate 121 and/or on circuit board 122 (hereinafter referred to as "" Pad 110") to form a corresponding solder joint configured to further transfer electrical signals between package substrate 121 and circuit board 122. Such as may include nickel (Ni), palladium (Pd), gold (Au Any suitable conductive material, such as silver (Ag), copper (Cu), and combinations of the above materials, may be used to form the pads 110. In other embodiments, the package substrate may be physically and/or electrically used. 121 other suitable techniques coupled to circuit board 122.

In other embodiments, the IC assembly 200 can include a variety of other suitable configurations including, for example, flip chip and/or wire-bonding configurations, interposers, including system level packages (System- An appropriate combination of in-package (SiP) multi-chip package configuration and/or package-on-package (PoP) configuration. In some embodiments, other suitable techniques for transmitting electrical signals between the die 102 and other components of the IC assembly 200 can be used.

3 is a flow diagram of a method 300 for forming an IC structure having a substituted ILD layer in accordance with various embodiments. 4A, 4B, 4C, 4D, 4E, 4F, and 4G are schematic cross-sectional side views of an IC structure 400 at various stages of method 300, in accordance with various embodiments. Accordingly, method 300 will be described hereinafter with reference to Figures 4A-4G. Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 4A-4G. In some embodiments, IC structure 400 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

At block 302, method 300 can include forming a first ILD layer on a lower layer. The underlying layer can be any suitable IC layer such as a device layer, another interconnect layer, or a semiconductor substrate. The first may be formed by any suitable deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). An ILD layer. Additionally, the first ILD layer can comprise any suitable dielectric material or combination of dielectric materials including one or more high K or low K value materials.

For example, the first ILD layer may include cerium oxide (SiO ₂ ), cerium oxynitride (SiO _x N _y ), cerium nitride (Si _x N _y ), aluminum oxide (Al ₂ O ₃ ), cerium oxide ( HfO ₂ ), strontium aluminate (HfAl _x O _y ), bismuth ruthenate (HfSi _x O _y ), zirconium oxide (ZrO ₂ ), zirconium silicate (ZrSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), Yttrium oxide (Y ₂ O ₃ ), barium aluminate (LaAl _x O _y ), tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), barium titanate (BaSrTi _x O _y ), barium titanate (BaTi _x O _y ), barium titanate (SrTi _x O _y ), lead phthalate (PbSc _x Ta _y O _z ), or lead lanthanum zincate (PbZn _x Nb _y O _z ), carbon doped oxide ( Carbon Doped Oxide; abbreviated as CDO), an organic polymer such as perfluorocyclobutane or polytetrafluoroethylene, Fluorosilicate Glass (FSG), and polysilsesquioxanes An organosilicate such as a silsesquioxane, a siloxane, or an organosilicate glass, or a combination of the above, wherein x, y, and z represent appropriate amounts of the respective elements. In some embodiments, when a high-k material is used, an annealing process can be performed on the first ILD layer to improve its quality. In other embodiments, other materials may also be used for the first ILD layer.

At block 304, method 300 can include forming a sacrificial layer on the first ILD layer. In some embodiments, the sacrificial layer can comprise any suitable material that can be wet cleaned, such as a dielectric material or a hard mask material. For example, the sacrificial layer may include titanium nitride (TiN) or amorphous silicon (abbreviated as a-Si).

At block 306, method 300 can include forming a hard mask layer on the sacrificial layer. The hard mask layer can be a pattern-generating material to selectively remove portions of the hard mask layer. For example, the hard mask layer may comprise a dielectric material (eg, one or more oxides, nitrides, carbides, or mixed oxynitrides, carbon doped oxides, nitrogen-doped carbides, etc.) And/or one or more transition metal compounds (for example, transition metal compounds such as titanium (Ti), zirconium (Zr), hafnium (Hf) oxides or nitrides).

FIG. 4A shows the IC structure 400 after block 306 of method 300. The IC structure 400 includes a first ILD layer 402 formed on a lower layer 404, a sacrificial material 406 formed on the first ILD layer 402, and a hard mask layer 408 formed on the sacrificial material.

At block 308, method 300 can include forming a trench opening in the hard mask layer and the sacrificial layer. The trench openings may extend through the sacrificial layer to the first ILD layer. The hard mask layer and portions of the sacrificial material can be removed to form the trench openings. In some embodiments, Removing portions of the hard mask layer using a selective removal process, and then removing the sacrificial material disposed under the removed portions of the hard mask layer section. The portions of the sacrificial material can be removed, such as by an etch process. The etch process can use an etchant that is more selective to the sacrificial material than the first ILD layer. That is, the first ILD layer can be used as an etch stop layer and can be removed by the etching process.

FIG. 4B illustrates an IC structure 400 having openings 410a and 410b in the hard mask layer 408 and the sacrificial material 406. The openings 410a and 410b in the sacrificial material 406 may correspond to trench openings that will form trenches that horizontally transmit electrical signals in the IC structure 400. Thus, the openings 410a and 410b can extend horizontally beyond the face shown in FIG. 4B (eg, extending into the page and/or extending beyond the page).

At block 310, method 300 can further include: creating a pattern of via openings in the first ILD layer below respective portions of the trench openings. Portions of the first ILD layer may be removed to form the via openings. The via openings may extend to the underlying layer to enable formation (as will be further explained below) in the via openings to electrically couple corresponding trenches to the vias of the underlying layer.

FIG. 4C illustrates IC structure 400 after block 310 of method 300. The portion of the first ILD layer in opening 410a has been removed while opening 410a extends to lower layer 404. As will be explained further below, a conductive material can be formed in the opening 410a to form a through hole. The via may be disposed only under a portion of the corresponding trench, and thus The portion of the opening 410a (e.g., the via opening) in the first ILD layer 402 may extend only a small amount (e.g., significantly smaller than the sacrificial layer 406) in a horizontal direction from the face shown in Fig. 4C. The horizontal extent of the portion of the opening 410a (eg, the trench opening).

At block 312, method 300 can include forming a metal in the trench openings and the via openings. The metal may be formed in the trench openings and via openings by any suitable deposition technique that may include a conformal and/or selective deposition process. For example, the metal can be formed by CVD, ALD, PVD, electroless plating, electroplating, or a suitable combination of these deposition techniques.

The metal can include any suitable metal. For example, in certain embodiments, the metal may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt ( Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or a combination of the above. In some embodiments, the metal layer can include a metal nitride such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or a combination of the above. In some embodiments, the metal layer may include, for example, titanium telluride (TiSi), tungsten telluride (WSi), tantalum telluride (TaSi), cobalt telluride (CoSi), platinum telluride (PtSi), nickel telluride (NiSi), or A metal halide of a combination of the above. In some embodiments, the metal layer can include a metal tantalum nitride such as titanium germanium nitride (TiSiN), or tantalum nitride (TaSiN), or a combination thereof. In certain embodiments, the metal layer may include, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), tantalum carbide (HfC), or aluminum carbide (AlC), or a combination thereof. Wait Metal carbide. In certain embodiments, the metal layer can include a metal carbonitride such as tantalum nitride carbon (TaCN), titanium nitride carbon (TiCN), or a combination of the above. In certain embodiments, the metal layer can include a conductive metal oxide (eg, hafnium oxide).

In some embodiments, the top surface of the IC structure can be ground after the metal is formed in the trench openings and the via openings. The polishing process removes the remainder of the hard mask layer and any excess metal disposed over the trench openings. The polishing process can include, for example, chemical mechanical polishing using a slurry designed to remove the metals used in the IC structure.

The 4D diagram shows the IC structure 400 after block 312 and shows one of the metals 412 disposed in the openings 410a-b. In the face shown in FIG. 4D, metal 412 forms one of trenches 414b in opening 410b, and one of trenches 414a and a via 416 in opening 410a. The top surface of the IC structure 400 has been ground to remove the remainder of the hard mask layer 408 and any excess metal 412 over the openings 410a-b.

At block 314, method 300 can include removing the sacrificial layer. The sacrificial layer can be removed by any suitable process such as wet cleaning.

4E illustrates the IC structure 400 after block 314 and shows that the sacrificial layer 406 has been removed (such as between the trenches 414a-b).

At block 316, method 300 can include forming a second ILD layer on the first ILD layer (eg, between the trenches formed by the metal). The second ILD layer can have a higher porosity and/or a lower density than the first ILD layer. The second ILD layer may additionally or alternatively have a ratio The first ILD layer has a low dielectric constant (K). For example, in certain embodiments, the second ILD layer can comprise a low porosity such as carbon doped oxide (CDO) having a controlled porosity (eg, 50% porosity). K value dielectric material. In some embodiments, the second ILD layer can have the same material composition as the first ILD layer, but may have a higher porosity and/or a lower density. In other embodiments, the second ILD layer can be a different material than the first ILD layer.

The second ILD layer may be formed on the first ILD layer by any suitable process such as a spin-on process or a deposition process such as chemical vapor deposition (CVD). In some embodiments, the voiding caused by the CVD process provides a lower K value for the second ILD layer formed. In some embodiments, an overloaded ILD material can fill the openings between the trenches to form the second ILD layer, and then the excess ILD material can be ground or recessed to an appropriate height (eg, to the The height of the groove).

The first ILD layer can provide structural support for the trenches, and the second ILD layer can prevent/reduce the capacitance between the trenches.

FIG. 4F shows the IC structure 400 after block 316. A second ILD layer 418 is disposed on the first ILD layer 402 (eg, between the trenches 414a-b). The trenches 414a-b may be disposed on the first ILD layer 402 (e.g., except where vias are disposed under the trenches). As shown in the face of FIG. 4F, the trench 414b is disposed on the first ILD layer 402, and the trench 414a is disposed on the via 416.

In some embodiments, in block 318, method 300 can be further Including: forming one or more additional layers on the second ILD layer and/or each trench. For example, an etch stop layer can be formed on the second ILD layer and/or each trench. Additional layers such as another interconnect layer may be formed on the etch stop layer.

FIG. 4G illustrates an IC structure 400 having an etch stop layer 420 disposed on the second ILD layer 418 and trenches 414a-b.

In various embodiments, method 300 and/or IC structure 400 may provide one or more advantages over previous methods and/or IC structures. In some embodiments, the sacrificial material (eg, the material of the sacrificial layer 406) can have better pattern fidelity than the material of the second ILD layer (eg, the second ILD layer 418). For example, the sacrificial material can be denser than the material of the second ILD layer to enable better pattern fidelity. Additionally or alternatively, during patterning and metallization, method 300 and/or IC structure 400 may not use a hole fill material to fill the holes of the second ILD layer while maintaining the structure of the second ILD layer, which This is because the second ILD layer is formed after patterning and metallization.

Additionally or alternatively, arranging the first ILD layer under the second ILD layer and/or the trenches may be superior to using a single sacrificial material in place of the sacrificial layer 406 and the first ILD layer 402; After the trenches and vias are removed, the sacrificial material is removed; and then, under the trenches and between the trenches, backfilled with a replacement ILD. For example, when the second ILD material is disposed under the trenches, the first ILD layer can provide better structural support for the trenches without performing damage to the trenches. Etching and backfilling of the trenches and/or may be provided for forming such An etch stop layer of trench openings (e.g., forming trench openings as described with reference to block 308) is capable of forming a uniform and controlled depth of the trenches.

In various embodiments, a sacrificial material on a first ILD layer can be used to create a pattern of interconnect structures and metallization and then replace the sacrificial material with a second ILD layer (eg, as previously described herein) The features described in Figures 3 and 4 are combined with other techniques for forming interconnect layers. For example, such techniques can be used with bimetallization processes that respectively create patterns of alternating trenches and metallize the trenches and/or use a variety of hard mask materials on the trenches and/or spacers. A process bonding (such as to mitigate shorting between the trenches).

5 is a flow diagram of a method 500 for forming an IC structure having a substituted ILD layer using a dual metallization process that produces alternating trench patterns and metallizes the trenches, respectively, in accordance with various embodiments. Figure. 6A-6L show, in schematic form, a cross-sectional side view of an IC structure 600 at various stages of method 500, in accordance with various embodiments. Accordingly, method 500 will be described hereinafter with reference to Figures 6A-6L. For ease of illustration, not every component is labeled with a reference number in each of Figures 6A-6L.

Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 6A-6L. In some embodiments, IC structure 600 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

At block 502, method 500 can include providing a first ILD layer disposed on a lower layer, configured on the first ILD layer a sacrificial layer, and an IC structure of a hard mask layer disposed on the sacrificial layer. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above.

6A illustrates a first ILD layer 602 formed on a lower layer 604, a sacrificial layer 606 formed over the first ILD layer 602, and a hard mask layer 608 formed over the sacrificial material. The IC structure 600.

At block 504, method 500 can include etching portions of the hard mask layer and forming openings in the hard mask layer.

FIG. 6B illustrates an IC structure 600 that forms openings 610a-c by etching portions of the hard mask layer 608.

At block 506, method 500 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

Figure 6C shows an IC structure 600 having spacers 612 disposed on the sides of the openings 610a-c.

At block 508, method 500 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, portions of the sacrificial material between the spacers of a particular opening can be removed to form the trench openings. Thus, between the spacers, the openings may extend down to the first ILD layer.

FIG. 6D illustrates the openings 610a-c between the spacers 612 on the sides of each opening 610a-c extending down to the IC structure 600 of the first ILD layer 602.

At block 510, method 500 can include forming a via opening in the first ILD layer below one or more of the trench openings in the first set of trench openings. The through hole openings may be referred to as a first set of through hole openings.

FIG. 6E illustrates an IC structure 600 in which a portion of the first ILD layer 602 is removed in the opening 610c to form a via opening.

At block 512, method 500 can include forming a metal (eg, metallization) in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist.

Figure 6F shows an IC structure 600 having a metal 614 formed in openings 610a-c.

At block 514, method 500 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the portion of the sacrificial layer below the remaining portions of the hard mask layer removed to form the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

FIG. 6G illustrates an IC structure 600 having openings 616a-d in the sacrificial layer 606.

At block 516, method 500 can include forming a via in the first ILD layer below one or more trench openings in the second set of trench openings Opening. The through hole openings may be referred to as a second set of through hole openings.

FIG. 6H illustrates an IC structure 600 in which a portion of the first ILD layer 602 is removed in the opening 616b to form a via opening.

At block 518, method 500 can include forming a metal (eg, metallization) in the second set of trench openings and the second set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. The grinding removes the spacers and the metal formed between the spacers in block 512.

Figure 6I shows IC structure 600 after block 518, showing metal 614 formed in openings 616a-d. The spacers 612 have been removed (such as with grinding).

At block 520, method 500 can include removing remaining sacrificial material (eg, sacrificial material disposed under the spacers). This removal of the sacrificial material can leave an opening between the grooves. Figure 6J shows the IC structure 600 with the sacrificial layer 606 removed, and shows the openings between the trenches.

At block 522, method 500 can include forming a second ILD layer on the first ILD layer between the trenches. Figure 6K shows an IC structure 600 of a second ILD layer 618 included between the trenches.

At block 524, method 500 can include forming an etch stop layer on the second ILD layer and/or the trenches. FIG. 6L illustrates an IC structure 600 of an etch stop layer 620 included on the second ILD layer 618.

7A and 7B are diagrams showing the use of a process for using a plurality of hard mask materials on the trenches and/or spacers, in accordance with various embodiments. A flow chart of a method 700 of forming an IC structure having a replacement ILD layer. The method 700 also uses a dual metallization process similar to the dual metallization process of method 500. 8A-8R are schematic cross-sectional side views of an IC structure 800 at various stages of method 700, in accordance with various embodiments. Accordingly, method 700 will be described hereinafter with reference to Figures 8A-8R. For ease of illustration, not every component is labeled with a reference number in each of Figures 8A-8R.

Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 8A-8R. In some embodiments, IC structure 800 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

In various embodiments, blocks 702, 704, 706, 708, 710, 712, 714, and 716 of method 700 can be similar to respective blocks 502, 504, 506, 508, 510, 512, 514 of method 500, and 516. At block 702, method 700 can include providing a first ILD layer disposed on a lower layer, a sacrificial layer disposed on the first ILD layer, and a first one disposed on the sacrificial layer One of the hard mask layers of the IC structure. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above. The sacrificial layer can comprise a first sacrificial material.

8A illustrates a first ILD layer 802 formed on a lower layer 804, a sacrificial layer 806 formed over the first ILD layer 802, and a hard mask layer 808 formed over the sacrificial material. The IC structure 800.

At block 704, method 700 can include etching portions of the hard mask layer and forming openings in the hard mask layer.

FIG. 8B illustrates an IC structure 800 that forms openings 810a-c by etching portions of the hard mask layer 808.

At block 706, method 700 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

Figure 8C shows an IC structure 800 having spacers 812 disposed on the sides of the openings 810a-c.

At block 708, method 700 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, portions of the sacrificial material between the spacers of a particular opening can be removed to form the trench openings. Thus, between the spacers, the openings may extend down to the first ILD layer.

8D illustrates the openings 810a-c between the spacers 812 on the sides of each opening 810a-c extending down to the IC structure 800 of the first ILD layer 802.

At block 710, method 700 can include forming a via opening in the first ILD layer below one or more of the trench openings in the first set of trench openings. The through hole openings may be referred to as a first set of through hole openings.

Figure 8E shows a portion of the first ILD layer 802 in the opening 810c being The IC structure 800 is removed to form a via opening.

At block 712, method 700 can include forming a metal (eg, metallization) in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist.

Figure 8F shows an IC structure 800 having a metal 814 formed in openings 810a-c.

At block 714, method 700 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the portion of the sacrificial layer below the remaining portions of the hard mask layer removed to form the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

FIG. 8G illustrates an IC structure 800 having openings 816a-d in the sacrificial layer 806.

At block 716, method 700 can include forming a via opening in the first ILD layer below one or more of the trench openings in the second set of trench openings. The through hole openings may be referred to as a second set of through hole openings.

FIG. 8H illustrates an IC structure 800 in which a portion of the first ILD layer 802 is removed in the opening 816b to form a via opening.

At block 718, method 700 can include forming (eg, depositing or filling) a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. As will be further below Illustratively, the second sacrificial material can be used as a mask (eg, a hard mask) that recesses the metal in the first set of trench openings, and can be tolerated in block 720 for use in The metal recessed process (eg, not removed by the process). For example, the second sacrificial material may comprise a spin-on dielectric such as CDO, or an amorphous carbon, or a transition metal nitride or oxide.

FIG. 8I illustrates an IC structure 800 having a second sacrificial material 818 disposed in one of the openings 816a-d.

At block 720, method 700 can include recessing the metal disposed in the first set of trench openings. For example, the top of the metal in the first set of trench openings can be removed by an etch process. The metal can be recessed to a height below the top surface of the sacrificial layer. The second sacrificial material protects the first ILD layer from the etching process.

8J illustrates an IC structure 800 in which the metal 814 in the openings 810a-c is recessed to a lower level than the top surface of the sacrificial layer 806.

At block 722, method 700 can include forming a first hard mask material on the recessed metal in the first set of trench openings. The top surface of the IC structure can then be ground while the spacers are removed.

FIG. 8K illustrates an IC structure 800 in which a first hard mask material 820 is disposed on metal 814 and the top surface is ground to remove the spacers 812.

At block 724, method 700 can include removing the second sacrificial material from the second set of trench openings and the second set of via openings. FIG. 8L illustrates the IC structure 800 with the second sacrificial material 818 removed from the openings 816a-d.

At block 726, method 700 can include: opening the second set of trenches A metal is formed in the opening and the opening of the second set of through holes. Figure 8M shows an IC structure 800 having a metal 814 disposed in the openings 816a-d.

At block 728, method 700 can include recessing the metal disposed in the second set of trench openings. For example, the top of the metal in the second set of trench openings can be removed by an etch process. The 8N figure shows the IC structure 800 that recesses the metal 814 in the openings 816a-d.

At block 730, method 700 can include forming a second hard mask material on the metal in the second set of trench openings. The second hard mask material may be deposited in an overfill condition, and then the second hard mask material is ground to make the top surface of the second hard mask material and the first hard mask material and/or Or the top surface of the sacrificial layer is substantially coplanar. The second hard mask material can have a different etch selectivity than the first hard mask material, and can be independent of the first hard mask material (eg, without etching to the first hard In the case of a masking material, the second hard mask material is etched.

FIG. 8O shows an IC structure 800 having a second hard mask material 822 disposed on metal 814 in openings 816a-d.

At block 732, method 700 can include removing (such as between the trenches) the sacrificial layer. After removing the sacrificial layer, the first ILD layer between the trenches may be exposed. FIG. 8P illustrates an IC structure 800 in which the sacrificial layer 806 is removed and the first ILD layer 802 between the trenches formed by the metal 814 is exposed.

At block 734, method 700 can include forming a second ILD layer on the first ILD layer between the trenches. Can be formed and/or recessed The second ILD layer has a top surface of the second ILD layer substantially coplanar with a top surface of the trenches. Alternatively, the top surface of the second ILD layer can be higher than the top surface of the trenches. As will be further explained in this specification, the second ILD layer can be more porous than the first ILD layer.

The 8Q diagram shows an IC structure 800 having a second ILD layer 824 disposed on a first ILD layer 802 between the trenches formed by the metal 814.

At block 736, method 700 can include forming a third hard mask material on the second ILD layer. The third hard mask material can have a different etch selectivity than the first and/or second hard mask material, and can be etched regardless of the first and/or second hard mask material ( For example, removing the third hard mask material.

FIG. 8R illustrates an IC structure 800 having a third hard mask material 826 disposed on the second ILD layer 824. The hard mask materials 820, 822, and 826 can help form an electrically conductive connection between each subsequent layer of the IC structure 800 and the trenches, and avoid the formation of unwanted conductive connections between adjacent trenches (eg, Short circuit). For example, the hard mask material 820 can be removed, but the hard mask materials 822 and 826 are not removed to enable the formation of an electrically conductive connection with the trenches in the openings 810a-c, and the hard mask materials 822 and 826 Contact to the grooves in openings 816a-d is blocked. The second hard mask material 822 can then be removed to enable an electrically conductive connection to the trenches in the openings 816a-d.

9A and 9B are diagrams showing the use of a process for using a plurality of hard mask materials on the trenches and/or spacers, in accordance with various embodiments. A flow chart of another method 900 of forming an IC structure having a replacement ILD layer. The method 900 also uses a dual metallization process similar to the method 500 and/or method 700 of the dual metallization process. 10A-10R are schematic cross-sectional side views of an IC structure 1000 at various stages of method 900, in accordance with various embodiments. Accordingly, method 900 will be described hereinafter with reference to Figures 10A-10R. Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 10A-10R. In some embodiments, IC structure 1000 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

In method 900, a portion of the first ILD layer (eg, the top that may be damaged by other operations of method 900) may be removed. In some embodiments, the sacrificial layer can include a hard mask material that facilitates a wet cleaning of method 900.

At block 902, method 900 can include providing a first ILD layer disposed on a lower layer, a sacrificial layer disposed on the first ILD layer, and a first one disposed on the sacrificial layer One of the hard mask layers of the IC structure. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above. The sacrificial layer can comprise a first sacrificial material. In some embodiments, the first sacrificial material can be a wet-cleanable hard mask material. For example, the first sacrificial material may be an oxide or nitride of a transition metal such as titanium nitride (TiN).

FIG. 10A illustrates a first ILD layer 1002 formed on a lower layer 1004, and a sacrificial layer formed on the first ILD layer 1002. 1006, and an IC structure 1000 of a hard mask layer 1008 formed over the sacrificial material.

At block 904, method 900 can include etching portions of the hard mask layer and forming openings in the hard mask layer. FIG. 10B illustrates an IC structure 1000 that forms openings 1010a-c by etching portions of the hard mask layer 1008.

At block 906, method 900 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

FIG. 10C illustrates an IC structure 1000 having spacers 1012 disposed on the sides of the openings 1010a-c.

At block 908, method 900 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, the openings between the spacers may be recessed through the sacrificial layer and recessed into the first ILD layer to form the trench openings. Thus, the sacrificial layer and a portion of the first ILD layer can be removed in a horizontal region defined by the openings between the ones.

10D shows that the openings 1010a-c between the spacers 1012 on the sides of each opening 1010a-c extend down to the first ILD layer 1002 and the openings 1010a-c thus extend The IC structure 1000 is below the top surface of the first ILD layer 1002.

At block 910, method 900 can include: opening the first set of trenches A via opening is formed in the first ILD layer below one or more of the trench openings. The through hole openings may be referred to as a first set of through hole openings. FIG. 10E illustrates an IC structure 1000 in which a portion of the first ILD layer 1002 is removed in the opening 1010c to form a via opening.

At block 912, method 900 can include forming a metal in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist. FIG. 10F illustrates an IC structure 1000 having a metal 1014 formed in openings 1010a-c.

At block 914, method 900 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the sacrificial layer and portions of the first ILD layer below the remaining portions of the hard mask layer are etched away (the remaining portions are also removed) And forming the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

FIG. 10G illustrates an IC structure 1000 having openings 1016a-d (eg, openings 1016a-d extending below the top surface of first ILD layer 1002) extending into sacrificial layer 1006 of first ILD layer 1002.

At block 916, method 900 can include forming a via opening in the first ILD layer below one or more of the trench openings in the second set of trench openings. The through hole openings may be referred to as a second set of through hole openings. FIG. 10H illustrates an IC structure 1000 in which a portion of the first ILD layer 1002 is removed in the opening 1016b to form a via opening.

At block 918, method 900 can include forming a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. As will be explained further below, the second sacrificial material can be used as a mask (eg, a hard mask) that recesses the metal in the first set of trench openings and can withstand block 920. The process used to recess the metal (eg, not removed by the process). For example, the second sacrificial material can comprise a dielectric or a carbon-based material.

FIG. 10I illustrates an IC structure 1000 having a second sacrificial material 1018 disposed in one of the openings 1016a-d.

At block 920, method 900 can include recessing the metal disposed in the first set of trench openings. For example, the top of the metal in the first set of trench openings can be removed by an etch process. The metal can be recessed below the height of the sacrificial layer (eg, below the top surface of the first ILD layer).

FIG. 10J illustrates the IC structure 1000 in which the metal 1014 in the openings 1010a-c is recessed below the sacrificial layer 1006 and below the top surface of the first ILD layer 1002.

At block 922, method 900 can include forming a first hard mask material on the metal in the first set of trench openings. The top surface of the IC structure can then be ground while the spacers are removed.

FIG. 10K illustrates a first hard mask material 1020 disposed on the metal 1014 and the top surface being ground to remove the IC junction of the spacers 1012. Structure 1000.

At block 924, method 900 can include removing the second sacrificial material from the second set of trench openings and the second set of via openings.

FIG. 10L illustrates the IC structure 1000 with the second sacrificial material 1018 removed from the openings 1016a-d.

At block 926, method 900 can include forming a metal in the second set of trench openings and the second set of via openings.

FIG. 10M illustrates an IC structure 1000 having a metal 1014 disposed in the openings 1016a-d.

At block 928, method 900 can include recessing the metal disposed in the second set of trench openings. For example, the top of the metal in the second set of trench openings can be removed by an etch process. In some embodiments, the metal in the second set of trench openings can be recessed to a lower level than the top surface of the first ILD layer (eg, recessed to the first set of trench openings) The height of the metal is flat).

The 10N figure shows the IC structure 1000 that recesses the metal 1014 in the openings 1016a-d.

At block 930, method 900 can include forming a second hard mask material on the metal in the second set of trench openings. Depositing the second hard mask material in an overfill condition, and then grinding the second hard mask material such that the top surface of the second hard mask material and the first hard mask material and/or sacrificial layer The top surface is substantially coplanar. The second hard mask material can have a different etch selectivity than the first hard mask material, and can be independent of the first hard mask material (eg, without etching to the first hard cover In the case of a cover material, the second hard mask material is etched.

FIG. 10O illustrates an IC structure 1000 having a second hard mask material 1022 disposed on metal 1014 in openings 1016a-d.

At block 932, method 900 can include removing the sacrificial layer (such as between the trenches) and etching away the top of the first ILD layer below the sacrificial layer. For example, the portion of the first ILD layer below the sacrificial layer can be recessed to be substantially flush with a lower surface of the trenches. For example, the sacrificial layer can be removed by a wet cleaning process. For example, the top of the first ILD layer can be removed using a plasma etch. The top of the first ILD layer may be damaged by other operations of method 900, and removal of the top of the first ILD layer may improve the structure of the first ILD layer.

FIG. 10P illustrates the IC structure 1000 with the sacrificial layer 1006 removed and the top of the first ILD layer 1002 (eg, the portion between the trenches formed by the metal 1014) removed.

At block 934, method 900 can include forming a second ILD layer on the first ILD layer between the trenches. The second ILD layer can be formed and/or recessed such that a top surface of the second ILD layer is higher than a top surface of the trenches. Alternatively, the top surface of the second ILD layer can be substantially coplanar with the top surface of the trenches. As will be further explained in this specification, the second ILD layer can be more porous than the first ILD layer.

FIG. 10Q illustrates an IC structure 1000 having a second ILD layer 1024 disposed on a first ILD layer 1002 between the trenches formed by the metal 1014.

At block 936, method 900 can include: on the second ILD layer A third hard mask material is formed. The third hard mask material can have a different etch selectivity than the first and/or second hard mask material, and can be etched regardless of the first and/or second hard mask material ( For example, removing the third hard mask material.

FIG. 10R illustrates an IC structure 1000 having a third hard mask material 1026 disposed on the second ILD layer 1024. The IC structure 1000 shown in FIG. 10R can be similar to the IC structure 800 shown in FIG. 8R.

The operations of methods 300, 500, 700, and/or 900 are illustrated in the form of a plurality of discrete operations that are sequentially performed in a manner that is most helpful in understanding the scope of the claimed patent. However, the order of the description should not be interpreted as meaning that the operations are necessarily sequential. Embodiments of the present disclosure may be implemented to use any suitable hardware and/or software system configured as desired.

11 is a schematic illustration of an exemplary system (eg, a computing device 1100) that can include an IC structure (eg, IC structure 400, 600, 800) in accordance with certain embodiments. And/or 1000, and/or using methods 300, 500, 700, and/or 900 to form one of the IC structures). The various components of computing device 1100 can be disposed in a housing (eg, housing 1108). The motherboard 1102 can include some components including, but not limited to, a processor 1104 and at least one communication chip 1106. The processor 1104 can be physically and electrically coupled to the motherboard 1102. In some embodiments, the at least one communication chip 1106 can also be physically and electrically coupled to the motherboard 1102. In a further embodiment, the communication chip 1106 can be the processor 1104 portion.

Computing device 1100 can include other components that may or may not be physically and electrically coupled to motherboard 1102, depending on its application. These other components may include, but are not limited to, volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (ROM)), flash memory, graphics processing , digital signal processor, crypto processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, Global Positioning System (GPS) devices, compasses, Geiger counters, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, A component such as a compact disk (CD) and a large number of storage devices such as a digital versatile disk (DVD).

The communication chip 1106 is capable of performing wireless communication and transmitting data to and from the computing device 1100. The term "wireless" and its derivatives may be used to describe terms, circuits, systems, methods, techniques, communication channels, and the like that may utilize data transmitted by modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not contain any wires, but in some embodiments, such associated devices may not contain any wires. The communication chip 1106 can implement an Institute of Electrical and Electronics Engineers including, but not limited to, Wi-Fi (IEEE 802.11 series) and IEEE 802.16 standards (eg, IEEE 802.16-2005 Amendment) (Institute of Electrical and Electronic Engineers; IEEE) standards, Long-Term Evolution (LTE) and any amendments, updates, and/or revisions (eg, advanced LTE plans, Ultra Mobile Broadband; UMB) Any wireless standard or agreement in some wireless standards or protocols for amendments, updates, and/or revisions of the program (also known as 3GPP2). The Broadband Wireless Access (BWA) network, which is compatible with IEEE 802.16, is commonly referred to as the Worldwide Interoperability for Microwave Access (WiMAX) network and is an IEEE 802.16 standard. Certification mark for products for compliance and interoperability testing. The communication chip 1106 can be based on the Global System for Mobile communication (GSM), the General Packet Radio Service (GPRS), the Universal Mobile Telecommunications System (UMTS), and the high speed packet. It is operated by High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA for short), or LTE network. The communication chip 1106 can be based on the Global Data Communication System (Enhanced Data for GSM Evolution; EDGE), the GSM EDGE Radio Access Network (GERAN), and the global terrestrial radio access network. (Universal Terrestrial Radio Access Network; UTRAN for short) or Evolved UTRAN (E-UTRAN for short) . The communication chip 1106 can be based on code division multiple access (CDMA), time division multiple access (TDMA), and digital enhanced Cordless Telecommunications (DECT). , Evolution-Data Optimized (EV-DO), derivative standards or agreements for the above, and any other wireless protocols known as 3G, 4G, 5G, and newer generations. In other embodiments, the communication chip 1106 can operate in accordance with other wireless protocols.

Computing device 1100 can include a plurality of communication chips 1106. For example, a first communication chip 1106 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 1106 can be dedicated to applications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. Long-distance wireless communication, such as EV-DO, and other wireless communication standards.

The processor 1104 of the computing device 1100 can comprise an IC structure (eg, IC structures 400, 600, 800, and/or 1000, and/or methods of use 300, 500, 700, and/or 900) as described herein. One of the IC structures) (for example, the die 102 of Figures 1-2). For example, the die 102 of Figures 1-2 can be mounted in a package assembly that can be mounted on a circuit board such as the motherboard 1102. The term "processor" may mean any device that processes electronic data from a register and/or memory and converts the electronic data into other electronic data that can be stored in a register and/or memory or One part of the device.

The communication chip 1106 can also include an IC having an IC structure (eg, IC structure 400, 600, 800, and/or 1000, and/or using methods 300, 500, 700, and/or 900) as described herein. One of the grains of the structure (for example, the die 102 of Figures 1-2). In further embodiments, another component (eg, a memory device or other integrated circuit device) disposed within computing device 1100 can include an IC structure (eg, IC structure 400, 600) as described herein. One of the dies of 800, and/or 1000, and/or an IC structure formed using methods 300, 500, 700, and/or 900 (eg, die 102 of Figures 1-2).

In various embodiments, the computing device 1100 can be a mobile computing device, a laptop, a simple notebook, a notebook, an ultra-thin laptop, a smart phone, a tablet, and a personal digital assistant (Personal Digital Assistant; PDA), super mobile PC, mobile phone, desktop, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video machine. In a further embodiment, computing device 1100 can be any other electronic device for processing data.

Some non-limiting examples are provided below.

Example 1 is a method of fabricating an integrated circuit (IC) structure, the method comprising: providing a stack comprising a first interlayer dielectric (ILD) layer disposed on a lower layer and including a a dielectric material, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer; forming a trench opening in the sacrificial layer, and Forming via openings in an ILD layer; forming a metal in the trench openings and the via openings to form respective trenches and vias; removing the sacrificial layer; and A second ILD layer is formed on the first ILD layer.

Example 2 is the method of Example 1, wherein the second ILD layer has a higher porosity than the first ILD layer.

Example 3 is the method of example 1, wherein forming the metal in the trench openings comprises depositing the metal on the first ILD layer.

Example 4 is the method of Example 1, wherein the sacrificial layer comprises a wet cleanable dielectric or a wet cleanable hard mask.

Example 5 is the method of any one of examples 1 to 4, wherein forming the trench openings and via openings and forming the metal in the trench openings and the via openings comprises: forming a first set of trenches a slot opening and a first set of through hole openings; forming a metal in the first set of trench openings and the first set of via openings to form a first set of trenches and a second set of trenches; After forming the metal in the trench opening and the first set of via openings, forming a second set of trench openings and a second set of via openings, wherein each trench opening of the second set of trench openings is associated with the sacrifice Forming a metal between the openings of the first set of trench openings in the layer; and forming a metal in the second set of trench openings and the second set of via openings to form a second set of trenches and a second set of vias .

Example 6 is the method of example 5, further comprising: forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the second The hard mask material has a different etch selectivity than the first hard mask material.

Example 7 is the method of example 6, further comprising: forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material has The first and second hard mask materials have different etch selectivity.

Example 8 is the method of example 1, wherein the trench openings extend below a top surface of the first ILD layer.

Example 9 is the method of example 1, wherein the first ILD layer has a different material composition than the second ILD layer.

Example 10 is an integrated circuit (IC) comprising: a first interlayer dielectric (ILD) layer disposed on a lower layer; a plurality of trenches disposed on the first ILD layer; a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches; wherein the second ILD layer has a lower dielectric constant than the first ILD layer.

Example 11 is the IC of Example 10, further comprising: a plurality of vias extending from the respective trenches to the underlying layer via the first ILD layer.

Example 12 is the IC of Example 10, wherein the top surface of the first ILD layer is substantially flat.

Example 13 is the IC of Example 10, wherein the second ILD layer has more holes than the first ILD layer.

Example 14 is the IC of Example 10, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches.

Example 15 is the IC of Example 10, wherein the first ILD layer has a different material composition than the second ILD.

Example 16 is a computing device comprising: a circuit board; a crystal The grain, the front face of the die is coupled to the board. The die includes: a first interlayer dielectric (ILD) layer disposed on a lower layer, wherein the first ILD layer includes a first dielectric material; and is disposed on the first ILD layer a plurality of trenches; and a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches, wherein the second ILD layer comprises more than the first dielectric material a second dielectric material of the aperture.

Example 17 is the computing device of example 16, wherein the interconnect layer further comprises a plurality of vias extending from the respective trenches to the lower layer via the first ILD layer.

Example 18 is the computing device of Example 16, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches.

Example 19 is the computing device of Example 16, wherein the first dielectric material has a different material composition than the second dielectric material.

Example 20 is the computing device of any one of examples 16 to 19, wherein: the die is a processor; and the computing device comprises an antenna, a display, a touch screen display, and a touch screen Controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker And one of the one or more of the cameras in the mobile computing device.

Embodiments may include any suitable combination of the embodiments previously described herein including alternative embodiments of the embodiments described above in the form of conjunctions (e.g., "and" may be "and/or"). Moreover, certain embodiments may include one or more articles (eg, non-transitory computer readable media) The one or more articles have instructions stored therein that, when executed, will result in the actions of any of the embodiments described above. Moreover, some embodiments may include apparatus or systems having any suitable means for performing the various operations of the embodiments described above.

The description of the illustrated embodiments of the present invention is not intended to be exhaustive or to limit the invention. While the invention has been described with respect to the specific embodiments and examples of the invention, it will be understood by those skilled in the art that various equivalent modifications can be made within the scope of the invention.

These modifications of the disclosed embodiments of the present invention can be made in accordance with the above detailed description. The terms used in the scope of the claims are not to be construed as limited to the particular embodiments disclosed herein. Rather, the scope of the present invention will be determined by the scope of the final application of the invention, which is to be interpreted in the light of the claims.

Claims (20)

A method for fabricating an integrated circuit (IC) structure, comprising: providing a stack comprising a first interlayer dielectric (ILD) layer disposed on a lower layer and comprising a dielectric material a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer; forming a trench opening in the sacrificial layer, and forming a pass in the first ILD layer a hole opening; forming a metal in the trench opening and the via opening to form respective trenches and vias; removing the sacrificial layer; and the first ILD between the trenches A second ILD layer is formed on the layer. The method of claim 1, wherein the second ILD material has a higher porosity than the first ILD material. The method of claim 1, wherein forming the metal in the trench openings comprises depositing the metal on the first ILD layer. The method of claim 1, wherein the sacrificial layer comprises a wet cleanable dielectric or a wet cleanable hard mask. The method of claim 1, wherein forming the trench openings and the via openings and forming the metal in the trench openings and the via openings comprises: forming a first set of trench openings and first a through hole opening; forming a gold in the first group of groove openings and the first group of through hole openings Generating to form a first set of trenches and a second set of trenches; forming a second set of trench openings and a second set after forming the metal in the first set of trench openings and the first set of via openings a via opening, wherein the trench opening of the second set of trench openings is spaced apart from the opening of the first set of trench openings in the sacrificial layer; and the second set of trench openings and the second set of via openings A metal is formed in the middle to form a second set of trenches and a second set of vias. The method of claim 5, further comprising: forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the The second hard mask material has a different etch selectivity than the first hard mask material. The method of claim 6, further comprising: forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material There is an etch selectivity different from the first and second hard mask materials. The method of claim 1, wherein the trench openings extend below a top surface of the first ILD layer. The method of claim 1, wherein the first dielectric material has a different material composition than the second dielectric material. An integrated circuit (IC) comprising: a first interlayer dielectric (ILD) layer disposed on a lower layer; a plurality of trenches disposed on the first ILD layer; a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches, wherein the second ILD layer has a lower dielectric constant than the first ILD layer. The IC of claim 10, further comprising a plurality of via holes extending from the respective trenches to the lower layer via the first ILD layer. The IC of claim 10, wherein the top surface of the first ILD layer is substantially flat. The IC of claim 10, wherein the second ILD layer has more holes than the first ILD layer. The IC of claim 10, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches. The IC of claim 10, wherein the first ILD layer has a different material composition than the second ILD layer. A computing device comprising: a circuit board; and a die having a front face coupled to the circuit board, the die having an interconnect layer, the interconnect layer comprising: being disposed on a lower layer a first interlayer dielectric (ILD) layer, the first ILD layer comprising a first dielectric material; a plurality of trenches disposed on the first ILD layer; and being disposed in the plurality of trenches a second ILD layer on the first ILD layer between the trenches, wherein the second ILD layer comprises a second dielectric material having more holes than the first dielectric material. A computing device as claimed in claim 16, wherein the interconnection The layer further includes a plurality of vias extending from the respective trenches to the underlying layer via the first ILD layer. The computing device of claim 16, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches. The computing device of claim 16, wherein the first dielectric material has a different material composition than the second dielectric material. The computing device of claim 16, wherein: the die is a processor; and the computing device comprises an antenna, a display, a touch screen display, a touch screen controller, a battery , an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera One or more of the mobile computing devices.