CN107863318A - Integrated circuit patterns and forming method based on pitch-multiplied formation - Google Patents
Integrated circuit patterns and forming method based on pitch-multiplied formation Download PDFInfo
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- CN107863318A CN107863318A CN201711173929.4A CN201711173929A CN107863318A CN 107863318 A CN107863318 A CN 107863318A CN 201711173929 A CN201711173929 A CN 201711173929A CN 107863318 A CN107863318 A CN 107863318A
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- 238000000034 method Methods 0.000 title claims abstract description 96
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims description 56
- 238000002347 injection Methods 0.000 claims description 51
- 239000007924 injection Substances 0.000 claims description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000007788 liquid Substances 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 239000012528 membrane Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000003079 width control Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 47
- 239000002344 surface layer Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 18
- 230000008569 process Effects 0.000 abstract description 10
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- 238000003384 imaging method Methods 0.000 abstract description 3
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- 150000002500 ions Chemical class 0.000 description 60
- 238000005755 formation reaction Methods 0.000 description 21
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- 238000010586 diagram Methods 0.000 description 12
- 238000002360 preparation method Methods 0.000 description 7
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- 238000012986 modification Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
Abstract
The present invention provides one kind based on pitch-multiplied formation integrated circuit patterns and forming method, including：Semiconductor base is provided, forms patterned mask structure sheaf, including some mask cells with the first gap thereon；The sidepiece that the first gap is revealed in mask cell carries out ion doping, forms doping and does not carry out the intrinsic portion of ion doping, the etch rate of doping is different from intrinsic portion；Deposition intrinsic pattern auxiliary layer, fill the first gap between mask cell；Specific etching selection ratio is used to perform etching to form the second gap on a semiconductor substrate, selected from the one kind removed in doping and the intrinsic portion of removal and intrinsic pattern auxiliary layer, the second gap is less than the first gap.By such scheme, pattern formation method provided by the invention, solve the problems, such as that existing exposure imaging technology is limited and complex process, based on special pitch multiplication techniques, using patterned mask structure sheaf and intrinsic pattern auxiliary layer, the patterning of line footpath micro is obtained, technique is simple.
Description
Technical field
The invention belongs to ic manufacturing technology field, more particularly to a kind of integrated electricity based on pitch-multiplied formation
Road pattern and the formation integrated circuit patterns method.
Background technology
At present, many factors, such as demand to increased portability, computing capability, memory span and energy efficiency,
Constantly make integrated circuit more dense.Be steadily decreasing to be formed integrated circuit constitutive characteristic (for example, electric installation and
Interconnection line) size to promote this bi-directional scaling.
In order that obtain integrated circuit more crypto set to increase portability, computing capability and the characteristic of memory capacity, not
Disconnected make integrated circuit more crypto set, by the conductor wire for reducing the size and memory cell that form memory cell electric installation
Size, storage arrangement can be made to diminish, in addition, can be by assembling more memories on the given area in storage arrangement
Unit increases memory capacity.
However, the continuous reduction of feature sizes proposes higher and higher requirement to the technology for forming the feature, by
In the factor such as optics and light or radiation wavelength, optical lithography techniques each have minimum spacing, special less than this minimum spacing
Determining optical lithography techniques just can not be reliably formed feature.Therefore, the minimum spacing of optical lithography techniques is big to continuous feature
The obstacle of small reduction.In addition, integrated circuit is generally also containing each come what is formed by conventional pitch multiplication technique with that can be difficult to
The feature of kind form and dimension, the lasting reduction of integrated circuit size provide the constant demand of the reduction to feature sizes, lead to
Often, the problems such as some existing techniques to form complexity, be difficult to control there is its pattern.
Therefore, how a kind of integrated circuit patterns based on pitch-multiplied formation are provided and forms the integrated circuit patterns
Method, it is necessary with solving the problems such as technique reaches physics limit and preparation technology complexity in the prior art.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of based on pitch-multiplied formation
Integrated circuit patterns and forming method, for solving that technique physics limit in the prior art is limited and formation process complexity etc. is asked
Topic.
In order to achieve the above objects and other related objects, the present invention provides one kind and is based on pitch-multiplied formation integrated circuit diagram
The method of case, comprises the following steps：
1) semiconductor substrate is provided, and in forming a patterned mask structure sheaf, the pattern on the semiconductor base
Mask structure layer includes several mask cells, and has the first gap between the mask cell；
2) sidepiece that first gap is revealed in the mask cell carries out ion doping, makes the mask cell
Sidepiece is formed as doping, and the mask cell separately has and do not carry out the intrinsic of ion doping by what the doping coated
Portion, the doping have different etch rates from the intrinsic portion；
3) an intrinsic pattern auxiliary layer is deposited on the semiconductor base, and the intrinsic pattern auxiliary layer is at least filled
First gap between the mask cell；And
4) structure obtained using specific etching selection comparison step 3) is performed etching, to be formed in the semiconductor base
On the second gap, the forming method in second gap include selected from remove the doping and retain the intrinsic portion and
The intrinsic pattern auxiliary layer combines for mask pattern, and removes the intrinsic portion and the intrinsic pattern auxiliary layer and reservation
The doping be mask pattern amendment the two one of them, so as to form the integrated circuit patterns, described second
Gap is located in the integrated circuit patterns and is less than first gap.
As a preferred embodiment of the present invention, the top progress ion of the mask cell is mixed simultaneously in step 2)
It is miscellaneous.
As a preferred embodiment of the present invention, in step 2), in the mask cell by way of ion implanting
Side carries out ion doping, specifically includes：
First time ion implanting is carried out with first angle to the patterned mask structure sheaf, with each mask cell
First side forms the first injection region；And
Second of ion implanting is carried out with second angle to the patterned mask structure sheaf, with each mask cell
Second side forms second injection region relative with first injection region.
As a preferred embodiment of the present invention, the first angle and the second angle are according to the adjacent mask
The depth-to-width ratio setting for the groove that first gap between unit is formed, needs are reached with control injection ion and injected
Region, so as to form first injection region and second injection region.
As a preferred embodiment of the present invention, the semiconductor base is in first direction and tilt progress described first
Secondary ion injects, and rotates the semiconductor base to second direction and tilts progress second of ion implanting, and described first
Direction and the differential seat angle of the second direction are 180 °, and the first angle is equal with the second angle.
As a preferred embodiment of the present invention, in step 2), in the mask cell by way of ion implanting
Top carries out ion doping, more specifically includes：Third time ion implanting is carried out with third angle to the patterned mask structure sheaf,
With the top of each mask cell formed the 3rd injection region, wherein, first injection region, second injection region and
3rd injection region forms the doping, and not ion implanted region forms the intrinsic portion in the mask cell.
As a preferred embodiment of the present invention, in step 2), ion doping is carried out by way of diffusion, specific bag
Include：
2-1) one layer of photoresist layer, or the photoetching retained based on front and continued technique are formed in the patterned mask structure layer surface
Glue-line, in a manner of rectilinear ion implanting to corresponding to the semiconductor substrate surface region carry out ion implanting, with
The sidepiece that each mask cell is revealed in the gap forms edge doped region；
2-2) to step 2-1) obtained by structure make annealing treatment, be diffused the edge doped region, with shape
Into the doping, and the region without diffusion forms the intrinsic portion in each mask cell, and removes remaining described
Photoresist layer.
As a preferred embodiment of the present invention, in step 2), ion doping is carried out by way of diffusion, specific bag
Include：The structure that step 1) is obtained is placed in a reaction chamber, and impurity gas is passed through into the reaction chamber and is annealed
Processing, to form the doping at the top of the mask cell and sidepiece, the area without diffusion in each mask cell
Domain forms the intrinsic portion.
As a preferred embodiment of the present invention, in step 3), the step of forming the intrinsic pattern auxiliary layer, includes：
3-1) surface of the structure obtained in step 2) deposits one layer of sacrificial material layer, and the sacrificial material layer is located at each institute
State the top of mask cell and side wall and coat each mask cell；
Described in 3-2) at least being removed on each mask cell top surface by cmp or etching technics
Sacrificial material layer, to obtain being filled in the intrinsic pattern auxiliary layer between each mask cell in gap.
As a preferred embodiment of the present invention, the material of the intrinsic pattern auxiliary layer includes photoresist or oxidation
Silicon.
As a preferred embodiment of the present invention, each mask cell in step 1) it is parallel and it is equidistant interval row
Cloth, the width control system in the middle intrinsic portion formed of step 2) is between described first between matching the adjacent mask cell
Gap.
The doping is removed as a preferred embodiment of the present invention, in step 4) and retains the intrinsic portion and described
Intrinsic pattern auxiliary layer, the intrinsic pattern auxiliary layer of reservation include several intrinsic pattern auxiliary layer units, methods described
Also include step 5)：The intrinsic pattern auxiliary layer unit is modified, so that the width of the intrinsic pattern auxiliary layer unit is equal to
The width in the intrinsic portion, and cause the spacing phase between each adjacent intrinsic pattern auxiliary layer unit and the intrinsic portion
Deng.
As a preferred embodiment of the present invention, in step 1), also it is included in the semiconductor base and is covered with the pattern
The step of one layer of mask layer is formed between membrane structure layer, wherein, methods described also includes step 5)：Step 4) is obtained
Integrated circuit patterns are transferred on the mask layer, to obtain a mask layer, wherein, the mask layer is partly led as described
The mask of body substrate continues to etch.
As a preferred embodiment of the present invention, the material of the mask layer includes silicon nitride, the intrinsic pattern
The material of auxiliary layer includes silica.
As a preferred embodiment of the present invention, the semiconductor base in step 1) includes substrate and positioned at the lining
Stacked gate architectures on bottom, wherein, the stacked gate architectures include：Positioned at the grid oxic horizon of the substrate surface；Position
In the polysilicon layer of the gate oxidation layer surface；And the metal level positioned at the polysilicon layer surface.
As a preferred embodiment of the present invention, in step 4), the etching liquid that specific etching selection ratio includes using is to institute
The etch rate for stating intrinsic portion and the intrinsic pattern auxiliary layer is all higher than the etching liquid to the doping etch rate
10 times；Or the etching liquid used is more than etch rate of the etching liquid to the intrinsic portion to the etch rate of the doping
10 times and more than 10 times to the etch rate of the intrinsic pattern auxiliary layer.
As a preferred embodiment of the present invention, when the removal doping in step 4) and retain the intrinsic portion and institute
When stating intrinsic pattern auxiliary layer, the material of patterned mask structure sheaf described in step 1) includes polysilicon.
As a preferred embodiment of the present invention, when the removal intrinsic portion and the intrinsic pattern auxiliary layer in step 4)
And when retaining the doping, the material of patterned mask structure sheaf described in step 1) includes silica.
The present invention provides a kind of integrated circuit patterns based on pitch-multiplied formation, including：
Semiconductor substrate；
Patterned mask structure sheaf, it is formed on the semiconductor base, the patterned mask structure sheaf is covered including several
Film unit, and there is the first gap between the mask cell, the mask cell has the intrinsic portion for not carrying out ion doping
And be revealed in first gap and be covered in the top in the intrinsic portion and the doping of side wall, wherein, the doping
Etch rate it is different from the etch rate in the intrinsic portion；And
Intrinsic pattern auxiliary layer, the intrinsic pattern auxiliary layer fill first gap between the mask cell and
Including several intrinsic pattern auxiliary layer units, wherein, the second gap is formed on the semiconductor base, second gap
Generation include retaining selected from the intrinsic portion and intrinsic pattern auxiliary layer unit, the adjacent intrinsic portion and described
Produce second gap between intrinsic pattern auxiliary layer unit, and the doping retains, same mask cell it is described
Produced between doping second gap the two one of them.
As a preferred embodiment of the present invention, the semiconductor base includes substrate and the stacking on the substrate
Grid structure, wherein, the stacked gate architectures include：Positioned at the grid oxic horizon of the substrate surface；Positioned at the grid
Aoxidize the polysilicon layer of layer surface；And the metal level positioned at the polysilicon layer surface.
As a preferred embodiment of the present invention, the material of the intrinsic pattern auxiliary layer, which includes, is selected from photoresist
One of with silica；When the material of the patterned mask structure sheaf includes polysilicon, the intrinsic portion and described intrinsic
Pattern auxiliary layer retains.
As a preferred embodiment of the present invention, the material of the intrinsic pattern auxiliary layer, which includes, is selected from photoresist
One of with silica；When the material of the patterned mask structure sheaf includes silica, the doping retains.
As described above, the integrated circuit patterns and forming method based on pitch-multiplied formation of the present invention, have with following
Beneficial effect：
The forming method of multiple spacing exposing patterns provided by the invention, effectively solves existing exposure imaging technology
The problem of limited and preparation technology complexity, the semiconductor pattern structure of line footpath micro can be obtained, based on special pitch-multiplied
(pitch doubling) technology, using patterned mask structure sheaf and intrinsic pattern auxiliary layer, integrated circuit feature can be reduced
The size of size, so as to form required integrated circuit patterns structure, technique is simple, is not easy, by ectocine, to obtain pattern
Accurate size, it is easily controllable；The structures and methods of the present invention can make integrated circuit more crypto set, and storage is formed by reducing
The size of the size of device unit electric installation and the conductor wire of memory cell, can make storage arrangement diminish, in addition, can be by depositing
More memory cells are assembled on given area in reservoir device to increase memory capacity.
Brief description of the drawings
Fig. 1 is shown as the process chart that the present invention forms the method for integrated circuit patterns.
Fig. 2 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for providing semiconductor base.
Fig. 3 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for forming patterned mask structure sheaf.
Fig. 4 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for forming doping and intrinsic portion.
Fig. 5 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for forming intrinsic pattern auxiliary layer.
Fig. 6 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for forming sacrificial material layer.
Fig. 7 is shown as the present invention and forms in the method for integrated circuit patterns the schematic diagram for etching removal doping.
Fig. 8 is shown as the present invention and formed in the method for integrated circuit patterns to remove showing for intrinsic portion and intrinsic pattern auxiliary layer
It is intended to.
Fig. 9 is shown as the present invention and forms in the method for integrated circuit patterns the structural representation for forming mask layer.
Figure 10 is shown as forming circuit pattern on mask layer in the method for present invention formation integrated circuit patterns
Schematic diagram.
Figure 11 is shown as the present invention and forms in the method for integrated circuit patterns the structural representation for forming mask layer.
Figure 12 is shown as the present invention and forms in the method for integrated circuit patterns the structure that doping is formed by ion implanting
Schematic diagram.
Figure 13 is shown as the patterned mask structure sheaf that a kind of mode is formed in the method for present invention formation integrated circuit patterns
Schematic diagram.
Figure 14 is shown as being formed the structural representation for the intrinsic pattern auxiliary layer for needing to modify after etching Figure 13 structures.
A kind of structure for semiconductor base that Figure 15 is shown as providing in the method for present invention formation integrated circuit patterns is shown
It is intended to.
Component label instructions
11 semiconductor bases
111 substrates
112 grid oxic horizons
113 polysilicon layers
114 metal levels
115 grid protection layers
12 patterned mask structure sheafs
121 mask cells
122 first gaps
123 second gaps
13 intrinsic portions
14 doping
15 intrinsic pattern auxiliary layers
151 intrinsic pattern auxiliary layer units
16 sacrificial material layers
17 mask layers
18 mask layers
19 Doped ions
S1~S4 steps 1)~step 4)
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 15.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
As shown in figure 1, the present invention provides a kind of method based on pitch-multiplied formation integrated circuit patterns, including following step
Suddenly：
1) semiconductor substrate is provided, and in forming a patterned mask structure sheaf, the pattern on the semiconductor base
Mask structure layer includes several mask cells, and has the first gap between the mask cell；
2) sidepiece that first gap is revealed in the mask cell carries out ion doping, makes the mask cell
Sidepiece is formed as doping, and the mask cell separately has and do not carry out the intrinsic of ion doping by what the doping coated
Portion, the doping have different etch rates from the intrinsic portion；
3) an intrinsic pattern auxiliary layer is deposited, and the intrinsic pattern auxiliary layer is at least filled between the mask cell
First gap；And
4) structure obtained using specific etching selection comparison step 3) is performed etching, to be formed in the semiconductor base
On the second gap, the forming method in second gap include selected from remove the doping and retain the intrinsic portion and
The intrinsic pattern auxiliary layer combines for mask pattern, and removes the intrinsic portion and the intrinsic pattern auxiliary layer and reservation
The doping be mask pattern amendment the two one of them, so as to form integrated circuit patterns, second gap
In the integrated circuit patterns and it is less than first gap.
The method based on pitch-multiplied formation integrated circuit patterns of the present invention is discussed in detail below in conjunction with accompanying drawing.
As shown in the S1 in Fig. 1 and Fig. 2~3, step 1) is carried out first, there is provided semiconductor substrate 11, and in described half
A patterned mask structure sheaf 12 is formed in conductor substrate 11, the patterned mask structure sheaf 12 includes several mask cells 121,
And there is the first gap 122 between the mask cell 121；
Specifically, the semiconductor base 11 selects according to actual demand, can be that any needs are further etched
Structure, such as can be grid structure to be formed structure sheaf, it can be layer of material layer, or two layers and more than
The laminated material bed of material, be not particularly limited herein.In addition, the patterned mask knot formed on the surface of semiconductor base 11
Structure layer 12 will subsequently form required patterning by special pitch-multiplied (pitch doubling) technology, wherein, shape
Into integrated circuit patterns can apply in device preparation technology, in such as AA, CELL, BL and WL preparation technology, institute
Size, shape, quantity and arrangement of the mask cell 121 in patterned mask structure sheaf 12 etc. is stated according to actual demand
Selection, it is preferable that in the present embodiment, each evenly sized shape identical unit of mask cell 121, each mask list
Member 121 is parallel and is equidistantly intervally arranged.
In addition, when the semiconductor base 11 is the structure sheaf of grid structure to be formed, the adjacent mask cell 121
Between gap influence the corresponding area of grid to be etched formation, wherein, spacing between each mask cell 121 can be with
Equal to the width of each mask cell 121, the two can not also wait, be not particularly limited herein, can be according to the present invention
Integrated circuit patterns forming method obtain want etch semiconductor substrates 11 mask structure.
Specifically, the material of the patterned mask structure sheaf 12 can be polysilicon, or oxide (Oxide),
Such as silica, forming the method for the patterned mask structure sheaf 12 includes：One layer of figure is formed in the surface of semiconductor base 11
The material layer of case mask structure layer 12, then it is performed etching using photoresist as mask, it is preferable that also include modifying it
The step of, after the completion of etching, remaining photoresist layer can be removed before subsequent technique, be also used as in subsequent technique
Mask Rotating fields, selected according to actual process.
As shown in figure 15, as an example, in step 1), the semiconductor base 11 includes substrate 111 and positioned at substrate
Stacked gate architectures on 111, the stacked gate architectures include：Grid oxic horizon 112 positioned at the surface of substrate 111；
Polysilicon layer 113 positioned at the surface of grid oxic horizon 112；And the metal level positioned at the surface of polysilicon layer 113
114。
As an example, one layer of diffusion impervious layer is also formed between the polysilicon layer 113 and the metal level 114；It is described
The surface of metal level 114 also forms one layer of grid protection layer 115.
Specifically, the substrate 111 can be ripe for those of ordinary skill in the art such as silicon substrate, silicon-on-insulator substrates
Any substrate known, the grid oxic horizon 112 include but is not limited to silica；The metal level 114 includes but is not limited to
Metal tungsten layer；The diffusion impervious layer includes but is not limited to titanium nitride layer, as the diffusion between tungsten metal layer and polysilicon layer
Barrier layer；The grid protection layer 115 includes but is not limited to silicon nitride layer, for protecting grid structure, as being subsequently formed
When stating doping 14, diffusion ion accumulation scattering is unlikely to cause damage to grid structure.
As shown in the S2 in Fig. 1 and 4 and Figure 11, step 2) is carried out, being revealed in described first to the mask cell 121
The sidepiece of gap carries out ion doping, the sidepiece of the mask cell 121 is formed as doping 14, and the mask cell 121
It is another that there is the intrinsic portion 13 for not carrying out ion doping coated by the doping 14, the doping 14 and the intrinsic portion 13
With different etch rates.
It should be noted that the processing by the step, two class formations are formd in each mask cell 121, one
Kind is undoped part, and referred to as intrinsic portion 13, a kind of is the structure after overdoping, referred to as doping 14, wherein, pass through
Doping 14 after doping and undoped intrinsic portion 13 simultaneously generate different etching selection ratios, may be such that described mix
Miscellaneous portion 14 is easier to be etched or is difficult to the doping 14 can be with addition, same etching mode be to two kinds of materials
Etch rate differ 1~20000 times, namely the ratio of etch rate, preferably 10~10000 times.In addition, formed
The doping 14 and the structure in the intrinsic portion 13, quantity etc. and actual demand selection.
The method for carrying out ion doping for the side of each mask cell 121, is described in detail below in conjunction with accompanying drawing,
Wherein, there is provided the following two kinds mode：
As shown in figure 12, the doping 14 is formed by the way of ion implanting, as an example, in step 2), is passed through
The mode of ion implanting carries out ion doping in the side of the mask cell 121, specifically includes：
First time ion implanting is carried out with first angle to the patterned mask structure sheaf 12, with each mask cell
121 first side forms the first injection region；And
Second of ion implanting is carried out with second angle to the patterned mask structure sheaf 12, with each mask cell
121 second side forms second injection region relative with first injection region.
As an example, ion doping is carried out to the top of the mask cell 121 simultaneously in step 2).
As an example, in step 2), in the top of the mask cell 121, progress ion is mixed by way of ion implanting
It is miscellaneous, more specifically include：Third time ion implanting is carried out with third angle to the patterned mask structure sheaf 12, described to be covered each
3rd injection region is formed on the top of film unit 121, wherein, first injection region, second injection region and the described 3rd
Injection region forms the doping 14, and not ion implanted region forms the intrinsic portion 13 in the mask cell.
Need what is illustrated, the purpose of the step be exactly by the patterned mask structure sheaf 12 is carried out from different directions from
Son injection, ensure that injection ion can reach the region of needs, and do not influence the intrinsic portion that need not be doped, so as to most
Reach needs eventually to be doped to change the region required for etching selection ratio.
As an example, the semiconductor base 11 is in first direction tilts the progress first time ion implanting, rotation
Turn the semiconductor base to second direction and tilt progress second of ion implanting, and the first direction and described second
The differential seat angle in direction is 180 °, and the first angle is equal with the second angle.
As an example, the ion beam direction of the third time ion implanting is perpendicular to the surface of semiconductor base 11.
Specifically, implant angle is tilted to by wafer or for semiconductor base, such as described first angle, using BL
(Beam Line) tool (ion implantation apparatus type) angle (vertical or special angle) of injection can be precisely controlled perform from
Son injection, now, semiconductor base is in first direction, such as the direction of rotation to 90 °, so as to form the first injection region, similarly,
The second injection region is formed according to similar operation, wherein, the second direction rotated extremely determines the position of the second injection region,
As the second injection direction select 270 °, so as to formed with symmetrical second injection region in the first injection region, in addition, the third time from
Son injection selection is to carry out ion implanting perpendicular to the in-plane where the upper surface of semiconductor base 11, to reach default
Injection depth, so as to form the 3rd injection region, its according to actual demand set.First injection region, second injection
Area and the 3rd injection region ultimately form the doping 14, and the region in mask cell 121 outside remaining injection region is just
As intrinsic region.
As an example, the first angle and the second angle are according to the institute between the adjacent mask cell 121
The depth-to-width ratio setting for the groove that the first gap is formed is stated, to control injection ion to reach the region that needs are injected, so as to
Form first injection region and second injection region.
Specifically, due to that may have influencing each other between different mask cells when carrying out ion implanting,
When needing to ensure to carry out ion implanting to a certain mask cell 121 as far as possible, adjacent mask cell 121 is not influenceed, now, is passed through
The depth-to-width ratio for the groove structure that gap between two adjacent mask cells 121 is formed with semiconductor base 11 come select to carry out from
The angle of son injection, for example, when the mask cell 121 to centre carries out first time ion implanting, the selection of its first angle
When, it is impossible to allow ion beam to have influence on the mask cell 121 in left side, then control mask cell of at least a branch of ion beam via left side
The lower-left angular vertex of reticule unit 121 is injected in 121 upper right side summit.
Furthermore it is also possible to form the doping 14 by the way of diffusion, as an example, in step 2), pass through expansion
Scattered mode specifically includes in carrying out ion doping：The structure that step 1) is obtained is placed in a reaction chamber, to the reaction
Impurity gas is passed through in chamber and is made annealing treatment, to form the doping at the top of the mask cell 121 and sidepiece
Portion, the region without diffusion forms the intrinsic portion in each mask cell 121.
Specifically, which is mixed by way of being directly diffused annealing in the mask cell 121 described in formation
Miscellaneous portion, and the technological parameter such as dosage, temperature and time of the impurity gas by controlling diffusion annealing, institute is formed so as to reach
Need the doping of area size being doped.
It is of course also possible to use other diffusion ways form the doping, such as in another example, pass through diffusion
Mode carries out ion doping, specifically includes：
2-1) one layer of photoresist layer, or the photoetching retained based on front and continued technique are formed in the patterned mask structure layer surface
Glue-line, ion implanting is carried out to the region corresponding to the surface of semiconductor base 11 in a manner of rectilinear ion implanting, with
The sidepiece that the gap is revealed in each mask cell 121 forms edge doped region；
2-2) to step 2-1) obtained by structure make annealing treatment, be diffused the edge doped region, with shape
Into the doping, and the region without diffusion forms the intrinsic portion in each mask cell, and removes remaining described
Photoresist layer.
Specifically, for this mode for diffuseing to form doping, using photoresist layer as mask, carry out vertical mode from
Son injection, the angle that injection can be precisely controlled using BL (Beam Line) tool (ion implantation apparatus type) are (vertical or specific
Angle) ion implanting is performed, it is of course also possible to use PLAD (Plasma Doping, plasma formula) modes perform, its
In, in the case of the effect of mask, ion implanting is not had in mask cell 121, High dose implantation makes ion accumulation exist
On the exposed surface of semiconductor base, such as Nitride surfaces, ion scattering mode is produced, the ion of scattering causes mask cell
There is mixing for dosage 121 both sides, form the edge doped region, further, it is necessary to carry out a step annealing handling process, make described
It is diffused in the peripherad mask cell 121 of edge doped region, the region after diffusion may eventually form the doping 14, and
Can be by making annealing treatment the control of condition, with the size of the doping 14 formed needed for further controlling.
As shown in the S3 in Fig. 1 and Fig. 5~6 and 13~14, step 3) is carried out, one intrinsic pattern auxiliary layer 15 of deposition is in institute
State on semiconductor base 11, and the intrinsic pattern auxiliary layer 15 at least fill between the mask cell 121 described first
Gap 122.
Specifically, in the step, then body structure surface after ion doping deposits to form one layer of intrinsic pattern auxiliary layer 15,
Wherein, the intrinsic pattern auxiliary layer 15 eventually forms integrated circuit patterns for auxiliary.As an example, the intrinsic pattern is auxiliary
Help the material of layer 15 to include photoresist or silica, but be not limited thereto.
As an example, in step 3), the step of forming intrinsic pattern auxiliary layer 15, includes：
3-1) surface of the structure obtained in step 2) deposits one layer of sacrificial material layer 16, and the sacrificial material layer 16 is located at
The top of each mask cell 121 and side wall simultaneously coat each mask cell 121；
Described in 3-2) at least being removed on each mask cell top surface by cmp or etching technics
Sacrificial material layer 16, to obtain being filled in the intrinsic pattern auxiliary layer 15 between each mask cell 121 in gap.
Specifically, in this example, the method for carrying out planarization process again by deposition materials layer obtains the intrinsic pattern
Auxiliary layer 15, wherein, when carrying out cmp or etching, it can only remove each top upper table of the mask cell 121
Sacrificial material layer on face, can also be by the expendable material described in each dome top surface of mask cell 121 more than plane
Layer all removes, it is, of course, also possible to further go the doping on the intrinsic dome top surface of portion 13 in the lump
Remove, this is set according to actual process demand, and this is not specifically limited.
In addition, when step 4) is chosen to remove the doping and retains the intrinsic pattern auxiliary layer and the intrinsic portion
In the case of, interstructural spacing is not necessarily adapted to perform etching as mask in being prepared due to pattern, then can be further
The intrinsic pattern auxiliary layer is modified, wherein, when the material selection of the intrinsic pattern auxiliary layer is photoresist, adopt
It is modified with well known Trim techniques in the industry, can when the material selection of the intrinsic pattern auxiliary layer is silica
To select the technique of wet etching to be modified, such as the mode for selecting hydrofluoric acid to be cleaned.
Need further exist for explanation is, if selection carries out modification to the intrinsic pattern auxiliary layer according to before in technique
Obtained patterned mask structure sheaf 12 pattern unit 121 between gap and select, below citing be explained：
As in one example, each mask cell 121 in step 1) is parallel and is equidistantly intervally arranged, in step 2)
First gap 122 of the width control system in the intrinsic portion 13 formed between the adjacent mask cell 121 is matched, it is excellent
Choosing is equal to first gap 122 between the adjacent mask cell 121.
In this case, by the injection size of the doping 14, and the doping 14 is finally being removed, so as to
So that the intrinsic pattern auxiliary layer of the reservation in the integrated circuit patterns eventually formed is identical and adjacent with the width in intrinsic portion
The distance between the intrinsic pattern auxiliary layer and described intrinsic portion determine its width because the width of doping is consistent
Uniformity, without modification, the integrated circuit patterns are directly obtained, next step process can be continued.
In another example, the doping 14 is removed in step 4) and retains the intrinsic portion 13 and the intrinsic pattern
Auxiliary layer 15, the intrinsic pattern auxiliary layer 15 of reservation include several intrinsic pattern auxiliary layer units, and methods described is also wrapped
Include step 5)：The intrinsic pattern auxiliary layer unit is modified, so that the width of the intrinsic pattern auxiliary layer unit is equal to described
The width in intrinsic portion, and cause the spacing phase between each adjacent intrinsic pattern auxiliary layer unit and the intrinsic portion 13
Deng.
Specifically, in this case, when the spacing between the adjacent mask cell 121 is not specifically limited, or
When spacing between the adjacent mask cell 121 is equal to the width of the mask cell 121, as shown in figure 13, finally going
After the doping 14, the intrinsic pattern auxiliary layer 15 defines wider remaining structure, i.e., described intrinsic pattern auxiliary
The wider width of layer unit, then it can now select to modify the intrinsic pattern auxiliary layer, the figure needed, with
The width of the intrinsic pattern auxiliary layer unit is equal to the width in the intrinsic portion, and cause each adjacent intrinsic pattern
Aid in layer unit equal with the spacing between the intrinsic portion 13, as shown in figure 14.
As shown in the S4 in Fig. 1 and Fig. 6~7, step 4) is carried out, the knot obtained using specific etching selection comparison step 3)
Structure performs etching, to form the second gap 123 on the semiconductor base 11, the forming method in second gap 123
Including being mask pattern selected from removing the doping 14 and retaining the intrinsic portion 13 and the intrinsic pattern auxiliary layer 15
Combination, and remove the intrinsic portion 13 and the intrinsic pattern auxiliary layer 15 and retain the doping 14 and repaiied for mask pattern
Positive the two one of them, so as to form the integrated circuit patterns, second gap 123 is located at the integrated circuit
In pattern and it is less than first gap 122.
Specifically, being performed etching using specific etching selection ratio in passing through the above-mentioned technique and this step of the present invention
Technique, the integrated circuit patterns structure in multiple patterns may finally be obtained, if after only removing the doping 14, by described
Levy pattern auxiliary layer 15 and the intrinsic portion 13 forms an integrated circuit patterns structure, this can be by ion doping Suo Shu
Doping 14 shows the characteristic realization for being easy to etching relative to the intrinsic pattern auxiliary layer and the intrinsic portion and removing, and such as schemes
Shown in 6；If removing the intrinsic portion 13 and the intrinsic pattern auxiliary layer 15 simultaneously, can obtain being made up of the doping 14
Integrated circuit patterns structure, this can be shown relative to the intrinsic pattern by the ion doping doping 14
Auxiliary layer and the intrinsic portion be difficult to the to be etched characteristic of removal realizes, as shown in Figure 7.
In addition, control second gap 123 is less than first gap 122, subtracted by simple pitch multiplication process
The small characteristic size of integrated circuit, the closeness of integrated circuit is further increased, reduce the volume of device architecture, can be with
Storage device is become smaller, further increase portability, computing capability and memory capacity of device etc..
As an example, characterized in that, in step 4), the etching liquid that specific etching selection ratio includes using is to described intrinsic
The etch rate of portion 13 and the intrinsic pattern auxiliary layer 15 is all higher than the etching liquid to the etch rate of doping 14
10 times；Or the etching liquid used is more than etching of the etching liquid to the intrinsic portion 13 to the etch rate of the doping 14
10 times of speed and more than 10 times of the etch rate to the intrinsic pattern auxiliary layer 15.
As an example, the doping 14 is removed in the step 4) and retains the intrinsic portion 13 and the intrinsic pattern is auxiliary
When helping layer 15, the material of patterned mask structure sheaf described in step 1) 12 includes polysilicon.
As an example, mixed when being removed in step 4) described in the intrinsic portion 13 and the intrinsic pattern auxiliary layer 15 and reservation
During miscellaneous portion 14, the material of patterned mask structure sheaf described in step 1) 12 includes silica.
Specifically, when the patterned mask structure sheaf material selection be polysilicon when, preferably remove the doping and
Retain the intrinsic portion and the intrinsic pattern auxiliary layer；When the material selection of the patterned mask structure sheaf is silica,
It is preferred that remove the intrinsic portion and the intrinsic pattern auxiliary layer and retain the doping.
In addition, as shown in figs. 8-10, as an example, in step 1), also it is included in the semiconductor base 11 and the figure
The step of one layer of mask layer 17 are formed between case mask structure layer 12, wherein, methods described also includes step 5)：By step
4) integrated circuit patterns obtained are transferred on the mask layer 17, and to obtain a mask layer 18, the mask layer 18 is made
Mask for the semiconductor base 11 continues to etch.
As an example, the material of the mask layer 17 includes silicon nitride, the material of the intrinsic pattern auxiliary layer 15
Include silica.
Specifically, as a kind of example, will present invention also offers the formation process of another integrated circuit patterns
The structure plan that the patterned mask structure sheaf 12 obtains with the intrinsic pattern auxiliary layer 15 through over etching is transferred to advance shape
Into mask layer 17 on obtain a mask layer 18.When the patterned mask structure sheaf 12 and the intrinsic pattern auxiliary layer 15
When structure after over etching is adapted to continue to perform etching the semiconductor base 11, it can be provided using this example
Technique, form one layer of new mask layer, wherein, the material of the mask layer 17 is such as worked as including but not limited to silicon nitride
When the material simultaneous selection of the intrinsic pattern auxiliary layer 15 is silica, mask layer 18 can be obtained, further, it is possible to using
Hydrofluoric acid etc. is modified silica, ensures the integrality of structure, obtains good mask layer 18.
The present invention also provides a kind of integrated circuit patterns based on pitch-multiplied formation, including：
Semiconductor substrate 11；
Patterned mask structure sheaf 12, it is formed on the semiconductor base 11, if the patterned mask structure sheaf 12 includes
A dry mask cell 121, and there is the first gap between the mask cell 121, the mask cell 121 with do not carry out from
The intrinsic portion 13 and be revealed in first gap and be covered in the top in the intrinsic portion 13 and the doping of side wall that son adulterates
Portion 14, wherein, the etch rate of the doping 14 is different from the etch rate in the intrinsic portion 13；And
Intrinsic pattern auxiliary layer 15, the intrinsic pattern auxiliary layer 15 fill the gap between the mask cell 121 and
Including several intrinsic pattern auxiliary layer units 151, wherein, the second gap 123 is formed on the semiconductor base 11, described
The generation in the second gap 123 includes retaining selected from the intrinsic portion 13 and the intrinsic pattern auxiliary layer unit 151, adjacent
Second gap, and the doping 14 are produced between the intrinsic portion 13 and the intrinsic pattern auxiliary layer unit 151
Retain, produce between the doping 14 of same mask cell 121 second gap it is above-mentioned both one of.
As an example, the material of the intrinsic pattern auxiliary layer 15, which includes, is selected from photoresist and silica wherein
It is a kind of.
As an example, when the material of the patterned mask structure sheaf 12 includes polysilicon, the intrinsic portion 13 and described
Intrinsic pattern auxiliary layer unit 151 retains.
As an example, when the material of the patterned mask structure sheaf 12 includes silica, the doping 14 retains.
Specifically, the semiconductor base 11 selects according to actual demand, can be that any needs are further etched
Structure, such as can be grid structure to be formed structure sheaf, it can be layer of material layer, or two layers and more than
The laminated material bed of material, be not particularly limited herein.In addition, the patterned mask knot formed on the surface of semiconductor base 11
Structure layer 12 will subsequently form required patterning by special pitch-multiplied (pitch doubling) technology, wherein, shape
Into integrated circuit patterns can apply in device preparation technology, in such as AA, CELL, BL and WL preparation technology, institute
Size, shape, quantity and arrangement of the mask cell 121 in patterned mask structure sheaf 12 etc. is stated according to actual demand
Selection, it is preferable that in the present embodiment, each evenly sized shape identical unit of mask cell 121, each mask list
Member 121 is parallel and is equidistantly intervally arranged.
In addition, when the semiconductor base 11 is the structure sheaf of grid structure to be formed, the adjacent mask cell 121
Between gap influence the corresponding area of grid to be etched formation, wherein, spacing between each mask cell 121 can be with
Equal to the width of each mask cell 121, the two can not also wait, be not particularly limited herein, can be according to the present invention
Integrated circuit patterns forming method obtain want etch semiconductor substrates 11 mask structure.Specifically, the pattern is covered
The material of membrane structure layer 12 can be polysilicon, or oxide (Oxide), such as silica.
As an example, the semiconductor base 11 includes substrate 111 and the piled grids knot on the substrate 111
Structure, wherein, the stacked gate architectures include：Grid oxic horizon 112 positioned at the surface of substrate 111；Positioned at the grid
The polysilicon layer 113 on the surface of oxide layer 112；And the metal level 114 positioned at the surface of polysilicon layer 113.
Specifically, the substrate 111 can be ripe for those of ordinary skill in the art such as silicon substrate, silicon-on-insulator substrates
Any substrate known, the grid oxic horizon 112 include but is not limited to silica；The metal level 114 includes but is not limited to
Metal tungsten layer；The diffusion impervious layer includes but is not limited to titanium nitride layer, as the diffusion between tungsten metal layer and polysilicon layer
Barrier layer；The grid protection layer 115 includes but is not limited to silicon nitride layer, for protecting grid structure, as being subsequently formed
When stating doping 14, diffusion ion accumulation scattering is unlikely to cause damage to grid structure.
In one example, remove the doping 14 and retain the intrinsic portion 13 and the intrinsic pattern auxiliary layer 15,
The intrinsic pattern auxiliary layer 15 retained includes several intrinsic pattern auxiliary layer units, the intrinsic pattern auxiliary layer unit
Width be equal to the width in the intrinsic portion, and cause each adjacent intrinsic pattern auxiliary layer unit and the intrinsic portion 13
Between spacing it is equal.
As an example, one layer of mask layer 17 between the semiconductor base 11 and the patterned mask structure sheaf 12,
Wherein, the integrated circuit patterns that patterned mask structure sheaf 12 of the invention and the intrinsic pattern auxiliary layer 15 obtain are transferred to institute
State on mask layer 17, to obtain a mask layer 18, the mask layer 18 continues as the mask of the semiconductor base 11
Perform etching.As an example, the material of the mask layer 17 includes silicon nitride, the material of the intrinsic pattern auxiliary layer 15
Include silica.
In summary, the present invention provides a kind of based on pitch-multiplied formation integrated circuit patterns and forming method, including such as
Lower step：Semiconductor substrate is provided, and in forming a patterned mask structure sheaf, the patterned mask on the semiconductor base
Structure sheaf includes several mask cells, and has the first gap between the mask cell；The mask cell is revealed in
The sidepiece in first gap carries out ion doping, the sidepiece of the mask cell is formed as doping, and the mask list
First separately to have the intrinsic portion for not carrying out ion doping coated by the doping, the doping has not with the intrinsic portion
Same etch rate；Deposit an intrinsic pattern auxiliary layer, and the intrinsic pattern auxiliary layer at least fill the mask cell it
Between first gap；And structure obtained in the previous step is compared using specific etching selection and performed etching, to be formed in institute
The second gap on semiconductor base is stated, the forming method in second gap is included selected from the removal doping and reservation
The intrinsic portion and the intrinsic pattern auxiliary layer combine for mask pattern, and remove the intrinsic portion and the intrinsic pattern
Auxiliary layer and retain described doping amendment the two one of them, so as to form integrated circuit patterns, between described second
Gap is located in the integrated circuit patterns and is less than first gap.By such scheme, multiple spacing provided by the invention
The forming method of exposing patterns, effectively solve the problems, such as that existing exposure imaging technology is limited and preparation technology complexity,
The semiconductor pattern structure of line footpath micro can be obtained, based on special pitch-multiplied (pitch doubling) technology, utilizes figure
Case mask structure layer and intrinsic pattern auxiliary layer, the size of integrated circuit feature size can be reduced, so as to required for being formed
Integrated circuit patterns structure, technique is simple, is not easy by ectocine, obtains the accurate size of pattern, easily controllable；The present invention's
Structures and methods can make integrated circuit more crypto set, and the size and memory cell of memory cell electric installation are formed by reducing
Conductor wire size, storage arrangement can be made to diminish, in addition, can be by being assembled more on the given area in storage arrangement
More memory cell increases memory capacity.So the present invention effectively overcomes various shortcoming of the prior art and has height
Spend industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (22)
- A kind of 1. method based on pitch-multiplied formation integrated circuit patterns, it is characterised in that comprise the following steps：1) semiconductor substrate is provided, and in forming a patterned mask structure sheaf, the patterned mask on the semiconductor base Structure sheaf includes several mask cells, and has the first gap between the mask cell；2) sidepiece that first gap is revealed in the mask cell carries out ion doping, makes the sidepiece of the mask cell Be formed as doping, and the mask cell separately has the intrinsic portion for not carrying out ion doping coated by the doping, institute State doping has different etch rates from the intrinsic portion；3) deposit an intrinsic pattern auxiliary layer on the semiconductor base, and the intrinsic pattern auxiliary layer at least fill it is described First gap between mask cell；And4) structure obtained using specific etching selection comparison step 3) is performed etching, to be formed on the semiconductor base Second gap, the forming method in second gap are included selected from removing the doping and retain the intrinsic portion and described Intrinsic pattern auxiliary layer combines for mask pattern, and removes described in the intrinsic portion and the intrinsic pattern auxiliary layer and reservation Doping be mask pattern amendment the two one of them, so as to form integrated circuit patterns, second gap is located at In the integrated circuit patterns and it is less than first gap.
- 2. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that in step 2) ion doping is carried out to the top of the mask cell simultaneously in.
- 3. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 2) In, ion doping is carried out in the side of the mask cell by way of ion implanting, is specifically included：First time ion implanting is carried out with first angle to the patterned mask structure sheaf, with the first of each mask cell Side forms the first injection region；AndSecond of ion implanting is carried out with second angle to the patterned mask structure sheaf, with the second of each mask cell Side forms second injection region relative with first injection region.
- 4. the method according to claim 3 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that described the The depth for the groove that one angle and the second angle are formed according to first gap between the adjacent mask cell Width reaches the region that needs are injected than setting with control injection ion, so as to form first injection region and described Second injection region.
- 5. the method according to claim 3 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that make described Semiconductor base is in first direction and tilts the progress first time ion implanting, rotates the semiconductor base to second direction Tilt and carry out second of ion implanting, and the first direction and the differential seat angle of the second direction are 180 °, described the One angle is equal with the second angle.
- 6. the method according to claim 3 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 2) In, ion doping is carried out in the top of the mask cell by way of ion implanting, is more specifically included：Third time ion implanting is carried out with third angle to the patterned mask structure sheaf, with the top of each mask cell The 3rd injection region is formed, wherein, mixed described in first injection region, second injection region and the 3rd injection region composition Miscellaneous portion, not ion implanted region forms the intrinsic portion in the mask cell.
- 7. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 2) In, ion doping is carried out by way of diffusion, is specifically included：2-1) one layer of photoresist layer, or the photoresist retained based on front and continued technique are formed in the patterned mask structure layer surface Layer, ion implanting is carried out to the region corresponding to the semiconductor substrate surface in a manner of rectilinear ion implanting, with each The sidepiece that the mask cell is revealed in the gap forms edge doped region；2-2) to step 2-1) obtained by structure make annealing treatment, be diffused the edge doped region, to be formed Doping is stated, and the region without diffusion forms the intrinsic portion in each mask cell, and remove the remaining photoetching Glue-line.
- 8. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 2) In, ion doping is carried out by way of diffusion, is specifically included：The structure that step 1) is obtained is placed in a reaction chamber, to Impurity gas is passed through in the reaction chamber and is made annealing treatment, the doping is formed with the sidepiece in the mask cell Portion, the region without diffusion forms the intrinsic portion in each mask cell.
- 9. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 3) In, formed the intrinsic pattern auxiliary layer the step of include：3-1) surface of the structure obtained in step 2) deposits one layer of sacrificial material layer, and the sacrificial material layer described is covered positioned at each The top of film unit and side wall simultaneously coat each mask cell；The sacrifice on each mask cell top surface at least 3-2) is removed by cmp or etching technics Material layer, to obtain being filled in the intrinsic pattern auxiliary layer between each mask cell in gap.
- 10. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that described The material of intrinsic pattern auxiliary layer includes photoresist or silica.
- 11. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 1) each mask cell in is parallel and is equidistantly intervally arranged, and the width control system in the intrinsic portion formed in step 2) exists Match first gap between the adjacent mask cell.
- 12. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 4) doping is removed in and retains the intrinsic portion and the intrinsic pattern auxiliary layer, the intrinsic pattern auxiliary of reservation Layer includes several intrinsic pattern auxiliary layer units, and methods described also includes step 5)：Modify the intrinsic pattern auxiliary layer list Member, so that the width of intrinsic pattern auxiliary layer unit is equal to the width in the intrinsic portion, and cause each adjacent described It is equal with the spacing between the intrinsic portion to levy pattern auxiliary layer unit.
- 13. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 1) also it is included in one layer of mask layer of formation between the semiconductor base and the patterned mask structure sheaf in, wherein, institute Stating method also includes step 5)：The integrated circuit patterns that step 4) is obtained are transferred on the mask layer, to obtain one Mask layer, the mask layer continue to etch as the mask of the semiconductor base.
- 14. the method according to claim 13 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that described The material of mask layer includes silicon nitride, and the material of the intrinsic pattern auxiliary layer includes silica.
- 15. the method according to claim 1 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that step 1) semiconductor base in includes substrate and the stacked gate architectures on the substrate, wherein, the stacking gate Pole structure includes：Positioned at the grid oxic horizon of the substrate surface；Positioned at the polysilicon layer of the gate oxidation layer surface；And Metal level positioned at the polysilicon layer surface.
- 16. the method based on pitch-multiplied formation integrated circuit patterns according to any one of claim 1~15, it is special Sign is, in step 4), the etching liquid that specific etching selection ratio includes using is aided in the intrinsic portion and the intrinsic pattern The etch rate of layer is all higher than the etching liquid to 10 times of the doping etch rate；Or the etching liquid used is mixed described The etch rate in miscellaneous portion is more than the etching liquid to 10 times of the etch rate in the intrinsic portion and more than the etching liquid to institute State the etch rate of intrinsic pattern auxiliary layer 10 times.
- 17. the method according to claim 16 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that work as step It is rapid 4) in remove the doping and when retaining the intrinsic portion and the intrinsic pattern auxiliary layer, pattern is covered described in step 1) The material of membrane structure layer includes polysilicon.
- 18. the method according to claim 16 based on pitch-multiplied formation integrated circuit patterns, it is characterised in that work as step When rapid 4) the middle removal intrinsic portion and the intrinsic pattern auxiliary layer and the reservation doping, pattern is covered described in step 1) The material of membrane structure layer includes silica.
- A kind of 19. integrated circuit patterns based on pitch-multiplied formation, it is characterised in that including：Semiconductor substrate；Patterned mask structure sheaf, it is formed on the semiconductor base, the patterned mask structure sheaf includes several mask lists Member, and there is the first gap between the mask cell, the mask cell have the intrinsic portion that does not carry out ion doping and It is revealed in first gap and is covered in the top in the intrinsic portion and the doping of side wall, wherein, the quarter of the doping It is different from the etch rate in the intrinsic portion to lose speed；AndIntrinsic pattern auxiliary layer, the intrinsic pattern auxiliary layer fill first gap between the mask cell and including Several intrinsic pattern auxiliary layer units, wherein, the second gap is formed on the semiconductor base, the production in second gap It is raw to include retaining selected from the intrinsic portion and the intrinsic pattern auxiliary layer unit, the adjacent intrinsic portion and described intrinsic Second gap is produced between pattern auxiliary layer unit, and the doping retains, the doping of same mask cell Produced between portion second gap the two one of them.
- 20. the integrated circuit patterns according to claim 19 based on pitch-multiplied formation, it is characterised in that described partly to lead Body substrate includes substrate and the stacked gate architectures on the substrate, wherein, the stacked gate architectures include：Positioned at institute State the grid oxic horizon of substrate surface；Positioned at the polysilicon layer of the gate oxidation layer surface；And positioned at the polysilicon layer The metal level on surface.
- 21. the integrated circuit patterns based on pitch-multiplied formation according to claim 19 or 20, it is characterised in that described The material of intrinsic pattern auxiliary layer includes and is selected from one of photoresist and silica；The patterned mask structure sheaf Material when including polysilicon, the intrinsic portion and the intrinsic pattern auxiliary layer unit retain.
- 22. the integrated circuit patterns based on pitch-multiplied formation according to claim 19 or 20, it is characterised in that described The material of intrinsic pattern auxiliary layer includes and is selected from one of photoresist and silica；The patterned mask structure sheaf Material when including silica, the doping retains.
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| CN110349906A (en) * | 2018-04-03 | 2019-10-18 | 长鑫存储技术有限公司 | A kind of forming method of autoregistration groove |
| CN110581066A (en) * | 2018-06-07 | 2019-12-17 | 长鑫存储技术有限公司 | Method for manufacturing multiple mask layer |
| CN111524794A (en) * | 2019-02-02 | 2020-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112542383A (en) * | 2019-09-20 | 2021-03-23 | 长鑫存储技术有限公司 | Semiconductor manufacturing method |
| CN113539794A (en) * | 2020-04-22 | 2021-10-22 | 芯恩（青岛）集成电路有限公司 | Semiconductor structure and preparation method thereof |
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