CN113539794A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN113539794A CN113539794A CN202010322713.5A CN202010322713A CN113539794A CN 113539794 A CN113539794 A CN 113539794A CN 202010322713 A CN202010322713 A CN 202010322713A CN 113539794 A CN113539794 A CN 113539794A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Abstract
The invention relates to a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming a first mask unit, a second mask unit and a third mask unit, carrying out ion implantation on the second mask unit based on the first mask unit and the third mask unit, forming at least one implantation area and at least one non-implantation area in the second mask unit, and forming a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation. The invention can adopt the combination of the processes of exposure-solidification-exposure-etching and the process of inclined ion implantation, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative developing method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the micro-shrinkage of the characteristic dimension of the pattern, does not need special technological process in the whole process, and has simple integral process, low cost and high productivity.
Description
Technical Field
The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
As the size of semiconductor devices continues to shrink, the feature size of photolithography technology gradually approaches and even exceeds the physical limit of optical lithography, which brings more serious manufacturing process challenges to semiconductor manufacturing technology, especially photolithography technology. The Double Pattern (Double Pattern) technology is widely applied to the 28 nm node technology, can greatly reduce the influence of the optical proximity effect, and alleviate the problem of single-mode shrinkage (single Pattern shrinkage), and realize smaller Pattern feature size (CD). The Double Patterning technique may include a LELE (light-Etch-light-Etch, exposure-etching-exposure-etching) Double Patterning method, an LFLE (light-Freeze-light-Etch, exposure-solidification-exposure-etching) Double Patterning method, and a Self-Aligned Double Patterning (SADP).
However, in the process of manufacturing the semiconductor device structure by using the conventional double patterning technology, the process steps and the manufacturing flow for realizing the structure with smaller nodes are often complex, the cost is high, and the manufacturing period is long. When the integrated circuit chip technology enters the node of 7nm and below, the size of the integrated circuit chip after photoetching by applying the technology is difficult to further reduce as expected, and the requirement of further shrinking the line width of the manufacturing process cannot be met. The technology based on the triple and quadruple patterns also greatly increases the cost and limits the application range of the technology.
Therefore, it is necessary to provide a dual-pattern based semiconductor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problems of complicated process steps and manufacturing procedures, low process efficiency, and the like in the prior art for manufacturing a device structure with a smaller technology node.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate;
forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units arranged at intervals and first gaps positioned between the adjacent first mask units, and the semiconductor substrate is exposed from the first gaps;
forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units arranged at intervals and second gaps located between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed from the first gaps, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units are lower than the upper surfaces of the first mask units, and the first mask units penetrate through the corresponding second gaps;
forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units arranged at intervals and third gaps located between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are located in the corresponding third gaps;
and performing ion implantation on the second mask unit based on the first mask unit and the third mask unit, forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit, and forming a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
Optionally, the first mask layer and the third mask layer are formed by a photolithography process, wherein the step of forming the first mask layer further includes a step of forming a barrier layer on a surface of the first mask unit.
Optionally, forming the second mask layer by a spin coating process; the material of the second mask layer comprises a silicon-doped anti-reflection layer or a silicon oxide layer.
Optionally, the upper surface of the third mask unit is not lower than the upper surface of the first mask unit.
Optionally, the semiconductor substrate includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, and the step of transferring the pattern on the new etching mask layer to the hard mask layer is further included after the new etching mask layer is formed.
Optionally, the material of the first mask layer is the same as the material of the third mask layer, and the material of the first mask layer and the material of the third mask layer include photoresist.
Optionally, the first mask units are uniformly spaced, the third mask units are uniformly spaced, the first mask units and the third mask units are alternately spaced, and the widths of the first mask units, the third mask units and the non-implanted regions are equal.
Optionally, the first gap and the third gap have the same width, and the first mask unit is located at the center of the third gap.
Optionally, positive-gradient ion implantation is adopted to form the implantation region, and the implantation region is removed after ion implantation, wherein the new etching mask layer is formed by the first mask unit, the non-implantation region and the second mask unit corresponding to the lower part of the third mask unit.
Optionally, negative inclined ion implantation is adopted to form the implantation region, and the non-implantation region is removed after the ion implantation is performed, wherein the non-implantation region is removed while the second mask units corresponding to the lower portions of the first mask unit and the third mask unit are removed, and the implantation region constitutes the new etching mask layer.
The present invention also provides a semiconductor structure, which is preferably prepared based on the semiconductor structure preparation method of the present invention, and of course, can also be prepared by other methods, wherein the semiconductor structure comprises:
a semiconductor substrate;
the first mask layer is positioned on the semiconductor substrate and comprises a plurality of first mask units which are arranged at intervals and first gaps positioned between the adjacent first mask units, and the semiconductor substrate is exposed from the first gaps;
the second mask layer is positioned on the semiconductor substrate and comprises a plurality of second mask units which are arranged at intervals and second gaps positioned between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed from the first gaps, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units are lower than the upper surfaces of the first mask units, and the first mask units penetrate through the corresponding second gaps;
the third mask layer is positioned on the second mask layer and comprises a plurality of third mask units which are arranged at intervals and third gaps positioned between the adjacent third mask units, wherein the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
the second mask unit further comprises at least one implanted region subjected to ion implantation and at least one non-implanted region, so that a new etching mask layer is formed on the basis of the second mask unit, the first mask unit and the third mask unit.
Optionally, the upper surface of the third mask unit is not lower than the upper surface of the first mask unit; and a barrier layer is also formed on the surface of the first mask unit.
Optionally, the material of the first mask layer is the same as the material of the third mask layer, and the material of the first mask layer and the material of the third mask layer include photoresist; the material of the second mask layer comprises a silicon-doped anti-reflection layer or a silicon oxide layer.
As described above, the semiconductor structure and the method for manufacturing the same of the present invention can adopt a combination of the exposure-solidification-exposure-etching process and the tilted ion implantation process, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative developing method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the micro-shrinkage of the characteristic dimension of the pattern, does not need special technological process in the whole process, and has simple integral process, low cost and high productivity.
Drawings
FIG. 1 is a process flow diagram illustrating the fabrication of a semiconductor structure according to the present invention.
FIG. 2 is a schematic diagram of a semiconductor substrate provided in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 3 is a schematic structural diagram illustrating the formation of a first masking material layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 4(a) is a schematic structural diagram illustrating the formation of a first mask layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 4(b) is a schematic structural diagram illustrating the formation of a barrier layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 5 is a schematic structural diagram illustrating the formation of a second mask layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 6 is a schematic structural diagram illustrating a third masking material layer formed during semiconductor structure fabrication according to an embodiment of the present invention.
FIG. 7 is a schematic structural diagram illustrating the formation of a third mask layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 8 is a schematic structural diagram illustrating an angled ion implantation process in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 9 is a schematic structural diagram illustrating the formation of a new etch mask layer during the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 10 is a schematic structural diagram illustrating another new etching mask layer formed during the semiconductor structure fabrication process according to an embodiment of the present invention.
FIG. 11 is a schematic diagram illustrating a patterned hard mask layer formed during fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 12(a) and 12(b) show the reaction formula of forming a silicon-containing polymer layer on the surface layer of the first mask unit using HMDS as a silylation agent in the preparation of the semiconductor structure according to the embodiment of the invention.
Fig. 13(a) shows the relationship between the etching time and the etching thickness after the ion implantation is not performed and the Ar + ion implantation of different concentrations is performed for the second mask unit.
Fig. 13(b) shows the change of the initial etching rate and the remaining percentage of the thin film for the second mask unit as the concentration of the implanted ions increases.
Fig. 14 shows an image of an etched structure formed after oblique ion implantation for Ar ions.
Description of the element reference numerals
100 semiconductor substrate
100a semiconductor substrate
100b hard mask layer
101 first layer of masking material
102 first mask layer
102a first mask unit
102b first gap
102c barrier layer
103 second mask layer
103a second mask unit
103b second gap
104 layer of a third masking material
105 third mask layer
105a third mask unit
105b third gap
106 implant region
107 non-implanted region
108 shaded region
109 new etch mask layer
110 patterned hard mask layer
S1-S5
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
s1: providing a semiconductor substrate;
s2: forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units arranged at intervals and first gaps positioned between the adjacent first mask units, and the semiconductor substrate is exposed from the first gaps;
s3: forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units arranged at intervals and second gaps located between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed from the first gaps, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units are lower than the upper surfaces of the first mask units, and the first mask units penetrate through the corresponding second gaps;
s4: forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units arranged at intervals and third gaps located between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are located in the corresponding third gaps;
s5: and performing ion implantation on the second mask unit based on the first mask unit and the third mask unit, forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit, and forming a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
The semiconductor structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings. The method for manufacturing a semiconductor structure provided by the present invention is not limited to the above-mentioned sequence of steps, and can be adjusted according to common knowledge in the art, and this embodiment provides only one example of the method for manufacturing a semiconductor structure of the present invention.
First, as shown in S1 of fig. 1 and fig. 2, step S1 is performed to provide the semiconductor substrate 100. The semiconductor base 100 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, or the like. In other embodiments, the semiconductor base 100 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The semiconductor substrate 100 may be a single-layer structure, or may be a stacked structure, such as a silicon/germanium-silicon stack. The semiconductor substrate 100 may be a substrate subjected to ion doping, and may be P-type doped or N-type doped. A plurality of semiconductor devices may also be formed in the semiconductor substrate 100.
As an example, the semiconductor base 100 includes a semiconductor substrate 100a and a hard mask layer 100b formed on the semiconductor substrate 100a, and a pattern on an etching mask layer may be transferred onto the hard mask layer 100b, and the semiconductor substrate 100a is etched based on the patterned hard mask layer 100 b. The material of the hard mask layer 100b includes, but is not limited to, carbon. In addition, the semiconductor substrate 100a may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, or the like, and may be a single-layer material layer or a structure formed by multiple material layers. In this example, the semiconductor substrate 100a is selected to be Si.
Next, as shown in S2 in fig. 1 and fig. 3, 4(a) and 4(b), step S2 is performed to form a first mask layer 102 on the semiconductor substrate 100, where the first mask layer 102 includes a plurality of first mask units 102a arranged at intervals and first gaps 102b located between adjacent first mask units 102a, and the first gaps 102b expose the semiconductor substrate 100. The first mask layer 102 may be formed by a photolithography process, in an example, the first mask material layer 101 may be formed on the semiconductor substrate 100, and then the first mask layer 102 is formed on the basis of exposure and development by the photolithography process, optionally, the material of the first mask material layer 101 includes but is not limited to photoresist, which may be positive photoresist or negative photoresist, and the first mask material layer 101 may be formed on the surface of the semiconductor substrate 100 by a common means such as spin coating or spray coating.
In an example, the first mask units 102a are uniformly spaced, and the height, the width, the number of the first mask units 102a and the width of the first gap 102b can be designed according to practical requirements.
In addition, as an example, after the first mask layer 102 is formed, a step of solidifying (freeze) the first mask unit 102a is further included, and after the solidification process is performed, a barrier layer 102c is formed on the surface of the first mask unit 102 a. The method for solidifying can be as follows: 1) and (3) chemical curing, namely coating a layer of chemical curing material on the surface of the photoresist, wherein the curing material consists of resin, a cross-linking agent and a solvent. After the wafer is baked and washed, a very thin cross-linked layer remains outside the lithography machine pattern, constituting the barrier layer. 2) And (2) high-temperature crosslinking curing, namely adding a temperature-activated crosslinking agent into the first layer of photoresist (namely the first mask material layer), wherein the activation temperature of the temperature-activated crosslinking agent is higher than the temperature of photoresist soft baking (PAB) and post-exposure baking (PEB), and after the first layer of photoresist is developed, baking the photoresist pattern at a higher temperature and carrying out crosslinking reaction. The crosslinked photoresist image is not affected by the second photolithography process. 3) Ultraviolet curing, i.e., the photoresist pattern formed by the first photolithography (i.e., the first mask unit), is performed by irradiating with ultraviolet light of 172nm, and then baking. Light at 172nm has only a limited penetration depth in 193nm photoresist and all the energy during exposure is absorbed by the surface of the photoresist. These energies will cause the organic polymers on the photoresist surface to cleave, generating free radicals. These free radicals react anew to form crosslinks that cure the photoresist pattern. Of course, other solidification (freeze) methods may be used, and are not limited thereto.
In another example, the material of the first mask material layer 101 is selected from a positive photoresist containing a resin and a photoacid generator, wherein the resin structure has an acid-labile or acid-cleavable organic group, and after exposure and baking, the acid-labile or acid-cleavable group in the resin is cleaved and changed from hydrophobic to hydrophilic, so that the solubility thereof in an organic solvent is reduced, and the unexposed portion still maintains the property of high solubility in the organic solvent. Using one characteristic of the positive photoresist, the embodiment uses a Negative Tone Development (NTD) technique to Develop the exposed and baked first mask material layer 101, and uses an organic solvent to remove the unexposed area of the first mask material layer. For example, ketones, ethers, esters, alcohols, hydrocarbons or amides are used. For example, in this embodiment, an alcohol solvent such as a mixed solution of one or more of 2-heptanone, 4-heptanone, 2-hexanone, 5-methyl-2-hexanone, 2-octanone, 2-nonanone, acetone, cyclohexanone, methylcyclohexanone, acetophenone, acetylacetone, methyl ethyl ketone, methyl isobutyl ketone, and the like is preferable. Of course, a normal developing method may be used, but not limited thereto.
And immersing the baked first mask material layer into the alcohol solvent to fully dissolve the unexposed area. The negative developing technique can be completed at room temperature without complicated process conditions, and can form fine patterns with high resolution. In addition, the technology adopts the organic solvent for development, the organic solvent has good solubility to organic matters on the surface of the substrate, and the surface of the substrate is high in cleanliness after development, less in organic residues and free from pollution to subsequent processes.
After the negative development, the unexposed region in the first mask material layer 101 is removed, and the exposed region is retained to form a pattern structure, so that the first mask layer 102 is obtained. After the pattern structure is formed, the pattern structure is subjected to silylation, that is, the first mask unit 102a is subjected to silylation. In the exposure process, the exposed region of the first mask material layer 101 generates a photoacid generating diffusion reaction when receiving light, wherein the photoacid generator generates an acid, and the baking process further allows the photoacid generating diffusion reaction to proceed, thereby forming a polymer containing hydroxyl (-OH) and/or carboxyl (-COOH) groups in the pattern structure. When the silylation process is performed later, a silicon-containing polymer layer is formed on the surface of the pattern structure. Commonly used silylating agents include Hexamethyldisilazane (HMDS), Trimethylchlorosilane (TMCS), Hexamethyldisilazane (HMDSZ), or other suitable silylating agents. In a preferred embodiment of this embodiment, HMDS is selected as the silylating agent, and a silylation reaction occurs on the surface layer of the patterned structure when the patterned structure is exposed to a gaseous HMDS atmosphere to form a silicon-containing polymer layer on the surface layer. Meanwhile, the reaction time and the reaction temperature of the silylation reaction are controlled to control the thickness of the silicon-containing polymer layer. In a preferred embodiment, in order to ensure that the silylation reaction is performed and that the photoresist layer inside the pattern structure is not damaged, the temperature of the silylation reaction is controlled to be less than 200 ℃, for example, the reaction temperature is controlled to be between 100 ℃ and 200 ℃, more preferably, to be between 120 ℃ and 150 ℃, and still more preferably, to be about 150 ℃. The reaction time is controlled to be 50 seconds to 200 seconds, thereby forming a silicon-containing polymer layer having a thickness of more than 5nm, preferably, between 5nm and 10nm on the surface layer of the pattern structure. The reaction formula for forming a silicon-containing polymer layer on the surface layer of the pattern structure using the above HMDS as a silylating agent is shown in fig. 12a and 12 b.
The formation thickness of the silicon-containing polymer is controlled by controlling the reaction temperature and time in the silylation treatment process, and meanwhile, the photoresist layer below the silicon-containing polymer layer can be prevented from being damaged by high temperature, so that the integrity of the first pattern structure is ensured, the line width of the first pattern structure is controlled, and the uniformity and the accuracy of the line width of the later etching are ensured.
After the silicon-containing polymer layer is formed, the silicon-containing polymer layer is subjected to a gas treatment, so that silicon in the silicon-containing polymer layer reacts with the gas to form a barrier layer 102c, as shown in fig. 4 (b). In this embodiment, the silicon-containing polymer layer is subjected to oxidation treatment, oxygen is introduced into the silicon-containing polymer layer, and the reaction temperature is controlled to cause oxidation reaction between silicon in the silicon-containing polymer and oxygen to generate a silicon dioxide layer. In the oxidation treatment process, in order to ensure that the oxidation reaction of the surface layer is carried out and the photoresist layer of the inner layer is not damaged, the temperature of the oxidation reaction is controlled to be less than or equal to 150 ℃, for example, the reaction temperature is controlled to be between 100 ℃ and 150 ℃, and more preferably, the reaction temperature is controlled to be 130 ℃. In addition, the time of oxidation can be controlled to control the thickness of the generated silicon dioxide barrier layer. In a preferred embodiment of this embodiment, the reaction time is controlled to be between 50 seconds and 200 seconds. In this embodiment, the thickness of the resultant silicon dioxide barrier layer is greater than 3nm, preferably between 3nm and 5 nm.
Through the above process, the barrier layer 102c is formed on the surface layer of the pattern structure (the first mask unit 102a), and the photoresist is wrapped, so that the first mask unit 102a is frozen and cannot be damaged in the subsequent process. In the freezing process, the thickness of the silicon-containing polymer layer and the silicon dioxide barrier layer generated on the surface layer of the first mask unit 102a can be well controlled by controlling the reaction time and the reaction temperature of the silylation treatment and the oxidation treatment, so that the line width of the first mask unit 102a can be controlled, the line width uniformity of the first mask unit 102a is realized, and the line width uniformity and the accuracy of the later etching are ensured.
Next, as shown in S3 of fig. 1 and fig. 5, step S3 is performed to form a second mask layer 103 on the semiconductor substrate 100, where the second mask layer 103 includes a plurality of second mask units 103a arranged at intervals and second gaps 103b located between adjacent second mask units 103a, where the second mask units 103a are correspondingly formed on the semiconductor substrate 100 exposed by the first gaps 102b, and the second gaps 103b expose the semiconductor substrate 100, where the exposure is not strictly an exposure, but may be that portions of the semiconductor substrate 100 not formed with the second mask units 103a are all referred to as exposing the semiconductor substrate 100, but the semiconductor substrate 100 may be formed with other material layers, and the first mask units 102a pass through the corresponding second gaps 103b, the upper surface of the second mask unit 103a is lower than the upper surface of the first mask unit 102 a. In this embodiment, the height of the second mask unit 103a is between 1/5-4/5 of the height of the first mask unit 102a, and 1/2 of the height of the second mask unit 103a may be selected to be smaller than the height of the first mask unit 102a, so as to facilitate the subsequent ion implantation and the preparation of a new mask.
In an example, an example of the second mask layer 103 is provided, that is, the second mask layer 103 is directly formed on the semiconductor substrate 100, the second mask layer 103 is formed on the semiconductor substrate 100 around the first mask unit 102a, that is, the second mask layer 103 is formed on the semiconductor substrate 100 exposed from the first gap 102b, as shown in fig. 5, a material layer in the first gap 102b forms a plurality of second mask units 103a, and the first mask unit 102a forms the second gap 103 b. Of course, in other embodiments, the positions, the numbers, and the widths of the second mask units 103a and the second gaps 103b may be designed according to actual requirements.
In one example, the material of the second mask layer 103 includes, but is not limited to, SiO2 or SiARC (silicon-containing anti-reflective coating), wherein a Si-containing BARC has a much faster etch rate than a photoresist during F ion etching, providing a higher etch selectivity. For example, the primary material of the SiARC is an organosiloxane, which is a highly branched siloxane and has pendant functional groups that absorb specific wavelengths. The material can be selected according to the requirements of subsequent ion implantation and formation of a new etching mask layer. The formation may be performed by spin coating.
Next, as shown in S4 of fig. 1 and fig. 6 to 7, step S4 is performed to form a third mask layer 105 on the second mask layer 103, where the third mask layer 105 includes a plurality of third mask units 105a arranged at intervals and third gaps 105b located between adjacent third mask units 105a, the third mask units 105a are correspondingly formed on the second mask units 103a, and the first mask units 102a are located in the corresponding third gaps 105 b.
The third mask layer 105 may be formed through a photolithography process, in an example, a third mask material layer 104 may be formed on the second mask layer 103, and then the third mask layer 105 is formed through the photolithography process based on exposure and development, optionally, a material of the third mask material layer 104 is the same as a material of the first mask material layer 101, for example, the material includes but is not limited to photoresist, in an example, the third mask material layer is coated on the first mask unit 102a and the second mask unit 103a, and optionally, a height of the third mask layer may be greater than or equal to a height of the first mask unit.
As an example, the height of the third mask unit 105a may be equal to or greater than the height of the first mask unit 102a, and the position of the ion implantation region may be subsequently adjusted by adjusting the tilt angle of the ion implantation, in a preferred example, the first mask unit 102a is flush with the upper surface of the third mask unit 105 a. So as to facilitate the subsequent inclined ion implantation to form the pattern with the middle space.
Finally, as shown in S5 of fig. 1 and fig. 8-11, step S5 is performed to implant ions into the second mask unit 103a based on the first mask unit 102a and the third mask unit 105a, and at least one implanted region 106 and at least one non-implanted region 107 are formed in the second mask unit 103a between the first mask unit 102a and the third mask unit 105a, so as to form a new etching mask layer based on the ion-implanted second mask unit 103a, the first mask unit 102a and the third mask unit 105 a.
In this step, a Tilt Ion Implantation (TII) is performed based on the formed third mask unit 105a and the shielding of the previously formed first mask unit 102a, and the second mask unit 103a is ion-implanted to form an implanted region 106 in the second mask unit 103a, and a non-implanted region 107 is formed in a non-implanted portion, so that the second mask unit 103a has a portion located below the third mask unit 105a, in addition to the implanted region 106 and the non-implanted region 107, and is defined as a shielded region 108. In this step, the angle of the tilted ion implantation, the implantation dose, the implantation energy, and the like are designed according to the actual structural requirements.
In an example, as shown in fig. 9, a negative-tone ion implantation (negative-tone) is used to form the implantation region 106, and the non-implantation region 107 is removed after the ion implantation is performed, wherein the non-implantation region 107 is removed while the second mask unit 103a corresponding to the lower portions of the first mask unit 102a and the third mask unit 105a, that is, the shielding region 108, is removed, and only the implantation region 106 formed by the implantation is remained, so that the implantation regions 106 constitute the new etching mask layer 109. In an example, the material of the first mask unit 102a and the third mask unit 105a is selected to be photoresist, the material of the second mask unit 103a is selected to be SiARC, and the ion for performing the tilted ion implantation is selected to be Ar +, but not limited thereto, the process for removing the non-implantation region 107, the first mask unit 102a and the shielding region 108 may be to first remove the first mask unit 102a, the barrier layer 102c and the third mask unit 105a, i.e., photoresist material, by using O2 plasma, and then select wet etching, and the etching solution is selected to be HF diluted by 200:1 (water: HF) and then further etch the non-implantation region 107.
In another example, as shown in fig. 10, a positive-slope ion implantation (positive-tone) is used to form the implantation region 106, and the implantation region 106 is removed after the ion implantation is performed, wherein the second mask unit 103a (i.e., the shielding region 108) corresponding to the first mask unit 102a, the non-implantation region 107, and the third mask unit 105a remains to form the new etching mask layer 109. In an example, the material of the first mask unit 102a and the third mask unit 105a is selected to be a photoresist, the material of the second mask unit 103a is selected to be SiO2, the ion for performing the tilted ion implantation is selected to be Ar +, but not limited thereto, the process for removing the implantation region 106 may be a wet etching process, and the etching solution is selected to etch away the implantation region 106 with HF diluted by 10:1 (water: HF).
In an example, the first mask units 102a are uniformly spaced, the third mask units 105a are uniformly spaced, and the first mask units 102a and the third mask units 105a are alternately spaced, and the first mask units 102a are located at the center of the third gaps 105b between adjacent third mask units 105a to form the first mask units 102a and the third mask units 105a which are uniformly spaced, in a further alternative example, the widths of the first mask units 102a, the third mask units 105a and the non-implantation regions 107 are equal. In addition, when the barrier layer is formed on the surface of the first mask unit 102a, the width and height are as large as the size of the barrier layer.
In addition, as shown in fig. 11, the semiconductor base 100 includes a semiconductor substrate 100a and a hard mask layer 100b formed on the semiconductor substrate 100a, in this example, the pattern on the new etching mask layer 109 formed as described above is transferred into the hard mask layer 100b to form a patterned hard mask layer 110, so as to perform downward etching based on the pattern. In the above-described manner of the present invention, the feature pitch (pitch) is reduced to 1/4 with respect to the first mask layer 102 formed on the semiconductor substrate 100. In addition, the present invention also provides a comparative example in which 3 pairs (6) of mask patterns are formed by a lelle (lithium-inch-lithium-inch) method, and 7 mask patterns may be formed by using the present invention, for example, the above-described LFLE (lithium-freeze-lithium-inch) combined with a tilted ion implantation process, and it can be seen that the present invention reduces 1 photolithography and 2 etchings with respect thereto. In addition, based on the scheme of the invention, the first mask layer can be obtained by carrying out first exposure and development through a photomask, and then when the third mask layer is obtained, the photomask is still used, and wafer stage (wafer platform) is moved quantitatively, so that graphs with fixed intervals and equal sizes can be obtained through two exposures.
In addition, as shown in fig. 13, an etching schematic diagram of the second mask unit 103a (selected as SiARC material) after Ar + ion implantation is provided, wherein wet etching is selected during the etching process, and the etching solution is selected as HF diluted by 200:1 (water: HF). Fig. 13(a) shows the relationship between the etching time and the etching thickness after the ion implantation was not performed and the Ar + ion implantation was performed at different concentrations. Therefore, after ion implantation with a certain concentration is carried out, the thickness of the material layer which can be etched away is gradually increased and gradually tends to be stable along with the increase of the ion implantation concentration within the same time; fig. 13(b) shows that as the doping concentration increases, the initial etch rate gradually decreases, as the SiARC ion implanted region begins to etch, and the remaining percentage of the film gradually increases and gradually stabilizes. Further, as shown in fig. 14, showing an image of an etched structure formed after oblique ion implantation (TII) for Ar ions, the upper graph shows that uniformity (uniformity) of the TII pattern even at 9nm is well controllable.
As shown in fig. 8, and referring to fig. 1-7 and fig. 9-12, the present invention further provides a semiconductor structure, comprising:
a semiconductor substrate 100;
the first mask layer 102 is located on the semiconductor substrate, the first mask layer includes a plurality of first mask units 102a arranged at intervals and first gaps 102b located between adjacent first mask units, and the first gaps 102b expose the semiconductor substrate 100;
the second mask layer 103 is located on the semiconductor substrate, and includes a plurality of second mask units 103a arranged at intervals and second gaps 103b located between adjacent second mask units, the second mask units 103a are correspondingly formed on the semiconductor substrate 100 exposed by the first gaps 102b, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units 103a are lower than the upper surfaces of the first mask units 102a, and the first mask units pass through the corresponding second gaps;
a third mask layer 105 located on the second mask layer, where the third mask layer includes a plurality of third mask units 105a arranged at intervals and third gaps 105b located between adjacent third mask units, where the third mask units 105a are correspondingly formed on the second mask units 103a, and the first mask units are located in the corresponding third gaps;
the second mask unit further comprises at least one implanted region 106 subjected to ion implantation and at least one non-implanted region 107, so as to form a new etch mask layer 109 based on the second mask unit, the first mask unit and the third mask unit.
As an example, the height of the third mask unit 105a may be equal to or greater than the height of the first mask unit 102a, and in a preferred example, the first mask unit 102a is flush with the upper surface of the third mask unit 105 a. So as to facilitate the subsequent inclined ion implantation to form the pattern with the middle space.
As an example, the material of the first mask layer 102 includes photoresist, the material of the second mask layer 103 includes a silicon-doped anti-reflection layer or a silicon oxide layer, and the material of the third mask layer 105 includes photoresist.
In summary, the semiconductor structure and the manufacturing method thereof of the present invention can adopt the combination of the exposure-solidification-exposure-etching process and the tilted ion implantation process, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative developing method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the micro-shrinkage of the characteristic dimension of the pattern, does not need special technological process in the whole process, and has simple integral process, low cost and high productivity. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A method for fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units arranged at intervals and first gaps positioned between the adjacent first mask units, and the semiconductor substrate is exposed from the first gaps;
forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units arranged at intervals and second gaps located between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed from the first gaps, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units are lower than the upper surfaces of the first mask units, and the first mask units penetrate through the corresponding second gaps;
forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units arranged at intervals and third gaps located between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are located in the corresponding third gaps;
and performing ion implantation on the second mask unit based on the first mask unit and the third mask unit, forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit, and forming a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
2. The method of claim 1, wherein the first mask layer and the third mask layer are formed by a photolithography process, and wherein the step of forming the first mask layer further comprises forming a barrier layer on a surface of the first mask unit.
3. The method of claim 1, wherein the second mask layer is formed by a spin-on process; the material of the second mask layer comprises a silicon-doped anti-reflection layer or a silicon oxide layer.
4. The method of claim 1, wherein an upper surface of the third mask unit is not lower than an upper surface of the first mask unit.
5. The method of claim 1, wherein the semiconductor base comprises a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, and the step of transferring the pattern on the new etch mask layer to the hard mask layer is further included after the new etch mask layer is formed.
6. The method of claim 1, wherein the first mask layer is made of the same material as the third mask layer, and the first mask layer and the third mask layer are made of photoresist.
7. The method according to claim 1, wherein the first mask units are uniformly spaced, the third mask units are uniformly spaced, and the first mask units and the third mask units are alternately spaced, and wherein the widths of the first mask units, the third mask units and the non-implanted regions are equal.
8. The method of claim 1, wherein the first gap and the third gap have the same width, and the first mask unit is located at the center of the third gap.
9. The method according to any one of claims 1 to 8, wherein the implantation region is formed by positive tilt ion implantation, and the implantation region is removed after the ion implantation, wherein the first mask unit, the non-implantation region and the second mask unit corresponding to the lower side of the third mask unit form the new etching mask layer.
10. The method according to any one of claims 1 to 8, wherein the implantation region is formed by negative tilt ion implantation, and the non-implantation region is removed after the ion implantation, wherein the second mask unit corresponding to the lower side of the first mask unit and the third mask unit is removed while the non-implantation region is removed, and the implantation region constitutes the new etching mask layer.
11. A semiconductor structure, comprising:
a semiconductor substrate;
the first mask layer is positioned on the semiconductor substrate and comprises a plurality of first mask units which are arranged at intervals and first gaps positioned between the adjacent first mask units, and the semiconductor substrate is exposed from the first gaps;
the second mask layer is positioned on the semiconductor substrate and comprises a plurality of second mask units which are arranged at intervals and second gaps positioned between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed from the first gaps, the second gaps expose the semiconductor substrate, the upper surfaces of the second mask units are lower than the upper surfaces of the first mask units, and the first mask units penetrate through the corresponding second gaps;
the third mask layer is positioned on the second mask layer and comprises a plurality of third mask units which are arranged at intervals and third gaps positioned between the adjacent third mask units, wherein the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
the second mask unit further comprises at least one implanted region subjected to ion implantation and at least one non-implanted region, so that a new etching mask layer is formed on the basis of the second mask unit, the first mask unit and the third mask unit.
12. The semiconductor structure of claim 11, wherein an upper surface of the third mask unit is not lower than an upper surface of the first mask unit; and a barrier layer is also formed on the surface of the first mask unit.
13. The semiconductor structure of any of claims 11-12, wherein the material of the first mask layer is the same as the material of the third mask layer, and the material of the first mask layer and the third mask layer comprises a photoresist; the material of the second mask layer comprises a silicon-doped anti-reflection layer or a silicon oxide layer.
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| CN101903977A (en) * | 2007-12-21 | 2010-12-01 | 朗姆研究公司 | Photoresist double patterning |
| CN102318046A (en) * | 2009-02-10 | 2012-01-11 | 国际商业机器公司 | Fin and finfet formation by angled ion implantation |
| US20130061183A1 (en) * | 2011-09-01 | 2013-03-07 | International Business Machines Corporation | Multiple Patterning Layout Decomposition for Ease of Conflict Removal |
| US20180130668A1 (en) * | 2015-05-01 | 2018-05-10 | The Regents Of The University Of California | Enhanced patterning of integrated circuit layer by tilted ion implantation |
| CN107863318A (en) * | 2017-11-22 | 2018-03-30 | 睿力集成电路有限公司 | Integrated circuit patterns and forming method based on pitch-multiplied formation |
| CN109860018A (en) * | 2017-11-30 | 2019-06-07 | 南亚科技股份有限公司 | The manufacturing method of semiconductor structure |
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