CN110349906B - Method for forming self-aligned trench - Google Patents
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- CN110349906B CN110349906B CN201810289842.1A CN201810289842A CN110349906B CN 110349906 B CN110349906 B CN 110349906B CN 201810289842 A CN201810289842 A CN 201810289842A CN 110349906 B CN110349906 B CN 110349906B
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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Abstract
The invention provides a method for forming a self-aligned trench, which comprises the following steps: forming an ion barrier layer, a mask layer and a patterned photoresist layer on a semiconductor substrate; forming mask structures on the ion blocking layer, wherein a first opening for exposing the ion blocking layer is formed between every two adjacent mask structures; performing ion implantation on the side wall of the mask structure, forming doped side walls on two sides of the mask structure, wherein an undoped mask bump is arranged between the doped side walls, and the etching selection ratio of the doped side walls to the ion barrier layer is greater than that of the mask bump to the ion barrier layer; performing first etching on the obtained structure based on the first opening to form a pre-groove in the semiconductor substrate; simultaneously removing the mask bump to form a second opening; etching the obtained structure based on the pre-groove and the second opening to form a first groove and a second groove in the semiconductor substrate; and removing the doped sidewall and the ion blocking layer to form a self-aligned trench. The invention solves the problems of complex steps and high cost of the existing method.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a method for forming a self-aligned trench.
Background
One way in which integrated circuit designers make faster and smaller integrated circuits is to reduce the separation distance between the various elements comprising the integrated circuit, a method of increasing the density of circuit elements on a substrate that is commonly referred to as "scaling" or increasing device integration; the structure design of the vertical transistor can effectively reduce the consumption of an active area and improve the integration level, and the transistor is generally isolated by a deep groove and a shallow groove is isolated from a source drain area.
The conventional methods for forming deep trenches and shallow trenches are generally shown in fig. 1 to 11, and the specific forming process includes: as shown in fig. 1, a semiconductor substrate 101 is provided, a buffer layer 102, an etch stop layer 103, an ion blocking layer 104, a mask layer 105 and a photoresist layer are sequentially formed on the semiconductor substrate 101, and the photoresist layer is subjected to photolithography to form a patterned photoresist layer 106; then, as shown in fig. 2 and fig. 3, the mask layer 105 and the ion blocking layer 104 are sequentially etched through a patterned photoresist layer 106; then, as shown in fig. 4 and 5, forming a first dielectric layer 107 on the surfaces of the remaining ion blocking layer 104 and the mask layer 105, and removing the first dielectric layer 107 on the upper surfaces of the remaining ion blocking layer 104 and the mask layer 105 to form a first opening; then, as shown in fig. 6 and 7, sequentially etching the etch stop layer 103, the buffer layer 102 and the semiconductor substrate 101 through the first opening to form a first trench 108 in the semiconductor substrate 101, and forming a first filling layer 109 in the first trench 108; then, as shown in fig. 8 and 9, removing the ion barrier layer 104 and the first dielectric layer 107 on the upper surface of the etch stop layer 103, and forming a second dielectric layer 110 on the surfaces of the etch stop layer 103 and the first filling layer 109 to form a second opening; then, as shown in fig. 10, the etching stop layer 103, the buffer layer 102 and the semiconductor substrate 101 are sequentially etched through the second opening, so as to form a second trench 111 in the semiconductor substrate 101; finally, as shown in fig. 11, a second filling layer 112 is formed in the second trench 111. Therefore, the forming method mainly comprises the steps of etching by using a mask twice to form a deep groove and a shallow groove respectively; therefore, when the grooves with different depths are prepared by adopting the forming method, the steps are complex and the production cost is higher.
Therefore, it is necessary to design a new method for forming self-aligned trenches to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for forming self-aligned trenches, which is used to solve the problems of complicated steps and high cost when the existing forming method is used to prepare trenches with different depths.
To achieve the above and other related objects, the present invention provides a method for forming a self-aligned trench, the method comprising:
s1: providing a semiconductor substrate, and sequentially forming an ion blocking layer, a mask layer and a patterned photoresist layer from bottom to top on the semiconductor substrate;
s2: etching the mask layer by using the patterned photoresist layer to form a plurality of mask structures positioned on the ion blocking layer, wherein a first opening is formed between every two adjacent mask structures, and the first opening exposes out of a first part of the ion blocking layer;
s3: performing ion implantation on the side wall of the mask structure to form doped side walls on two sides of the mask structure, wherein an undoped mask bump is arranged between the doped side walls, and the etching selection ratio of the doped side walls to the ion blocking layer is greater than that of the mask bump to the ion blocking layer;
s4: performing a first etching on the structure obtained in the step S3 based on the first opening, where the first etching removes at least the first portion of the ion blocking layer and the semiconductor substrate located under the first portion, so as to form a pre-trench in the semiconductor substrate; simultaneously removing the mask bump positioned between the adjacent doped side walls to form a second opening between the doped side walls; wherein the second opening exposes a second portion of the ion blocking layer;
s5: performing a second etching on the structure obtained in the step S4 based on the pre-trench and the second opening, wherein the second etching removes at least the second portion of the ion blocking layer and the semiconductor substrate located under the second portion to form a first trench in the semiconductor substrate, and a portion of the semiconductor substrate corresponding to the pre-trench is formed as a second trench having a depth different from that of the first trench; and
s6: and removing the doped side wall and a third part of the ion blocking layer except the first part and the second part to form the self-aligned trench.
Optionally, the second etching further includes removing at least the semiconductor substrate located at the bottom of the pre-trench to form the second trench in the semiconductor substrate; wherein the depth of the second trench is greater than the depth of the pre-trench and greater than the depth of the first trench.
Optionally, the first etching and the second etching are performed continuously.
Optionally, forming the second trench in the semiconductor substrate by the first etching, and removing a part of the mask bump located between the adjacent doped sidewalls; wherein a depth of the second trench is equal to a depth of the pre-trench.
Optionally, the first etching and the second etching are performed discontinuously, and the forming method further includes: s4-1 between the step S4 and the step S5: and forming a filling layer in the second groove, and removing a part of the mask bump positioned between the adjacent doped side walls to expose a second part of the ion blocking layer.
Optionally, the forming method further comprises: s4-1-1 between the step S4 and the step S4-1: and removing part of the doped side wall to enable the height of the remained doped side wall to be equal to the height of the remained mask bump.
Optionally, the depth of the second trench is greater than the depth of the first trench.
Optionally, the depth of the second trench is smaller than the depth of the first trench.
Optionally, in the step S3, an oblique angle ion implantation process is used to implant ions into the sidewalls of the mask structure.
Optionally, the tilt angle of the tilt angle ion implantation process is positively correlated with the thickness of the mask structure, and is negatively correlated with the width of the first opening.
Optionally, the tilt angle of the tilt angle ion implantation process ranges from 10 degrees to 80 degrees, and the tilt angle is an angular deviation with respect to a forward ion implantation direction perpendicular to the upper surface of the semiconductor substrate.
Optionally, the material of the mask layer comprises a carbon layer; the material of the doped side wall is different from that of the mask bump and contains boron.
Optionally, the ion implantation is performed with an implant gas selected from one of the group consisting of diborane and boron trifluoride.
Optionally, the atomic percentage of boron in the doped sidewall is between 5 atom% and 25 atom%.
Optionally, an etching selection ratio of the doped sidewall to the ion blocking layer is between 20 and 30, and an etching selection ratio of the mask bump to the ion blocking layer is between 10 and 15, so that the doped sidewall remains on the semiconductor substrate after the steps of S4 and S5, and a remaining height of the doped sidewall after the step of S4 is greater than or equal to one half of a forming height of the doped sidewall after the step of S3.
Optionally, the step of S1 further includes the step of sequentially forming a buffer layer and an etch stop layer from bottom to top between the semiconductor substrate and the ion blocking layer.
As described above, the method for forming a self-aligned trench according to the present invention has the following advantages:
according to the forming method, the etching selection ratio of the doped side wall to the ion blocking layer is larger than that of the mask lug to the ion blocking layer by performing ion implantation on the side wall of the mask structure, the preparation of the grooves with different depths can be realized by using the mask plate once, namely, the preparation of the second groove is realized by using the mask plate, the preparation of the first groove is realized by performing self-alignment on the doped side wall, the process steps are simplified, and the production cost is reduced.
The forming method of the invention can also increase the adjustability of the depth of the first groove by selecting the thickness of the mask layer, thereby enlarging the application range.
Drawings
Fig. 1 to 11 are schematic structural views illustrating steps in a conventional method for forming trenches with different depths.
Fig. 12 to 17 are schematic structural diagrams illustrating steps in a forming method according to an embodiment of the invention.
Fig. 18 to 27 are schematic structural diagrams illustrating steps in a forming method according to a second embodiment of the invention.
Fig. 28 is a schematic structural diagram of a self-aligned trench according to a third embodiment of the present invention.
Description of the element reference numerals
101 semiconductor substrate 102 buffer layer
103 etch stop layer 104 ion barrier layer
105 mask layer 106 patterned photoresist layer
107 first dielectric layer 108 first trench
109 first fill layer 110 second dielectric layer
111 second trench 112 second fill layer
201 semiconductor substrate 202 buffer layer
203 etch stop layer 204 ion barrier layer
205 mask layer 206 patterned photoresist layer
207 masking structure 208 first opening
209 mask bump 210 doped sidewall
211 pregroove 212 second opening
213 second trenches 214 first trenches
301 semiconductor substrate 302 buffer layer
303 etch stop layer 304 ion barrier layer
305 mask layer 306 patterned photoresist layer
307 mask structure 308 first opening
309 masking bump 310 doping sidewalls
311 pregroove 312 filler material layer
313 filling the second opening of the layer 314
315 first trench
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
Please refer to fig. 12 to fig. 28. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
Example one
As shown in fig. 12 to 17, the present embodiment provides a method for forming a self-aligned trench, the method including:
s1: providing a semiconductor substrate 201, and sequentially forming an ion blocking layer 204, a mask layer 205 and a patterned photoresist layer 206 from bottom to top on the semiconductor substrate 201;
s2: etching the mask layer 205 by using the patterned photoresist layer 206 to form a plurality of mask structures 207 on the ion blocking layer 204, wherein a first opening 208 is formed between adjacent mask structures 207, and a first part of the ion blocking layer 204 is exposed by the first opening 208;
s3: performing ion implantation on the sidewall of the mask structure 207 to form doped sidewalls 210 on both sides of the mask structure 207, wherein an undoped mask bump 209 is disposed between the doped sidewalls 210, and an etching selection ratio of the doped sidewalls 210 to the ion blocking layer 204 is greater than an etching selection ratio of the mask bump 209 to the ion blocking layer 204;
s4: performing a first etching on the structure obtained in step S3 based on the first opening 208, wherein the first etching removes at least the first portion of the ion blocking layer 204 and the semiconductor substrate 201 located under the first portion, so as to form a pre-trench 211 in the semiconductor substrate 201; simultaneously removing the mask bump 209 located between the adjacent doped sidewalls 210 to form a second opening 212 between the doped sidewalls 210; wherein the second opening 212 exposes a second portion of the ion blocking layer 201;
s5: performing a second etching on the structure obtained in the step S4 based on the pre-trench 211 and the second opening 212, wherein the second etching removes at least the second portion of the ion blocking layer 204 and the semiconductor substrate 201 under the second portion to form a first trench 214 in the semiconductor substrate 201, wherein a portion of the semiconductor substrate 201 corresponding to the pre-trench 211 is formed as a second trench 213, and a depth of the second trench 213 is different from a depth of the first trench 214; and
s6: removing the doped sidewall 210 and a third portion of the ion blocking layer 204 outside the first portion and the second portion to form the self-aligned trench.
The forming method of the present embodiment is described in detail with reference to fig. 12 to 17.
As shown in fig. 12, a semiconductor substrate 201 is provided, and an ion blocking layer 204, a mask layer 205 and a patterned photoresist layer 206 are sequentially formed on the semiconductor substrate 201 from bottom to top.
As an example, as shown in fig. 12, the step S1 further includes a step of sequentially forming a buffer layer 202 and an etch stop layer 203 from bottom to top between the semiconductor substrate 201 and the ion blocking layer 204.
Specifically, the material of the semiconductor substrate 201 includes a silicon (Si) layer; forming a buffer layer 202 on the semiconductor substrate 201 by a high temperature oxidation process, wherein the buffer layer 202 is made of a material includingSilicon dioxide (SiO)2) A layer, the buffer layer 202 having a thickness in a range from 3nm (nanometers) to 15 nm; forming an etching stop layer 203 on the buffer layer 202 by adopting a high-temperature furnace tube deposition or chemical vapor deposition process, wherein the material of the etching stop layer 203 comprises a silicon nitride (SiN) layer, and the thickness range of the etching stop layer 203 is 30 nm-150 nm; forming an ion barrier layer 204 on the etch stop layer 203 by using a chemical vapor deposition process, wherein the material of the ion barrier layer 204 includes silicon dioxide (SiO)2) A layer, the thickness of the ion blocking layer 204 ranges from 30nm to 100 nm; and forming a mask layer 205 on the ion blocking layer 204 by adopting a chemical vapor deposition process, wherein the material of the mask layer 205 comprises a carbon (C) layer, and the thickness of the mask layer 205 is in the range of 20nm to 200 nm.
As shown in fig. 12 and 13, the mask layer 205 is etched by using the patterned photoresist layer 206 to form a plurality of mask structures 207 on the ion blocking layer 204, a first opening 208 is formed between adjacent mask structures 207, and the first opening 208 exposes a first portion of the ion blocking layer 204.
As an example, a method of forming the mask structure 207 includes: a photoresist is spin-coated on the mask layer 205, and is patterned by a mask plate, and then the patterned photoresist 206 is used to etch the mask layer 205, so as to form the mask structure 207. It should be noted that the width D of the first opening 208 is the width of the second trench 213 to be formed later, so the width D of the first opening 208 can be determined according to actual requirements during the manufacturing process.
As shown in fig. 14, ion implantation is performed on the sidewall of the mask structure 207 to form doped sidewalls 210 on both sides of the mask structure 207, an undoped mask bump 209 is disposed between the doped sidewalls 210, wherein an etching selectivity of the doped sidewalls 210 to the ion blocking layer 204 is greater than an etching selectivity of the mask bump 209 to the ion blocking layer 204.
It should be noted that the width of the mask bump 209 is the width of the first trench 214 formed subsequently, so that in the manufacturing process, the width of the mask bump 209 may be determined according to actual requirements, so as to determine the width of the doped sidewall 210 according to the width of the mask bump 209, and further determine the energy and dose of the ion implantation.
As an example, the sidewall of the mask structure 207 is ion implanted using an angled ion implantation process.
Specifically, the tilt angle of the tilt angle ion implantation process is positively correlated with the thickness of the mask structure 207, and is negatively correlated with the width D of the first opening 208; that is, the thicker the mask structure 207 is, the larger the tilt angle is when the tilt angle ion implantation process is adopted; the wider the first opening 208, the smaller the tilt angle when using a tilt angle ion implantation process. Therefore, in the actual manufacturing process, the thickness of the mask structure 207 and the width D of the first opening 208 need to be considered together to determine the tilt angle. Preferably, in the present embodiment, the tilt angle θ of the tilt angle ion implantation process is in a range of 10 degrees to 80 degrees, and the tilt angle θ is an angular deviation with respect to a forward ion implantation direction perpendicular to the upper surface of the semiconductor substrate 201.
As an example, the ion implantation may be performed with an implant gas selected from one of the group consisting of diborane and boron trifluoride; the atomic percentage of boron in the doped sidewall 210 is between 5 atom% and 25 atom%, that is, the percentage of the number of boron atoms in the doped sidewall 210 to the total number of all atoms is between 5 atom% and 25%.
As an example, the material of the mask bump 209 includes carbon, and the material of the doped sidewall 210 is different from the material of the mask bump 209, and includes boron; the etching selection ratio of the doped side wall 210 to the ion blocking layer 204 is between 20 and 30, the etching selection ratio of the mask bump 209 to the ion blocking layer 204 is between 10 and 15, so that the doped side wall 210 remains on the semiconductor substrate 201 after the steps of S4 and S5, and the remaining height of the doped side wall 210 after the step of S4 is greater than or equal to one half of the forming height of the doped side wall 210 after the step of S3.
As shown in fig. 15, performing a first etching on the structure obtained in step S3 based on the first opening 208, where the first etching removes at least the first portion of the ion blocking layer 204 and the semiconductor substrate 201 located under the first portion, so as to form a pre-trench 211 in the semiconductor substrate 201; simultaneously removing the mask bump 209 located between the adjacent doped sidewalls 210 to form a second opening 212 between the doped sidewalls 210; the second opening 212 exposes a second portion of the ion blocking layer 204.
It should be noted that, in the present embodiment, under the same etching condition, the etching rate of the mask bump 209 is greater than the etching rate of the doped sidewall 210, so as to form the second opening 212 between the adjacent doped sidewalls 210, that is, the etching window of the first trench 214 is defined by the second opening 212, thereby achieving self-alignment.
As shown in fig. 16, a second etching is performed on the structure obtained in step S4 based on the pre-trench 211 and the second opening 212, the second etching removes at least the second portion of the ion blocking layer 204 and the semiconductor substrate 201 under the second portion to form a first trench 214 in the semiconductor substrate 201, wherein a portion of the semiconductor substrate 201 corresponding to the pre-trench 211 is formed as a second trench 213.
It should be noted that, in the subsequent manufacturing process of the semiconductor device, the first trench 214 and the second trench 213 may be filled with corresponding materials according to actual needs to achieve their corresponding functions. Filling a conductive material in the first trench 214 to form a trench gate; the second trench 213 is filled with an insulating material to form an isolation structure.
As an example, the second etching further includes removing at least the semiconductor substrate 201 located at the bottom of the pre-trench 211 to form the second trench 213 in the semiconductor substrate 201; wherein the depth of the second trench 213 is greater than the depth of the pre-trench 211 and greater than the depth of the first trench 214. Preferably, in this embodiment, the first etching and the second etching are performed continuously; for example, a dry etching process is used to form the first trench 214 and the second trench 213, wherein a depth H1 of the first trench 214 is in a range of 100nm to 200nm, and a depth H2 of the second trench 213 is in a range of 200nm to 300 nm.
As shown in fig. 17, the doped sidewall 210 and a third portion of the ion blocking layer 204 outside the first portion and the second portion are removed to form the self-aligned trench.
The self-aligned trench structure prepared by the above-described formation method is shown in fig. 17, and the self-aligned trench includes:
a semiconductor substrate 201; and
a first trench 214 and a second trench 213 formed in the semiconductor substrate 201, wherein the depth of the second trench 213 is greater than the depth of the first trench 214.
As an example, as shown in fig. 17, the self-aligned trench further includes: a buffer layer 202 and an etch stop layer 203 formed on the semiconductor substrate 201.
Specifically, the material of the semiconductor substrate 201 includes a silicon (Si) layer; the buffer layer 202 is made of silicon dioxide (SiO)2) A layer, the buffer layer 202 having a thickness in the range of 3nm to 15 nm; the material of the etching stop layer 203 comprises a silicon nitride (SiN) layer, and the thickness range of the etching stop layer 203 is 30 nm-150 nm.
Specifically, the first trenches 214 and the second trenches 213 are arranged at intervals, the depth H1 of the first trenches 214 ranges from 100nm to 200nm, and the depth H2 of the second trenches 213 ranges from 200nm to 300 nm.
Example two
As shown in fig. 18 to 27, the present embodiment provides a method for forming a self-aligned trench, including:
s1: providing a semiconductor substrate 301, and sequentially forming an ion blocking layer 304, a mask layer 305 and a patterned photoresist layer 306 from bottom to top on the semiconductor substrate 301;
s2: etching the mask layer 305 by using the patterned photoresist layer 306 to form a plurality of mask structures 307 on the ion blocking layer 304, wherein a first opening 308 is formed between adjacent mask structures 307, and a first portion of the ion blocking layer 304 is exposed by the first opening 308;
s3: performing ion implantation on the sidewall of the mask structure 307 to form doped sidewalls 310 on both sides of the mask structure 307, wherein an undoped mask bump 309 is disposed between the doped sidewalls 310, and an etching selectivity of the doped sidewalls 310 to the ion blocking layer 304 is greater than an etching selectivity of the mask bump 309 to the ion blocking layer 304;
s4: performing a first etching on the structure obtained in step S3 based on the first opening 308, wherein the first etching removes at least the first portion of the ion blocking layer 304 and the semiconductor substrate 301 located under the first portion, so as to form a pre-trench 311 in the semiconductor substrate 301; simultaneously removing the mask bump 309 between adjacent doped sidewalls 310 to form a second opening 314 between the doped sidewalls 310; wherein the second opening 314 exposes a second portion of the ion blocking layer 304;
s5: performing a second etching on the structure obtained in the step S4 based on the pre-trench 311 and the second opening 314, wherein the second etching removes at least the second portion of the ion blocking layer 304 and the semiconductor substrate 301 located under the second portion to form a first trench 315 in the semiconductor substrate 301, wherein a portion of the semiconductor substrate 301 corresponding to the pre-trench 311 is formed as a second trench, and a depth of the second trench is different from a depth of the first trench; and
s6: removing the doped sidewall 310 and a third portion of the ion blocking layer 304 outside the first portion and the second portion to form the self-aligned trench.
The forming method of the present embodiment is described in detail with reference to fig. 18 to 26.
As shown in fig. 18, a semiconductor substrate 301 is provided, and an ion blocking layer 304, a mask layer 305 and a patterned photoresist layer 306 are sequentially formed on the semiconductor substrate 301 from bottom to top.
As an example, as shown in fig. 18, the step S1 further includes a step of sequentially forming a buffer layer 302 and an etch stop layer 303 from bottom to top between the semiconductor substrate 301 and the ion blocking layer 304.
Specifically, the material of the semiconductor substrate 301 includes a silicon (Si) layer; forming a buffer layer 302 on the semiconductor substrate 301 by using a high temperature oxidation process, wherein the material of the buffer layer 302 includes silicon dioxide (SiO)2) A layer, the buffer layer 302 having a thickness in the range of 3nm to 15 nm; forming an etching stop layer 303 on the buffer layer 302 by adopting a high-temperature furnace tube deposition or chemical vapor deposition process, wherein the material of the etching stop layer 303 comprises a silicon nitride (SiN) layer, and the thickness range of the etching stop layer 303 is 30 nm-150 nm; forming an ion blocking layer 304 on the etch stop layer 303 by using a chemical vapor deposition process, wherein the material of the ion blocking layer 304 includes silicon dioxide (SiO)2) A layer, the thickness of the ion blocking layer 304 ranges from 30nm to 100 nm; a mask layer 305 is formed on the ion blocking layer 304 by using a chemical vapor deposition process, wherein the material of the mask layer 305 comprises a carbon (C) layer, and the thickness of the mask layer 305 is in a range from 20nm to 200 nm.
As shown in fig. 18 and 19, the mask layer 305 is etched by using the patterned photoresist layer 306 to form a plurality of mask structures 307 on the ion blocking layer 304, a first opening 308 is formed between adjacent mask structures 307, and the first opening 308 exposes a first portion of the ion blocking layer 304.
As an example, the method of forming the mask structure 307 includes: a photoresist is spin-coated on the mask layer 305, and is patterned by a mask plate, and then the patterned photoresist 306 is used to etch the mask layer 305, so as to form the mask structure 307. It should be noted that the width D of the first opening 308 is the width of the second trench to be formed later, so that the width D of the first opening 308 can be determined according to actual requirements during the manufacturing process.
As shown in fig. 20, ion implantation is performed on the sidewall of the mask structure 307 to form doped sidewalls 310 on both sides of the mask structure 307, wherein an undoped mask bump 309 is disposed between the doped sidewalls 310, and an etching selectivity of the doped sidewalls 310 to the ion blocking layer 304 is greater than an etching selectivity of the mask bump 309 to the ion blocking layer 304.
It should be noted that the width of the mask bump 309 is the width of the first trench 315 to be formed subsequently, so that the width of the mask bump 309 can be determined according to actual requirements during the manufacturing process, so as to determine the width of the doped sidewall 310 according to the width of the mask bump 309, and further determine the energy and dose of the ion implantation.
As an example, the sidewall of the mask structure 307 is ion implanted using an angled ion implantation process.
Specifically, the tilt angle of the tilt angle ion implantation process is positively correlated with the thickness of the mask structure 307, and is negatively correlated with the width D of the first opening 308; that is, the thicker the mask structure 307 is, the larger the tilt angle is when the tilt angle ion implantation process is adopted; the wider the first opening 308, the smaller the tilt angle when using a tilt angle ion implantation process. Therefore, in the actual manufacturing process, the thickness of the mask structure 307 and the width D of the first opening 308 need to be considered together to determine the tilt angle. Preferably, in the present embodiment, the tilt angle θ of the tilt angle ion implantation process is in a range of 10 degrees to 80 degrees, and the tilt angle θ is an angular deviation with respect to a forward ion implantation direction perpendicular to the upper surface of the semiconductor substrate 301.
As an example, the ion implantation may be performed with an implant gas selected from one of the group consisting of diborane and boron trifluoride; the atomic percentage of boron in the doped sidewall 310 is between 5 atom% and 25 atom%, that is, the percentage of the number of boron atoms in the doped sidewall 210 to the total number of all atoms is between 5 atom% and 25%.
As an example, the material of the mask bump 309 includes carbon, and the material of the doped sidewall 310 is different from the material of the mask bump 309 and includes boron; the etching selection ratio of the doped sidewall 310 to the ion blocking layer 304 is between 20 and 30, the etching selection ratio of the mask bump 309 to the ion blocking layer 304 is between 10 and 15, so that the doped sidewall 310 remains on the semiconductor substrate 301 after the steps of S4 and S5, and the remaining height of the doped sidewall 310 after the step of S4 is greater than or equal to one half of the formation height of the doped sidewall 310 after the step of S3.
As shown in fig. 21 to 25, performing a first etching on the structure obtained in step S3 based on the first opening 308, wherein the first etching removes at least the first portion of the ion blocking layer 304 and the semiconductor substrate 301 located under the first portion, so as to form a pre-trench 311 in the semiconductor substrate 301; simultaneously removing the mask bump 309 between adjacent doped sidewalls 310 to form a second opening 314 between the doped sidewalls 310; the second opening 314 exposes a second portion of the ion blocking layer 304.
It should be noted that, in the present embodiment, under the same etching condition, the etching rate of the mask bump 309 is greater than the etching rate of the doped sidewall 310, so as to form the second opening 314 between adjacent doped sidewalls 310, that is, the etching window of the first trench 315 is defined by the second opening 314, thereby achieving self-alignment.
As an example, as shown in fig. 21, the second trench is formed in the semiconductor substrate 301 by the first etching, and simultaneously, a portion of the mask bump 309 located between the adjacent doped sidewalls 310 is removed; wherein the depth of the second trench is equal to the depth of the pre-trench 311. That is, in this embodiment, the second trench is formed in the semiconductor substrate 301 directly by the first etching, while a portion of the mask bump 309 remains between the adjacent doped sidewalls 310.
As an example, as shown in fig. 22, the forming method further includes: s4-1-1 between the step S4 and the step S4-1: portions of the doped sidewalls 310 are removed such that the remaining doped sidewalls 310 have a height equal to the remaining height of the mask bumps 309.
Specifically, the doped sidewalls 310 are planarized by a chemical mechanical polishing process, such that the remaining doped sidewalls 310 have a height equal to the remaining height of the mask bump 309.
As an example, as shown in fig. 23 to 25, the forming method further includes: the first etching and the second etching are carried out discontinuously, and S4-1 between the step S4 and the step S5: a filling layer 313 is formed in the second trench, and a portion of the mask bump 309 between adjacent doped sidewalls 310 is removed to expose a second portion of the ion blocking layer 304.
Specifically, as shown in fig. 23 and 24, the method for forming the filling layer 313 includes: forming a filling material layer 312 in the second trench, on the doped sidewall 310 and on the mask bump 309 by using a chemical vapor deposition process, and performing surface planarization on the filling material layer 312 by using a chemical mechanical polishing process to expose the mask bump 309, thereby forming the filling layer 313. The material of the filling layer 313 comprises an insulating material; preferably, in this embodiment, the material of the insulating material includes silicon dioxide (SiO)2) A layer; i.e. filled with silicon dioxide (SiO)2) The second trench of the layer serves as an isolation structure for the semiconductor device. Of course, the material of the filling layer 313 may be selected from other materials according to actual needs to form other structures in the semiconductor device.
As shown in fig. 26, the structure obtained in step S4 is subjected to a second etching process based on the pre-trench 311 and the second opening 314, the second etching process removes at least the second portion of the ion blocking layer 304 and the semiconductor substrate 301 located under the second portion to form a first trench 315 in the semiconductor substrate 301, wherein a portion of the semiconductor substrate 301 corresponding to the pre-trench 311 is formed as a second trench.
As an example, the first trench 315 is formed by a dry etching process, wherein the depth of the second trench is greater than the depth of the first trench 315. Preferably, in the present embodiment, the depth H1 of the first trench 315 ranges from 100nm to 300nm, and the depth H2 of the second trench ranges from 200nm to 300 nm.
It should be noted that, in the subsequent manufacturing process of the semiconductor device, the first trench 315 may be filled with a corresponding material according to actual needs, so as to implement corresponding functions, such as a trench gate.
As shown in fig. 27, the doped sidewall 310 and a third portion of the ion blocking layer 304 other than the first portion and the second portion are removed to form the self-aligned trench.
As an example, as shown in fig. 27, the present embodiment further includes a step of removing the filling layer 313 above and at the sidewall of the ion blocking layer 304.
The self-aligned trench structure prepared by the above-described formation method is shown in fig. 27, and the self-aligned trench includes:
a semiconductor substrate 301; and
a first trench 315 and a second trench formed in the semiconductor substrate 301, wherein the depth of the second trench is greater than the depth of the first trench 315; and
and a filling layer 313 formed in the second trench.
As an example, as shown in fig. 27, the self-aligned trench further includes: a buffer layer 302 and an etch stop layer 303 formed on the semiconductor substrate 301.
Specifically, the material of the semiconductor substrate 301 includes a silicon (Si) layer; the buffer layer 302 is made of silicon dioxide (SiO)2) A layer, the buffer layer 302 having a thickness in the range of 3nm to 15 nm; the material of the etching stop layer 303 comprises a silicon nitride (SiN) layer, and the thickness range of the etching stop layer 303 is 30 nm-150 nm; the material of the filling layer 313 includes silicon dioxide (SiO)2) And the thickness of the filling layer 313 ranges from 200nm to 300 nm.
Specifically, the first trenches 315 and the second trenches are arranged at intervals, the depth H1 of the first trenches 315 ranges from 100nm to 300nm, and the depth H2 of the second trenches ranges from 200nm to 300 nm.
EXAMPLE III
As shown in fig. 28, the forming method of the present embodiment is different from the forming method of the second embodiment in that the depth of the first trench 315 is different, and in the present embodiment, the depth of the first trench 315 is greater than the depth of the second trench.
As an example, the first trenches and the second trenches are spaced apart from each other, the depth H1 of the first trenches ranges from 200nm to 400nm, and the depth H2 of the second trenches ranges from 200nm to 300 nm.
In the second and third embodiments, since the first trench and the second trench are formed separately at one time, when the first trench is formed, the adjustability of the depth of the first trench can be increased by adjusting the thickness of the mask layer, that is, the depth of the first trench can be adjusted according to actual needs; in combination with the second embodiment and the third embodiment, the depth of the first trench of the present invention can be adjusted within a range of 100nm to 400 nm.
In summary, the method for forming a self-aligned trench of the present invention has the following advantages:
according to the forming method, the etching selection ratio of the doped side wall to the ion blocking layer is larger than that of the mask lug to the ion blocking layer by performing ion implantation on the side wall of the mask structure, the preparation of the grooves with different depths can be realized by using the mask plate once, namely, the preparation of the second groove is realized by using the mask plate, the preparation of the first groove is realized by performing self-alignment on the doped side wall, the process steps are simplified, and the production cost is reduced.
The forming method of the invention can also increase the adjustability of the depth of the first groove by selecting the thickness of the mask layer, thereby enlarging the application range.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A method for forming a self-aligned trench, the method comprising:
s1: providing a semiconductor substrate, and sequentially forming an ion blocking layer, a mask layer and a patterned photoresist layer from bottom to top on the semiconductor substrate;
s2: etching the mask layer by using the patterned photoresist layer to form a plurality of mask structures positioned on the ion blocking layer, wherein a first opening is formed between every two adjacent mask structures, and the first opening exposes out of a first part of the ion blocking layer;
s3: performing ion implantation on the side wall of the mask structure to form doped side walls on two sides of the mask structure, wherein an undoped mask bump is arranged between the doped side walls, and the etching selection ratio of the doped side walls to the ion blocking layer is greater than that of the mask bump to the ion blocking layer;
s4: performing a first etching on the structure obtained in the step S3 based on the first opening, where the first etching removes at least the first portion of the ion blocking layer and the semiconductor substrate located under the first portion, so as to form a pre-trench in the semiconductor substrate; simultaneously removing the mask bump positioned between the adjacent doped side walls to form a second opening between the doped side walls; wherein the second opening exposes a second portion of the ion blocking layer;
s5: performing a second etching on the structure obtained in the step S4 based on the pre-trench and the second opening, wherein the second etching removes at least the second portion of the ion blocking layer and the semiconductor substrate located under the second portion to form a first trench in the semiconductor substrate, and a portion of the semiconductor substrate corresponding to the pre-trench is formed as a second trench having a depth different from that of the first trench; and
s6: removing the doped side wall and a third part of the ion blocking layer except the first part and the second part to form the self-aligned trench;
forming a second groove in the semiconductor substrate through the first etching, and removing a part of the mask bump between the adjacent doped side walls; wherein the depth of the second trench is equal to the depth of the pre-trench; the first etching and the second etching are performed discontinuously, and between the step S4 and the step S5, the forming method further includes: removing part of the doped side wall to enable the height of the remained doped side wall to be equal to the height of the remained mask bump; and forming a filling layer in the second groove, and removing a part of the mask bump positioned between the adjacent doped side walls to expose a second part of the ion blocking layer.
2. The method of claim 1, wherein a depth of the second trench is greater than a depth of the first trench.
3. The method of claim 1, wherein a depth of the second trench is less than a depth of the first trench.
4. The method as claimed in claim 1, wherein the step of S3 comprises performing an ion implantation process on the sidewalls of the mask structure by using an oblique angle ion implantation process.
5. The method of claim 4, wherein the tilt angle of the tilt angle ion implantation process is positively correlated to the thickness of the mask structure and negatively correlated to the width of the first opening.
6. The method of claim 4, wherein the tilt angle of the tilt angle ion implantation process is in a range of 10 degrees to 80 degrees, the tilt angle being an angular deviation from a forward ion implantation direction perpendicular to the upper surface of the semiconductor substrate.
7. The method of claim 1, wherein the mask layer comprises a carbon layer; the material of the doped side wall is different from that of the mask bump and contains boron.
8. The method of claim 7 wherein the ion implantation is performed with an implant gas selected from the group consisting of diborane and boron trifluoride.
9. The method of claim 7, wherein the atomic percent of boron in the doped sidewall is between 5 atom% and 25 atom%.
10. The method as claimed in claim 9, wherein an etching selectivity of the doped sidewall to the ion blocking layer is 20-30, an etching selectivity of the mask bump to the ion blocking layer is 10-15, so that the doped sidewall remains on the semiconductor substrate after the steps of S4 and S5, and a remaining height of the doped sidewall after the step of S4 is equal to or greater than one-half of a forming height of the doped sidewall after the step of S3.
11. The method as claimed in claim 1, wherein the step of S1 further comprises a step of sequentially forming a buffer layer and an etch stop layer from bottom to top between the semiconductor substrate and the ion blocking layer.
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| CN112750699B (en) * | 2019-10-29 | 2024-10-15 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN111211090B (en) * | 2019-12-11 | 2020-11-13 | 合肥晶合集成电路有限公司 | Groove manufacturing method and semiconductor isolation structure manufacturing method |
| CN113496944A (en) * | 2020-04-08 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113675141B (en) * | 2020-05-15 | 2024-01-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113809047B (en) * | 2020-06-12 | 2024-02-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN112259453A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Method for slotting surface of chip and chip |
| CN118366857A (en) * | 2023-01-11 | 2024-07-19 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN116364658B (en) * | 2023-05-31 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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| CN113488430A (en) | 2021-10-08 |
| CN113488430B (en) | 2023-04-25 |
| CN110349906A (en) | 2019-10-18 |
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