JP3943200B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a plurality of thin film transistors (TFTs), and relates to a semiconductor integrated circuit having a high breakdown voltage TFT and a high-speed driving TFT on the same substrate and a manufacturing method thereof.
[0002]
[Prior art]
Recently, research has been conducted on an insulating gate type semiconductor device having a thin film semiconductor layer (also referred to as an active layer) on an insulating substrate. In particular, thin-film insulated gate transistors, so-called thin film transistors (TFTs), have been actively studied. Depending on the material and crystal state of the semiconductor to be used, it is distinguished as amorphous silicon (hereinafter referred to as a-Si TFT) TFT or polysilicon TFT (hereinafter referred to as p-Si TFT).
[0003]
In general, the electric field mobility of an amorphous semiconductor is small, and therefore an a-Si TFT cannot be used for a TFT that requires high-speed operation. On the other hand, a crystalline semiconductor such as polysilicon has a high electric field mobility, and a TFT capable of high speed operation can be manufactured.
[0004]
In general, p-Si TFTs are distinguished by low temperature p-Si TFTs and high temperature p-Si TFTs depending on the process temperature of silicon crystallization. In recent years, the performance of p-Si TFTs has been improved. In particular, the threshold voltage is 3 V or less for low-temperature p-Si TFTs and 1.5 V or less for high-temperature p-Si TFTs. Also, the power supply voltage has been lowered, and it has become possible to operate at a clock frequency of several MHz to several tens of MHz even with a relatively low power supply voltage of 10 V or less for a low temperature p-Si TFT and 5 V or less for a high temperature p-Si TFT.
[0005]
For an active matrix display panel such as a liquid crystal display device, a peripheral circuit integrated type in which not only a pixel circuit but also a peripheral circuit (driver circuit) for driving the pixel circuit is formed on the same substrate by p-Si TFT. Commercialization of panels is progressing.
[0006]
From the viewpoint of simplifying the configuration of the electronic system and reducing power consumption, it is desirable that the power supply voltage level of the liquid crystal display system is the same as that of the external IC for controlling the driver circuit. Usually, the operating voltage of the IC is 5V or 3.3V. In general, the power supply voltage of the driver circuit of the active matrix panel is about 5V. However, for the following reasons, it is very difficult to reduce the power supply voltage of the pixel circuit to several volts at present.
[0007]
In recent years, the demand for gradation display has increased, and 256 gradations (8 bits) are necessary for full-color display. For example, if the voltage level of the liquid crystal per gradation is 10 to 20 mV, the level of the driving voltage of the liquid crystal is about 2.5 to 5 V in order to realize 256 gradations.
[0008]
The threshold voltage of the liquid crystal is about 1.5 to 2V in the TN mode and about 2 to 5V in the ECB mode.
[0009]
Accordingly, the power supply voltage of the pixel circuit is at least about 14 to 25 V when the threshold voltage of the pixel TFT, the threshold voltage of the liquid crystal, the voltage required for gradation display, and the driving voltage of the liquid crystal (amplitude of the alternating voltage) are added. It is appropriate to set to. Therefore, since a relatively high voltage is applied to the pixel TFT and the gate driver TFT, there is a problem that the pixel TFT and the gate driver TFT are easily deteriorated.
[0010]
On the other hand, a signal processing circuit such as a driver circuit is a circuit that is operated at a low voltage of about 3 to 5 V, and high speed operation characteristics are required for the driver TFT. As described above, in the peripheral integrated panel, TFTs having contradictory characteristics such as a high voltage operation-high withstand voltage TFT and a low voltage operation-high speed operation TFT are manufactured on the same substrate.
[0011]
[Problems to be solved by the invention]
In the peripheral integrated panel described above, the pixel TFT driven at a high voltage is likely to deteriorate. An n-channel TFT is mainly used as the pixel TFT. The main cause of the deterioration of the n-channel TFT is that hot carriers are injected into the gate insulating film at the drain junction. In particular, when the gate insulating film is formed of an insulating film formed by CVD or the like, the degree of deterioration becomes larger because the trap level is larger than that of the thermal oxide film.
[0012]
In order to prevent deterioration due to carrier injection, the applied voltage is lowered or the gate insulating film is thickened to weaken the electric field strength at the drain junction. However, as described in the conventional example, it is difficult to reduce the voltage applied to the pixel portion. On the other hand, the technique of increasing the thickness of the gate insulating film reduces the deterioration of the pixel TFT, but reduces the operation speed of the driver circuit. In order to maintain the operation speed of the driver circuit, the drive voltage may be increased, but the power consumption increases.
[0013]
Thus, a method for satisfying the characteristics of the respective TFTs by recalling the gate insulating films of the high breakdown voltage TFT and the high-speed operation TFT and making the film thicknesses different is conceived. However, the following problems arise.
[0014]
First, an optimum film thickness can be obtained by separately forming the gate insulating film forming process of the high voltage TFT and the high speed TFT. However, it becomes necessary to produce a resist mask that covers the other gate insulating film, which causes a problem of contamination and complicates the process.
[0015]
Second, a method of reducing the thickness of the gate insulating film of the high-speed operation TFT by an etching method is conceivable. However, there is a problem in the controllability and reproducibility of the film thickness. In particular, in the top gate type TFT, the gate insulating film is etched in the presence of the active layer, so that a new defect level is generated and the reliability is impaired. Further, in the case of a top gate type TFT, if the gate insulating film is made thick, it becomes difficult to perform impurity doping by through doping.
[0016]
High speed operation and high breakdown voltage are contradictory characteristics. As described above, it is very difficult to manufacture a high-speed operation type TFT and a high breakdown voltage type TFT on the same substrate without impairing reliability by a conventional TFT manufacturing method. The present invention is intended to provide an answer to such a difficult problem.
[0017]
An object of the present invention is to form a top gate type TFT and a bottom gate type TFT on the same substrate and to make the high-speed operation TFT on the same substrate by making the film thicknesses of the gate insulating films of the two types of TFTs different from each other. An object of the present invention is to provide a semiconductor integrated circuit having a high voltage TFT.
[0018]
It is another object of the present invention to provide a method for manufacturing a semiconductor integrated circuit capable of easily and reliably manufacturing a semiconductor integrated circuit in which such high-speed operation TFTs and high breakdown voltage TFTs are integrated.
[0019]
[Means for Solving the Problems]
In order to solve the above-described problems, a semiconductor integrated circuit according to the present invention has a top gate type thin film transistor and a bottom gate type thin film transistor on the same substrate.
A first insulating film covering the substrate;
A gate electrode of the bottom gate type thin film transistor formed between the substrate and the first insulating film;
A semiconductor layer of the top gate type thin film transistor formed on the first insulating film; a semiconductor layer of the bottom gate type thin film transistor;
A second insulating film covering at least a channel formation region of the semiconductor layer of the top gate thin film transistor;
A gate electrode of the top gate type thin film transistor formed on the second insulating film;
Have
The first insulating film is used as a gate insulating film of the bottom gate type thin film transistor, and the second insulating film is used as a gate insulating film of the top gate type thin film transistor.
[0020]
In order to solve the above-described problem, the structure of the method for manufacturing a semiconductor integrated circuit according to the present invention is a method for manufacturing a semiconductor integrated circuit having a bottom gate thin film transistor and a top gate thin film transistor on the same substrate. ,
Forming a gate electrode of the bottom gate type thin film transistor on the substrate;
A second step of forming a first insulating film covering the substrate and the gate electrode of the bottom gate type thin film transistor;
A semiconductor layer of the top gate thin film transistor on the first insulating film;
A third step of forming a bottom gate type thin film transistor semiconductor layer;
A fourth step of forming a second insulating film covering at least the channel formation region of the semiconductor layer of the top gate thin film transistor;
A fifth step of forming a gate electrode of the top gate type thin film transistor on the second insulating film;
Have
The first insulating film is used as a gate insulating film of the bottom gate type thin film transistor, and the second insulating film is used as a gate insulating film of the top gate type thin film transistor.
[0021]
In the present invention, the gate insulating film of the bottom gate type TFT and the base insulating film for preventing impurity diffusion from the substrate of the top gate type TFT are made common to the first insulating film, and the gate of the bottom gate type TFT is provided. The insulating film (first insulating film) and the gate insulating film (second insulating film) of the top gate type TFT are present in different layers, and are characterized by being manufactured by different processes.
[0022]
With the configuration of the present invention described above, the thickness of the top gate type gate insulating film and the bottom gate type gate insulating film can be made different without adding or changing a process for changing the thickness of the gate insulating film such as etching or film formation. Can be easily done. Based on the manufacturing process of the top gate type TFT, the integrated circuit manufacturing method of the present invention only adds a process of manufacturing the gate electrode of the bottom gate type TFT before forming the base insulating film. Therefore, according to the present invention, TFTs having contradictory characteristics of a high breakdown voltage type TFT and a high speed operation type TFT can be easily manufactured on the same substrate without impairing reliability.
[0023]
For example, the bottom gate type TFT is a high breakdown voltage type with a thick gate insulating film. On the other hand, the top gate type TFT is made a high speed operation type by thinning the gate insulating film. On the contrary, the first insulating film can be made thinner than the second insulating film so that the bottom gate type TFT can be a high breakdown voltage type and the top gate type TFT can be a high speed operation type.
[0024]
Actually, the thicknesses of the first and second insulating films are appropriately set according to the driving voltage of the TFT. For example, when the semiconductor integrated circuit of the present invention is applied to an active matrix type liquid crystal display device, if it is a low drive voltage and high speed operation type TFT of about 3 to 5 V such as a signal processing circuit such as a driver circuit, The thickness of the gate insulating film (first or second insulating film) may be 100 nm or less. The lower limit is defined by a film thickness that does not open pinholes, and is about 10 nm for a deposited film such as a CVD film, and can be 10 nm or less using a thermally oxidized film with good density.
[0025]
In the case of a TFT driven by a relatively high power supply voltage of about 14 to 25 V, such as a pixel TFT, the thickness of the gate insulating film (first or second insulating film) is increased to about 150 nm to 300 nm. To do. If the driving voltage is higher, the first or second insulating film is made thicker.
[0026]
For example, when the top gate type TFT is a low driving voltage / high speed operation type and the bottom gate type thin film transistor is a high driving voltage / high withstand voltage type, the second insulating film is thinned to 100 nm or less, and the first insulating film Is as thick as 150-300 nm. Further, when the characteristics of the top gate type and the bottom gate type are reversed, the relationship between the thicknesses of the first and second insulating films may be reversed.
[0027]
In conventional semiconductor integrated circuits (particularly digital circuits), the voltages used are all the same in the circuit. For example, in a DRAM, a memory area and a peripheral circuit are driven with a single voltage. Therefore, the features of the present invention can be understood by paying attention to the fact that the conventional semiconductor integrated circuit technology does not require the thickness of the gate insulating film to be positively changed as in the present invention.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a cross-sectional view of an active matrix panel. On the same substrate 100, a bottom gate type TFT 200,
Top gate TFTs 300 and 350 are provided. The substrate 100 is provided with a first insulating film 110 that covers the surface. A gate electrode 201 of the bottom gate type TFT 200 is formed between the substrate 100 and the first insulating film 110. On the first insulating film 100, the semiconductor layer 202 of the bottom gate type TFT 200 and the semiconductor layers 302 and 303 of the top gate type TFTs 300 and 350 are formed.
[0029]
The first insulating film 110 functions as a gate insulating film of the bottom gate type TFT 200, and impurities such as Na ions diffuse from the substrate 100 (particularly, a glass substrate) into the semiconductor layers 302 and 303 of the top gate type TFTs 300 and 350. It also functions as a base film for preventing this.
[0030]
The first insulating film 110 includes a single layer film formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a multilayer film thereof formed by a deposition method such as a CVD method. The multilayer structure has an effect that the redundancy is increased as compared with the case where a thick film of 150 to 300 nm is formed by a single layer film. For example, even if the pin pole is generated by a single film, the pin pole can be covered by being laminated in multiple layers.
[0031]
In addition, from the viewpoint of TFT mobility characteristics, the semiconductor layers 202, 302, and 303 are preferably formed of polycrystalline silicon. As a method for forming polycrystalline silicon, an amorphous silicon thin film may be crystallized by heat treatment or laser irradiation.
[0032]
In the case of using the above crystallization process, the material of the substrate 100 may be selected depending on the process temperature. For example, a glass substrate is used when a low temperature process of about 600 ° C. is used, and a quartz substrate is used when a high temperature process of about 900 ° C. is used.
[0033]
Further, the material of the gate electrode 201 of the bottom gate type 200 formed before the crystallization process is selected so as to withstand the crystallization process temperature. Examples of the material of the gate electrode 201 include semiconductor materials such as polycrystalline silicon or microcrystalline silicon to which phosphorus is added, refractory metals such as tantalum, chromium, tungsten, molybdenum, and titanium, alloys or silicides of these refractory metals. Can be used.
[0034]
Next, the second insulating film 120 is formed over the semiconductor layers 202, 302, and 303. The second insulating film 120 functions as a gate insulating film of the top gate type TFTs 300 and 350. As the second insulating film, a deposited film by CVD such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a single layer film or a multilayer film made of a thermal oxide film obtained by thermally oxidizing the semiconductor layers 302 and 303 is used. For example, a laminated film of a thermal oxide film and a silicon oxide deposited film by CVD can be used.
[0035]
As one embodiment, the bottom gate type TFT 200 is a high breakdown voltage type by thickening the gate insulating film, and the first insulating film 110 is used when the gate gate insulating film of the top gate type TFTs 300 and 350 is thinned to be a high speed operation type. The film thickness may be about 150 to 300 nm, and is set appropriately depending on the required high breakdown voltage characteristics. On the other hand, the second insulating film 120 is preferably as thin as possible from the viewpoint of high-speed operation characteristics.
[0036]
As a method of making the gate insulating film of the bottom gate type TFT 200 thicker, the gate electrode 201 is formed of an anodic refractory metal such as tantalum, titanium, molybdenum, chromium, etc., and the gate electrode is anodized to surround it. The method of producing a metal oxide is mentioned.
[0037]
Next, the gate electrodes 304 and 305 of the top gate type TFTs 300 and 350 are formed on the second insulating film 120. The materials of the gate electrodes 304 and 305 are semiconductor materials such as polycrystalline silicon or microcrystalline silicon to which phosphorus is added, refractory metals such as tantalum, chromium, tungsten, molybdenum, and titanium, alloys or silicides of these refractory metals. Can be used. In order to operate the top gate type TFTs 300 and 350 at higher speed, the top gate type TFTs 300 and 350 are made of a material mainly composed of low resistance aluminum. Further, it can be submicron to be a high-speed operation type. In this case, it is preferable to salicide the semiconductor layer and gate electrode of the top gate type TFT.
[0038]
Next, a third insulating film 130 that covers the second insulating film 120 and the gate electrodes 304 and 305 of the top gate type TFTs 300 and 350 is formed. Then, contact holes reaching the semiconductor layers 202, 302, and 303 are opened in the second and third insulating films 120 and 130, and wirings 209 and 210 connected to the active layers 202, 302, and 303 are formed. Since the semiconductor layers 202, 302, and 303 are respectively covered with the same second and third insulating films 120 and 130, the contact hole opening process of the bottom TFT 200 and the top gate TFTs 300 and 350 is made the same. Can do.
[0039]
Here, the top gate type has been described as a high-speed operation type, and the bottom gate type has been described as a high breakdown voltage type, but it is apparent that the reverse is possible.
[0040]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.
[0041]
Embodiment 1 In this embodiment, an example in which the present invention is applied to an active matrix display device in which a pixel portion and a driver circuit are formed on the same substrate will be described. FIG. 1 is a schematic cross-sectional view of the matrix panel of this embodiment, and FIG. 2 is a block diagram of the active matrix panel of this embodiment.
[0042]
As shown in FIG. 2, the substrate 10 includes a pixel unit 11 that performs display, a peripheral circuit including a source driver 12 and a gate driver 13, and an extraction terminal unit 14 for inputting signals and power from the outside. Is provided. A plurality of pixel electrodes are arranged in a matrix in the pixel portion 11, and TFTs are connected to the pixel electrodes, respectively. The source driver 12 and the gate driver 13 are composed of TFTs. The output of the source driver 12 is connected to the source line of the pixel TFT, and a video signal is input to the pixel TFT. The output of the gate driver 13 is connected to the gate line of the pixel TFT and controls on / off of the pixel TFT.
[0043]
In this embodiment, as shown in FIG. 1, the pixel TFT 200 in which high breakdown voltage is given priority is a bottom gate type. On the other hand, the n-channel driver TFT 300 and the p-channel driver TFT 350 constituting the source driver 12 and the gate driver 13 in which high-speed operation is given priority are set to the top gate type. An inverter circuit can be configured by connecting the TFTs 300 and 350 in a complementary manner.
[0044]
By making the TFT structure different, the gate insulating film of the pixel TFT 200 (bottom gate type TFT) is made thick without impairing the reliability of the TFT, and the thickness of the gate insulating film of the driver TFT 300, 350 (top gate type TFT). It is possible to reduce the thickness. Hereinafter, a manufacturing process of the active matrix panel shown in FIG. 1 will be described with reference to FIGS.
[0045]
First, as shown in FIG. 4A, the gate electrode 201 of the pixel TFT 200 is formed on the glass substrate 100. Here, a gate electrode 201 is formed by forming a tantalum film with a thickness of 200 nm by sputtering and patterning.
[0046]
Next, a bottom gate insulating film 110 made of a silicon oxide film and having a thickness of 150 to 300 nm is formed on the entire substrate 100 by sputtering or plasma CVD. In this embodiment, the thickness of the gate insulating film 110 is 200 nm. The bottom gate insulating film 110 functions as a gate insulating film of the pixel TFT 200 and also functions as a base film that prevents diffusion of impurities from the substrate 100. Further, the gate insulating film 110 is not a single layer film but can be a multilayer film in which insulating films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are stacked. By using a multi-layer structure rather than a single-layer film having a thickness of 150 to 300 nm, there is an effect that redundancy is improved.
[0047]
Next, a polycrystalline silicon film 21 for forming a TFT semiconductor layer is formed.
An intrinsic (I type) amorphous silicon film having a thickness of 40 to 150 nm, for example 55 nm, is deposited by plasma CVD or low pressure CVD, and crystallized by a known crystallization method to form a polycrystalline silicon film 21. (FIG. 4A).
[0048]
The polycrystalline silicon film 21 is patterned by photolithography to be separated into islands, thereby forming the semiconductor layer 202 of the pixel TFT 200 and the semiconductor layers 302 and 303 of the driver TFTs 300 and 350, respectively (FIG. 4B).
[0049]
Next, a gate insulating film 120 for top gate covering the semiconductor layers 202, 302, and 303 is formed to a thickness of 10 to 100 nm. In this embodiment, a silicon oxynitride film having a thickness of 100 nm is formed by plasma CVD. In addition to the silicon oxynitride film, a silicon oxide film or a silicon nitride film can also be formed. Further, a multilayer film of these insulating films may be formed. In the pixel TFT 200, the gate insulating film 120 constitutes the lowermost layer of the interlayer insulating film (FIG. 4C).
[0050]
Next, the conductive film 22 constituting the gate electrodes of the driver TFTs 300 and 350 is formed. In this embodiment, an aluminum film to which a small amount of Sc is added is formed by sputtering to a thickness of 300 nm (FIG. 4D).
[0051]
Next, the conductive film 22 is patterned to form the gate electrodes 304 and 305 of the driver TFTs 300 and 350. Since aluminum is an anodizable material, a known anodizing treatment may be performed after patterning to form an anodized film around the gate electrode. By forming the anodic oxide film, the heat resistance of the gate electrodes 304 and 305 can be improved (FIG. 5A).
[0052]
Next, the semiconductor layers 202 and 302 are doped with n-type impurities by a known doping method. First, a photoresist mask 23 having openings in the semiconductor layers 202 and 302 and covering the channel formation region and the semiconductor layer 303 with the semiconductor layer 202 of the pixel TFT 200 is formed. Ion doping is used for doping, and phosphine is used as a doping gas.
[0053]
In this doping process, in the pixel TFT 200, the region 203 shielded by the photoresist mask 23 becomes a channel formation region. The regions 204 and 205 function as n-type source and drain regions. In the driver TFT 300, the region 306 shielded by the gate electrode 304 substantially maintains the intrinsic conductivity type and becomes a channel formation region. The regions 308 and 309 which are not shielded become n-type source regions and drain regions (FIG. 5B).
[0054]
Next, the resist mask 23 is peeled off, a resist mask 24 having an opening in the semiconductor layer 303 is newly formed, and a p-type impurity, for example, boron is doped into the semiconductor layer 303 by ion doping. As a result, p-type impurity regions 312 and 313 are formed. These regions 312 and 313 become a source region and a drain region of the driver TFT 350. After the doping process, the resist mask 24 is peeled off, and the doped impurities are activated by laser annealing or thermal annealing (FIG. 5C).
[0055]
Note that the mask 23 used in the doping step shown in FIG. 5B mainly functions to shield the channel formation region of the bottom gate type TFT 200. In order to form such a mask in a self-aligning manner, the method shown in FIG. 7 can be used. First, after the process shown in FIG. 5A, a resist 30 is applied to the entire surface.
Then, laser light is irradiated from the back surface of the substrate 100 to expose the resist 30 (FIG. 7A).
[0056]
Then, since the gate electrodes 202, 303, and 304 function as a mask, a portion that is not irradiated with laser light remains after development, and a mask 31 that covers the channel formation region of the bottom gate type TFT 200 is formed in a self-aligned manner. Using this mask 31, phosphorus is doped to form n-type impurity regions 204, 205, 310, and 311. In this case, phosphorus is also added to the semiconductor layer 303, so that n-type impurity regions 310 and 311 are formed (FIG. 7B).
[0057]
Therefore, in the boron doping step shown in FIG. 5C, the dose must be set so that the conductivity type of the n-type impurity regions 310 and 311 is inverted to the p-type.
[0058]
In addition, although the ion doping method is used in the doping step of FIG. 5B, the mask 23 becomes unnecessary by using the laser doping method. In the case of an ion doping method, laser light is irradiated from the back surface of the substrate 100 in an atmosphere containing activated phosphorus.
[0059]
Then, in the semiconductor layer of the TFT 200, the region where the laser beam is blocked by the gate electrode 201 is not doped with dopant, so that n-type impurity regions 204 and 205 are formed in a self-aligned manner, and the conductivity of the region 203 is increased. Is true.
[0060]
On the other hand, in the semiconductor layers of the TFTs 300 and 350, the region where the dopant contacts is limited by the gate electrodes 304 and 305, so that n-type impurity regions 308 to 311 are formed in a self-aligned manner as shown in FIG. . Therefore, in the boron doping step shown in FIG. 5C, the dose must be set so that the conductivity type of the n-type impurity regions 310 and 11 is inverted to the p-type.
[0061]
After activating the impurity doped in the semiconductor layer, a silicon oxide film having a thickness of 600 nm is formed as a first interlayer insulating film 130 by a plasma CVD method (FIG. 6A).
[0062]
Next, the first interlayer insulating film 130 and the gate insulating film 120 are etched, and contact holes 206, 207, 314 to 318 reaching the source / drain regions 204, 205, and 308 to 311 of the TFTs 200, 300, and 350, respectively. Then, contact holes 320 and 321 reaching the gate electrodes 304 and 305 of the driver TFTs 300 and 350 are formed (FIG. 6B).
[0063]
Next, a 100 nm titanium film, a 300 nm aluminum film, and a 100 nm titanium film are continuously formed by sputtering and patterned to form electrodes 208, 209, and 322 to 326. Thus, the TFTs 200, 300, and 350 are completed (FIG. 6C).
[0064]
Next, a pixel electrode connected to the pixel TFT 200 is manufactured. First, as shown in FIG. 1, a second interlayer insulating film 140 covering these electrodes 208, 209, and 322 to 326 is formed of an acrylic film having a thickness of 1 μm. A resin film of acrylic or the like is suitable as a base on which a pixel electrode is formed because a flat surface can be obtained by canceling the unevenness of the base. As the interlayer insulating film 140, an organic resin material such as acrylic, polyamide, or polyimide amide can be used in addition to polyimide. Among organic resin materials, acrylic is the cheapest. In addition, an inorganic insulating material of silicon nitride, silicon oxide, or silicon nitride oxide film can be used for the interlayer insulating film 140. Alternatively, a laminate of an inorganic material and an organic resin material can be used.
[0065]
Next, a titanium film having a thickness of 150 to 250 nm, for example, 200 nm is formed on the second interlayer insulating film 140 by sputtering and patterned to form a light shielding film 210 that covers the semiconductor layer of the pixel TFT 200. Next, a third interlayer insulating film 150 made of acrylic having a thickness of 0.5 μm is formed on the entire substrate so as to cover the light shielding film 210.
[0066]
Next, the second and third interlayer insulating films 140 and 150 are etched, a contact hole reaching the electrode 209 is opened, and a pixel electrode 211 connected to the electrode 209 is formed. In the case of a transmissive display panel, the pixel electrode 211 is formed of an indium tin oxide film (ITO) or a transparent conductive material such as tin oxide. In the case of a reflection type, the pixel electrode 211 is formed of a metal film such as aluminum. The pixel TFT 200 is connected to a storage capacitor 212 having a light shielding film 210, a pixel electrode 211 as a counter electrode, and a third interlayer insulating film 150 as a dielectric.
[0067]
Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. Through the above steps, an active matrix substrate having a bottom gate type pixel TFT 200 and top gate type driver TFTs 300 and 350 is completed (FIG. 1).
[0068]
By adopting the manufacturing method of this embodiment, TFTs having gate insulating films with different thicknesses can be manufactured over the same substrate without adding an etching process or an extra film forming process. According to this embodiment, the top gate type gate insulating film 120 is made as thin as 100 nm and the bottom gate gate insulating film 110 is made as thick as 200 nm, so that the top gate type TFTs 300 and 350 having high-speed operation characteristics and the high withstand voltage characteristics can be obtained. The bottom gate type TFT 200 having the same can be manufactured over the same substrate. Note that the thickness of the gate insulating film of the TFT 200, TFT 300, 350 may be appropriately set by the practitioner depending on the driving voltage or the like.
[0069]
Further, in the top gate type TFTs 300 and 350 of this embodiment, the channel forming regions are formed in a self-aligned manner by the gate electrodes 304 and 305. Therefore, by narrowing the width of the gate electrodes 304 and 305, the channel length can be shortened in a self-aligned manner, and the high-speed operation characteristics of the top gate type TFTs 300 and 350 can be further improved.
[0070]
The gate electrode of the top gate type TFT is formed after the crystallization process of polycrystalline silicon. Therefore, since the gate electrode can be made of a low melting point but low resistance material such as aluminum, the top gate type TFT is more suitable for the high speed operation type TFT than the bottom gate type. Further, since the top gate type uses a gate electrode as a doping mask, a channel formation region is formed in a self-aligned manner. Therefore, by reducing the width of the gate electrode, the channel length can be easily shortened, and higher speed operation characteristics can be improved.
[0071]
Conversely, by increasing the channel length, the breakdown voltage characteristics can be improved. Even in a TFT having a gate insulating film with the same film thickness, by changing the gate line width, a TFT giving priority to higher speed operation and a TFT giving priority to a high breakdown voltage can be separately formed. In the top gate type TFTs 300 and 350, the channel formation region is formed by the gate electrode in a self-aligned manner. Therefore, for example, the gate electrode width of a circuit giving priority to high-speed operation such as a shift register circuit is set to about 1 μm, The gate electrode width of a circuit that prioritizes high breakdown voltage is set to about 2 μm, and the characteristics can be made different between the same top gate type TFTs 300 and 350. The same applies to the bottom gate type TFT 200.
[0072]
Example 2 This example is a modification of the active matrix panel shown in Example 1. FIG. A cross-sectional view of the active matrix panel of this example is shown in FIG.
[0073]
In this embodiment, the light shielding film 330 for the driver TFTs 300 and 350 is formed by the same process as the gate electrode 201 of the pixel TFT 200. The configuration other than the light shielding film 330 and the manufacturing process are the same as those in the first embodiment, and in FIG.
[0074]
When the material of the substrate 100 is light-transmitting like glass or quartz, light enters the semiconductor layers 302 and 303 of the TFTs 300 and 350 from the back surface of the substrate 100, which causes the TFTs 300 and 350 to deteriorate. In this embodiment, an object is to shield the semiconductor layers 302 and 303 from light incident from the back surface of the substrate 100 by providing the light shielding film 330.
[0075]
In order to form the light shielding film 330, first, the gate electrode 201 and the starting film of the light shielding film 330 are formed on the substrate 100. The starting film may be made of a metal that has conductivity and reflects light. From the viewpoint of heat resistance of the gate electrode 201, a high melting point metal material such as titanium, molybdenum, chromium, tantalum, or tungsten, or these The alloy is used.
[0076]
After the metal film is formed on the substrate 100, the gate electrode 201 and the light shielding film 330 are formed by patterning. For example, the light shielding film 330 is formed in the entire position where the source driver 12 and the gate driver 13 shown in FIG. 1 are formed. Alternatively, they are formed only at positions where the semiconductor layers 302 and 303 of the top gate TFTs 300 and 350 are formed.
[0077]
In the present embodiment, the light shielding film can be formed only by changing the mask pattern for patterning the gate electrode 201 of the first embodiment. Therefore, the photogate deterioration of the top gate TFTs 300 and 350 can be prevented without complicating the process.
[0078]
[Embodiment 3] In Embodiment 1, an example in which the TFTs constituting the source driver 12 and the gate driver 13 are all high-speed operation type top gate TFTs 300 and 350 is shown. However, the gate driver 13 is not relatively higher in operating frequency than the source driver 12. Therefore, the gate driver 13 may be manufactured using the high breakdown voltage TFT 200 of the first embodiment, and the source driver 12 may be manufactured using the high-speed operation type top gate TFTs 300 and 350.
[0079]
As shown in FIG. 3, the gate driver 13 has a configuration in which a shift register circuit 16, a level shifter circuit 17, and an output buffer circuit 18 are sequentially connected, and the output of the output buffer circuit 18 is arranged in the pixel unit 13. It is connected to the gate electrode of the pixel TFT.
[0080]
Generally, the drive voltage of the shift register circuit 16 is about 5V, the level shifter circuit 17 is about 5-10V, the output buffer circuit 18 is about 14-25V, and the drive voltage differs from circuit to circuit. Therefore, since the shift register circuit 16 is required to operate at a low voltage and at a high speed, the shift register circuit 16 is manufactured using high-speed operation type top gate TFTs 300 and 350 and is driven at a high voltage like the level shifter circuit 17 and the output buffer circuit 18. A circuit in which high withstand voltage is prioritized may be manufactured with the bottom gate type TFT 200.
[0081]
In the first embodiment, the bottom gate type TFT 200 is only an n-channel type, but an n-type and a p-type conductivity type may be separately formed by a known CMOS process, and the bottom gate type TFT 200 also has an inverter circuit. Obviously we can do it.
[0082]
In the active matrix panel shown in FIG. 2, examples of TFTs that require high voltage resistance include a protective TFT connected to the lead terminal 14 and a TFT connected to a short link (not shown). . Such a TFT may be manufactured using a high breakdown voltage bottom gate TFT 200.
[0083]
In addition, since holes are less likely to move in the semiconductor layer than electrons, p-channel TFTs do not suffer from ion implantation due to hot carriers and are unlikely to deteriorate. On the other hand, the n-channel TFT is easily deteriorated due to the ion implantation phenomenon, but has a higher mobility than the p-channel TFT. For this reason, the TFTs constituting the drivers 12 and 13 may be fabricated by using high-speed operation type top gate type TFTs as p-channel TFTs and high breakdown voltage type bottom gate type TFTs 200 as n-channel TFTs.
[0084]
In this embodiment, the top gate type TFT is described as a high-speed operation type, and the bottom gate type is described as a high breakdown voltage type. However, as shown in Example 5 (FIG. 10) described later, the top gate type TFT is set to a high breakdown voltage. It is also possible to make a circuit by making the bottom gate type a high-speed operation type.
[0085]
Example 4 FIG. 9 shows a manufacturing process of a TFT of this example.
[0086]
In Example 1, an example in which two types of TFTs having different gate insulating film thicknesses were produced was shown. In this embodiment, a method of manufacturing a bottom gate type TFT in which higher gate voltage resistance is pursued by changing the thickness of the gate insulating film between the bottom gate TFTs. In this embodiment, a method for forming a high breakdown voltage TFT 500, a medium breakdown voltage TFT 550, and a low breakdown voltage (high-speed operation) TFT 600 on the same substrate will be described. The names of these TFTs are for convenience of explanation, and indicate that the thickness of the gate insulating film is gradually reduced from high to low withstand voltage. In this embodiment, the high breakdown voltage TFT 500 and the medium breakdown voltage TFT 550 are bottom gate types, and the high speed operation TFT 600 is a top gate type.
[0087]
As shown in FIG. 9A, gate electrodes 501 and 502 of a high voltage TFT 500 and a medium voltage TFT 550 are formed on a glass substrate 400. Next, a first bottom gate gate insulating film 410 covering the gate electrode 501 is formed to a thickness of 10 nm to 300 nm. In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by plasma CVD and patterned to form a first gate insulating film 410. As a material of the gate insulating film 410, a silicon oxide film or a silicon oxynitride film is used (FIG. 9A).
[0088]
Next, a second bottom gate insulating film 420 made of a silicon oxide film and having a thickness of 100 to 300 nm is formed on the entire substrate 100. The gate insulating film 420 functions as a gate insulating film for the TFTs 500 and 550, and functions as a base film for preventing diffusion of impurities from the substrate 400 in the TFT 600. In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by plasma CVD.
[0089]
Next, island-shaped semiconductor layers 503, 504, and 601 are formed over the gate insulating film 420. The semiconductor layers 503, 504, and 601 are manufactured according to the steps shown in FIGS. 4A and 4B of Embodiment 1 (FIG. 9B).
[0090]
Next, a top gate gate insulating film 430 covering the semiconductor layers 503, 504, and 601 is formed to a thickness of 10 to 150 nm. In this embodiment, a silicon oxynitride film having a thickness of 100 nm is formed by a CVD method. Next, the gate electrode 602 of the high speed operation type TFT 600 is formed of an aluminum film to which a small amount of Sc is added. Then, using a known doping method, the semiconductor layers 503, 504, and 601 are doped with phosphorus or / and boron to form source / drain regions 505 to 508, 603, and 604, and channel formation regions 509, 510, and 605. (FIG. 9C).
[0091]
After the impurities are activated, a silicon nitride film having a thickness of 400 nm is formed as an interlayer insulating film 440 by a plasma CVD method, and a contact hole is formed in this. Next, electrodes 509 to 513 and 607 to 609 are formed from aluminum and subjected to hydrogenation treatment, whereby a high breakdown voltage TFT 500, a medium breakdown voltage TFT 550, and a low breakdown voltage (high speed operation) TFT 600 are completed (FIG. 9D). ).
[0092]
In this embodiment, the gate insulating film of the high breakdown voltage TFT 500 includes a gate insulating film 410 having a thickness of 50 nm and a gate insulating film 420 having a thickness of 200 nm. The gate insulating film of the medium voltage TFT 550 is formed of a gate insulating film 420 having a thickness of 200 nm. The low breakdown voltage TFT 600 gate insulating film is a gate insulating film 430 having a thickness of 100 nm. By making the thickness of each gate insulating film different, three types of TFTs having different characteristics can be manufactured on the same substrate.
[0093]
When this embodiment is applied to an actual integrated circuit, the layout of the high breakdown voltage TFT 500, the medium breakdown voltage TFT 550, and the high-speed operation TFT 600 can be appropriately selected by the designer according to the driving voltage of the TFT and the frequency of the driving signal.
[0094]
For example, when the TFTs 500, 550, and 600 are applied to an active matrix panel, a circuit that prioritizes high-speed operation such as a shift register circuit, a logic circuit, a decoder circuit, and a memory circuit in a source driver or a gate driver has a low withstand voltage. A type TFT 600 is used. A signal processing circuit that prioritizes high breakdown voltage, such as a level shifter circuit and a buffer circuit driven by a relatively high voltage, and a pixel TFT arranged in the pixel portion are configured by a medium breakdown voltage TFT 550. A TFT to which a high power supply voltage such as a short link or an extraction terminal is applied is constituted by a high breakdown voltage TFT 500.
[0095]
In this embodiment, an etching process is used to form the gate insulating film 410. However, when etching is performed, only the gate electrodes 501 and 502 of the bottom gate type TFT are provided as shown in FIG. 9A. Is present. Therefore, since there is no influence on the semiconductor layer of the TFT, reliability is not impaired. In addition, since the film forming / etching conditions for forming the gate insulating film 410 and the selection range of usable means are widened, the formation is easy.
[0096]
Further, as shown in FIG. 9A, the first bottom gate insulating film 410 is formed so as to remain only in the region where the TFT 500 is formed, but also in the region where the top gate type TFT 600 is formed. It can be left to function as a base film of the TFT 600.
[0097]
Example 5 FIG. 10 is a cross-sectional view of a manufacturing process of a TFT of this example.
[0098]
In the first and fourth embodiments, the gate insulating film of the bottom gate type TFT is thickened and the gate insulating film of the top gate type TFT is thinned. However, in this embodiment, the gate insulating film of the bottom gate type TFT is thinned. An example of increasing the thickness of the gate insulating film of the top gate type TFT will be described. In FIG. 10, the bottom gate type TFT 800 is shown on the left side and the top gate type TFT 900 is shown on the right side.
[0099]
A gate electrode 801 of a bottom gate type TFT 800 is formed on a quartz or glass substrate 700. Next, a bottom gate insulating film 710 is formed of a silicon oxide film having a thickness of 100 nm by plasma CVD. The gate insulating film 710 also functions as a base insulating film of the top gate type TFT 900 (FIG. 10A).
[0100]
An intrinsic (I-type) crystalline silicon film having a thickness of 80 nm is deposited on the gate insulating film 710. A crystalline silicon film such as polysilicon is separated into island shapes, and a semiconductor layer 802 of a bottom gate type TFT 800 and a semiconductor layer 901 of a top gate type TFT 900 are formed. A silicon oxide film 720 having a thickness of 200 nm is deposited on the entire surface of the substrate over the semiconductor layers 802 and 901 by plasma CVD. The silicon oxide film 720 constitutes a gate insulating film of the top gate type TFT 900 (FIG. 10B).
[0101]
An aluminum film having a thickness of 4000 to 600 nm, for example, 500 nm is deposited on the silicon oxide film 720 by sputtering, and a thin aluminum oxide film (not shown) is formed on the surface thereof. Then, an aluminum pattern 41 is formed using the resist mask 42. The aluminum pattern 41 constitutes a gate electrode of the top gate type TFT 900. Further, the aluminum oxide film has a function of preventing the surface of the aluminum pattern 43 from being excessively oxidized by anodic oxidation described later (FIG. 10C).
[0102]
Next, an anodic oxidation treatment using the aluminum pattern 41 as an anode in an oxalic acid solution is performed, and a porous (porous) anodic oxide film 43 is formed on the side surface. This growth distance defines the width of an offset region to be formed later (FIG. 10D).
[0103]
Next, after the resist mask 42 is peeled off, an anodic oxidation process using the aluminum pattern 41 as an anode is performed in a tartaric acid solution to form a dense anodic oxide film 904 therearound. The aluminum pattern 41 remaining in the two anodic oxidation steps becomes the gate electrode 902.
[0104]
Next, using the porous (porous) anodic oxide film 43 and the gate electrode 902 as a mask, the silicon oxide film 720 is patterned to form a top gate insulating film 905.
[0105]
In order to make the top gate type TFT 900 a high breakdown voltage type, the silicon oxide film 720 is made thicker than the gate insulating film 710. In the case where through doping that allows the silicon oxide film 720 to pass through cannot be performed due to the increase in thickness, patterning of the silicon oxide film 720 is necessary. If through doping can be performed, patterning is not always necessary. This patterning step has the purpose of forming the offset region in a self-aligned manner using the silicon oxide film 720 as a doping mask (FIG. 10E).
[0106]
Next, after forming a doping mask that covers the channel formation region of the TFT 800, the semiconductor layers 802 and 901 are doped with impurities (phosphorus and / or boron) by a known doping method. As a result, a source region 803, a drain region 804, and a channel formation region 805 are formed in the semiconductor layer 802. On the other hand, in the semiconductor layer 901, a source region 906 and a drain region 907 are formed in a region where no gate insulating film is present. In a region where the gate insulating film 905 exists, a channel formation region 908 and offset regions 909 and 910 are formed (FIG. 10F).
[0107]
Note that by setting the doping process conditions so that the gate insulating film 905 functions as a semi-transparent mask, the regions 909 and 910 are low-concentration impurities whose impurity concentration is lower than that of the source / drain regions 906 and 907. Regions can be formed. Since the offset region and the low concentration impurity region have high resistance, the breakdown voltage characteristics of the TFT 900 can be improved.
[0108]
After removing a doping mask (not shown) on the TFT 800 and activating the doped impurity, a silicon oxide film having a thickness of 400 nm is formed as an interlayer insulating film 730, and a contact hole is formed in the silicon oxide film. Next, a laminated film of titanium / aluminum / titanium is formed and patterned to form electrodes 806, 807, 911, and 912. Through the above steps, a semiconductor integrated circuit having a low breakdown voltage (high-speed operation) bottom gate TFT 800 and a high breakdown voltage top gate TFT 900 on the same substrate is completed (FIG. 10G).
[0109]
Example 6 FIG. 11 is a cross-sectional view illustrating a manufacturing process of a TFT of this example. In this embodiment, as in the first and fourth embodiments, the bottom gate TFT is a high breakdown voltage type and the top gate TFT is manufactured in a high speed operation type.
[0110]
As the gate insulating film of the bottom gate type TFT of the present invention, the base insulating film of the top gate type TFT is used. Conventionally, this base film forms a relatively thick film of about several hundred nm. In the top gate type TFT, the channel formation region is formed in a self-aligned manner by the gate electrode. Therefore, in consideration of these matters, in order to integrate the high voltage type TFT and the high speed operation type TFT, it is necessary to increase the gate insulating film of the bottom gate type TFT and thin the gate insulating film of the top type TFT. The most preferred form is considered.
[0111]
In Examples 1 and 4, the gate insulating film of the top gate type TFT uses a deposited film by the CVD method, but in this example, it is a thermal oxide film. The structure of the gate electrode of the top gate type TFT is salicide. The object of the present embodiment is to further improve the high-speed operation characteristics by combining this thermal oxide film and salicide.
[0112]
On the quartz substrate 1000, a gate electrode 2001 having a width of the bottom gate type TFT 2000 is produced. The material of the gate electrode 2001 is polycrystalline silicon to which phosphorus is added so as to withstand the thermal oxidation process. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used. In order to make the TFT 2000 a high breakdown voltage type, the width of the gate electrode 2000 is set to 2 to 4 μm, and here, 2 μm.
[0113]
Next, a bottom gate insulating film 1010 is formed of a 200 nm thick silicon oxide film by plasma CVD.
[0114]
Next, an intrinsic (I-type) amorphous silicon film having a thickness of 70 nm is deposited on the gate insulating film 1010 by low pressure CVD, and crystallized to form polycrystalline silicon. Known thermal crystallization and laser crystallization are used for crystallization. This polycrystalline silicon film is separated into island shapes, and a semiconductor layer 2002 of a bottom gate type TFT 2000 and a semiconductor layer 3002 of a top gate type TFT 3000 are formed (FIG. 11A).
[0115]
Next, the surfaces of the semiconductor layers 2002 and 3002 are thermally oxidized in an oxidizing atmosphere to form thermal oxide films 51 and 52. In this embodiment, the thickness of the thermal oxide film is 50 nm. Therefore, the thickness of the semiconductor layer is reduced by about 25 nm. The thermal oxide film 52 constitutes a gate insulating film of the top gate type TFT 3000. Therefore, by using the thermal oxide film 52, it is possible to form a dense gate insulating film having a small film interface state even if it is as thin as several tens of nm.
[0116]
A gate electrode 3003 is formed on the thermal oxide film 52 using polycrystalline silicon to which phosphorus is added. The thickness of the gate electrode 3003 is 500 to 800 nm. Here, it is 600 nm. In order to make the TFT 3000 a high-speed operation type, the width of the gate electrode 3003 is set to 1 μm (FIG. 11B).
[0117]
After forming the resist mask 54 covering the channel formation region of the TFT 2000, phosphorus is added to the semiconductor layers 2002 and 3002 by ion doping, and n ^- Regions 54 and 55 are formed. In the semiconductor layers 2002 and 3002, the regions covered with the resist mask 54 and the gate electrode 3003 maintain intrinsic conductivity (FIG. 11C).
[0118]
Next, after removing the resist mask 54, a silicon oxide film or a silicon nitride film having a thickness of 500 nm to 1 μm is formed. In this embodiment, a silicon oxide film 57 (illustrated by a dotted line) having a thickness of 900 nm is formed. Then, a resist mask 57 is formed on the silicon oxide film 57. This mask 57 functions as a mask for patterning the channel stopper 2003 of the bottom gate type TFT 2000.
[0119]
The silicon oxide film 57 is etched by anisotropic dry etching using known RIE (reactive ion etching). By anisotropic etching, the side walls of the silicon oxide are left on the side surfaces of the gate electrode 3000, and the silicon oxide pattern 60 is left under the mask 57.
[0120]
Subsequently, the thermal oxide films 51 and 52 are etched. The thermal oxide film 52 is left under the gate electrode 3003 and the side wall 3004, and a gate insulating film 3005 is formed. On the other hand, a pattern 61 made of a thermal oxide film is left under the mask 57. The laminate of the silicon oxide pattern 60 and the pattern 61 made of the thermal oxide film functions as the channel stopper 2003. The channel stopper 2003 is formed so as to cover the channel formation region and the low concentration impurity regions formed at both ends thereof. That is, the length of the low concentration impurity is determined by the width of the channel stopper 2003 (FIG. 11D).
[0121]
Next, phosphorus is doped into the semiconductor layers 2002 and 3002 by ion doping, and n ⁺ Form a region. In a region not masked by the channel stopper 2003, the gate electrode 3003, and the side wall 3004, n ⁺ Regions 2004, 2005, 3006, and 3007 are formed (FIG. 11E).
[0122]
In the semiconductor layer 2002, n ⁺ Regions 2004 and 2005 become a source region and a drain region, respectively. N covered by the channel stopper 2003 ^- The region 54 becomes a high-resistance low-concentration impurity region 2006, 2007. A region 2009 in which phosphorus is not doped in the two doping steps becomes a channel formation region.
[0123]
On the other hand, in the semiconductor layer 3002, n ⁺ Regions 3006 and 3007 serve as a source region and a drain region, respectively. Also, n covered by the gate electrode 3003 and the side wall 3004 ^- The region 55 becomes low resistance impurity regions 3008 and 3009 having high resistance. A region 3010 not doped with phosphorus in the two doping steps becomes a channel formation region.
[0124]
In this embodiment, the TFTs 2000 and 3000 are both n-channel type, but both n-channel type and p-channel type can be manufactured by a known CMOS process.
[0125]
After activating the doped phosphorus, a metal film 62 for forming silicide is formed. For the metal film 62, titanium, tantalum, molybdenum, tungsten, or the like is used. In this embodiment, a titanium film 62 is formed. Next, the titanium film 62 and silicon (semiconductor layers 2002 and 3002, gate electrode 3003) are reacted by thermal annealing at 550 to 600 ° C.
[0126]
As a result, silicide layers 2011, 2012, 3011 and 3012 are formed in the source / drain regions 2004 and 2005 of the TFT 2000 and the source / drain regions 3006 and 3007 of the TFT 3000 to reduce the resistance, and the upper layer of the gate electrode 3003 is also a silicide layer. 3013 is formed to reduce resistance.
[0127]
The silicide layers 2011, 2012, 3011 to 3013 are for preventing contact deterioration due to an alloy reaction between silicon (source / drain regions and gate electrodes) and metal (wiring). In particular, the TFT 3000 pursues high-speed operation by miniaturization, specifically by shortening the channel length. By forming the silicide layers 3011 and 3012, an effect that the short channel effect accompanying the miniaturization can be suppressed is also obtained. (FIG. 11 (F)).
[0128]
In FIG. 11F, the source / drain regions of the TFTs 2000 and 3000 are all shown as silicided, but the silicide layer does not reach the bottom of the semiconductor layer, and a part of the upper layer of the semiconductor layer is silicided. It can also be made.
[0129]
Next, after the titanium film 62 is removed, an interlayer insulating film 1020 is formed. Here, a 30 nm silicon nitride film and a 900 nm silicon oxynitride film are continuously formed by a plasma CVD method. Next, contact holes are opened in the interlayer insulating film 1020, wirings 2013, 2014, 3014 to 3016 made of aluminum are formed, hydrogenated, and a bottom gate type TFT 2000 having high breakdown voltage characteristics and high speed operation characteristics. A top gate type TFT 3000 is completed on the same substrate 1000 (FIG. 11F).
[0130]
【The invention's effect】
In the present invention, the gate insulating film of the bottom gate type TFT and the base insulating film of the top gate type TFT are shared as the first insulating film, and the gate insulating film (first insulating film) of the bottom gate type TFT is used. The gate insulating film (second insulating film) of the top gate type TFT exists in different layers and is manufactured by different processes. Therefore, it is easy to make the top gate type and bottom gate type gate insulating film thicknesses different from each other without adding or changing processes for controlling the gate insulating film thickness such as etching and film formation. Can be.
[0131]
Accordingly, a TFT that prioritizes high-speed operation at a low voltage and a TFT that prioritizes high breakdown voltage can be formed on the same substrate without impairing the reliability of the TFT. When this is applied to an active matrix panel, reliability and power consumption can be improved.
[0132]
The manufacturing method of the semiconductor integrated circuit of the present invention is based on the manufacturing process of the top gate type TFT, and only the film forming / patterning process for manufacturing the gate electrode of the bottom gate type TFT is added to this process. Moreover, this added process is a known technique. Therefore, the present invention can be easily implemented and is industrially beneficial.
[0133]
In the above-described embodiments, examples in which the present invention is applied mainly to an active matrix panel in which a pixel portion and a driver circuit are integrated have been shown. Furthermore, by using the present invention, not only a driver circuit but also an arithmetic circuit for controlling the driver circuit and a high-speed / low-voltage driving circuit such as a memory circuit such as a DRAM can be used. Can be formed on the same substrate. It is also possible to form a power MOS circuit having a driving voltage of about several tens of volts and an arithmetic circuit driven at about 3 to 5 volts on the same substrate.
[Brief description of the drawings]
1 is a cross-sectional view of an active matrix panel of Example 1. FIG.
FIG. 2 is a block diagram of an active matrix panel.
FIG. 3 is a block diagram of a gate driver.
4 is a cross-sectional view showing a manufacturing process of the active matrix panel of Example 1. FIG.
5 is a cross-sectional view showing a manufacturing process of the active matrix panel of Example 1. FIG.
6 is a cross-sectional view showing a manufacturing process of the active matrix panel of Example 1. FIG.
7 is a cross-sectional view showing another method for performing the doping process of Example 1. FIG.
8 is a cross-sectional view of an active matrix panel of Example 2. FIG.
9 is a cross-sectional view showing a manufacturing step of the TFT of Example 4. FIG.
10 is a cross-sectional view showing a manufacturing step of the TFT of Example 5. FIG.
11 is a cross-sectional view showing a manufacturing step of the TFT of Example 6. FIG.
[Explanation of symbols]
100 substrates
110 Gate insulating film for bottom gate (first insulating film)
120 Gate insulating film for second gate (second insulating film)
130 1st interlayer insulation film (3rd insulation film)
140 Second interlayer insulating film
150 Third interlayer insulating film
200 pixel TFT (bottom gate type TFT)
201 Gate electrode
202 Semiconductor layer
203 Channel formation region
204 Source area
205 Drain region
210 Shading film
211 Pixel electrode
212 Auxiliary capacity
300 n-channel driver TFT (bottom gate type TFT)
350 p-channel driver TFT (bottom gate TFT)
302, 303 Semiconductor layer
304, 305 Gate electrode
306, 307 Channel formation region
308, 309 source region
310, 311 Drain region

Claims (9)

A method for manufacturing a semiconductor device having a bottom gate thin film transistor and a top gate thin film transistor over the same substrate,
Forming a gate electrode of the bottom gate type thin film transistor on the substrate;
Forming a first insulating film so as to cover the gate electrode of the bottom gate type thin film transistor;
Forming a semiconductor layer of the bottom gate thin film transistor and a semiconductor layer of the top gate thin film transistor on the first insulating film;
Forming a second insulating film having a thickness different from the thickness of the first insulating film on the semiconductor layer of the bottom gate type thin film transistor and the semiconductor layer of the top gate type thin film transistor;
Forming a gate electrode of the top gate type thin film transistor on the second insulating film;
Forming a third insulating film so as to cover the semiconductor layer of the bottom gate type thin film transistor and the semiconductor layer of the top gate type thin film transistor and the gate electrode;
Etching the third insulating film forms a channel stopper for the bottom gate thin film transistor, and forms a side wall on the side surface of the gate electrode of the top gate thin film transistor,
Etching the second insulating film using the channel stopper of the bottom gate thin film transistor and the gate electrode of the top gate thin film transistor and the side wall as a mask,
Impurities are respectively added to the bottom gate type thin film transistor semiconductor layer and the top gate type thin film transistor semiconductor layer using the bottom gate type thin film transistor channel stopper and the top gate type thin film transistor gate electrode and the side wall as a mask. Forming a source region and a drain region of the bottom gate thin film transistor, and a source region and a drain region of the top gate thin film transistor,
Forming a metal film on a source region and a drain region of the bottom gate type thin film transistor and a source region and a drain region of the top gate type thin film transistor;
A semiconductor characterized by reacting the metal film, the source region and drain region of the bottom gate type thin film transistor, and the source region and drain region of the top gate type thin film transistor, respectively, by thermal annealing to form a silicide layer Device fabrication method. 2. The silicide layer according to claim 1, wherein the silicide layer is formed by silicidizing a source region and a drain region of the bottom gate thin film transistor and a part of an upper layer of each of the source region and the drain region of the top gate thin film transistor. A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device having a bottom gate thin film transistor and a top gate thin film transistor over the same substrate,
A gate electrode of the bottom gate type thin film transistor formed on the substrate,
Forming a first insulating film so as to cover the gate electrode of the bottom gate type thin film transistor ;
Forming a semiconductor layer of the bottom gate thin film transistor and a semiconductor layer of the top gate thin film transistor on the first insulating film;
Forming a second insulating film having a thickness different from the thickness of the first insulating film on the semiconductor layer of the bottom gate type thin film transistor and the semiconductor layer of the top gate type thin film transistor ;
Forming a gate electrode of the top gate type thin film transistor made of polycrystalline silicon doped with phosphorus on the second insulating film;
Forming a resist mask so as to cover the channel formation region of the bottom gate type thin film transistor;
The resist mask and the gate electrode of the top gate type TFT as a mask, the bottom gate type semiconductor layer of the thin film transistor and the addition of each impurity to the semiconductor layer of the top gate type thin film transistor, the impurity region of the bottom gate type thin film transistor And after forming the impurity region of the top gate type thin film transistor ,
Forming a third insulating film so as to cover the semiconductor layer of the bottom gate type thin film transistor and the semiconductor layer of the top gate type thin film transistor and the gate electrode;
Etching the third insulating film forms a channel stopper for the bottom gate thin film transistor, and forms a side wall on the side surface of the gate electrode of the top gate thin film transistor ,
And the channel stopper of the bottom gate type thin film transistor, and the side walls and the gate electrode of the top gate type TFT as a mask, etching the second insulating film,
Impurities are added to the impurity region of the bottom gate type thin film transistor and the impurity region of the top gate type thin film transistor, respectively , using the channel stopper of the bottom gate type thin film transistor and the gate electrode and the side wall of the top gate type thin film transistor as a mask. Forming a source region, a drain region, and a low concentration impurity region of the bottom gate thin film transistor, and a source region, a drain region, and a low concentration impurity region of the top gate thin film transistor ,
Forming a metal film on the source region and drain region of the bottom gate type thin film transistor, and on the source region, drain region, and gate electrode of the top gate type thin film transistor ;
By thermal annealing, and the metal film, a source region and a drain region of the bottom gate type thin film transistor, and the source region of the top gate type TFT, the drain region, and a gate electrode is reacted respectively, to form a sheet Risaido layer A method for manufacturing a semiconductor device. 4. The silicide layer according to claim 3 , wherein the silicide layer is formed by siliciding a part of an upper layer of each of a source region and a drain region of the bottom gate type thin film transistor and a source region, a drain region, and a gate electrode of the top gate type thin film transistor. A method for manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film has a thickness of 150 to 300 nm. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the second insulating film is 100 nm or less. 7. The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is a silicon oxide film. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the width of the gate electrode of the bottom gate type thin film transistor is set to 2 to 4 [mu] m. In any one of claims 1 to 8, wherein the metal film, a method for manufacturing a semiconductor device comprising titanium, tantalum, molybdenum, that is one or tungsten.

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