JPH01183854A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower the wiring resistance of source-drain sections, and to form a thin- film transistor positively in a large area by forming a reaction layer onto the surface of a semiconductor region in high impurity concentration as a source-drain, connecting an electrode for a wiring to the reaction layer and forming arrangement in which the electrode for the wiring is not superposed on a gate electrode. CONSTITUTION:A reaction layer 8 is shaped onto the surface of a semiconductor region in high impurity concentration as source-drain, electrodes 6 for wirings composed of a metal are connected to the reaction layer 8, and arrangement in which the electrodes 6 for the wirings are not superposed to a gate electrode 2 is formed. Conse quently, alignment accuracy among the gate 2 and the electrodes 6 for the wirings can be brought to gate-electrode width or more. That is, at least one of the source- drain sides is separated spatially among the gate electrode 2 and the electrodes 6 for the wirings connected to the source-drain, but the reaction layer 8 reacting between the surface of the source-drain semiconductor region in high impurity concentration and the metal is shaped together with the source-drain semiconductor region between the gate electrode 2 and the electrodes 6. Accordingly, sheet resistance is lowered, series resistance in the source or the drain can be ignored, and a large area and improvement in performance can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) This invention relates to a thin film transistor used for driving a liquid crystal display or the like.

(Prior Art) Amorphous silicon (hereinafter abbreviated as a-5L) thin film transistors (abbreviated as TPT) are widely used as active matrix elements in liquid crystal displays. Currently, 3- to 6-inch LCD televisions have been developed and some are commercially available.

Several structures have been considered for amorphous silicon thin film transistors, but self-alignment TFTs have the following advantages not found in other structures. That is, ■ there is no additional capacitance due to overlap between the gate, source, and drain; and ■ it is easy to manufacture because there is no strict requirement for alignment accuracy between the gate, source, and drain.

As a result, as an active matrix, gate line 1
One example is that the actual capacity can be reduced. Also,
Capacitance between gate and source (gate-source capacitance Cgs
) can be made constant regardless of alignment accuracy, and when obtaining a display over a large area, the penetration of the gate pulse to the pixel electrode voltage can also be made constant.

On the other hand, several methods have been proposed for manufacturing self-alignment TPTs. In this case, n-type a
-5L and wiring electrodes must be formed in self-alignment with respect to the gate.

FIG. 7 shows an example of this, in which an n-type a-3i, 52° wiring electrode layer 62 is deposited on the positive resist left on the gate by back exposure, and patterned by lift-off.

n-type a-3 which becomes source and drain in a-Si TPT
The i-layer 52 has a resistivity of about 10 2 Ω, and a sheet resistance of 2×10 7 Ω per 500 people, which is quite high. Therefore, in the a-3i TFT, the n-layer is usually used only as a rectifying junction with the channel, and a metal is provided on the n-layer to lower wiring resistance.

In a self-alignment type TPT, the wiring electrode layer can be self-aligned in the same way as the n-layer, or it can be formed by aligning it with an exposure device so that it overlaps the insulating V (indicated by 7 in Figure 7) above the channel. be. However, the latter is undesirable because it loses the second feature of self-alignment. Further, the former is not desirable because if lift-off is used as described above, the lift-off may be incomplete and the yield will be reduced.

(Problems to be Solved by the Invention) The present invention solves the problem of complicating the process caused by the fact that the sheet resistance of the n10 layers forming the source and drain regions found in a-5i TFT is high and cannot be used for wiring. The aim is to prevent this from becoming more difficult. In other words, the purpose is to reduce the wiring resistance of the source and drain portions to reliably form a large number of transistors in a large area, such as an active matrix.

[Structure of the invention]

(Means for Solving the Problems) A thin film transistor according to the present invention has a gate electrode, a gate insulating film, an active layer made of amorphous silicon, and a semiconductor region with a high impurity concentration that serves as a source and a drain, and is connected to these. In a thin film transistor having two wiring electrodes, a reaction layer is provided on the surface of the semiconductor region with high impurity concentration, which serves as the source and drain, and a wiring electrode made of metal is connected to this reaction layer. The present invention is characterized in that the electrode is arranged so as not to overlap the gate electrode. The metal for forming the reaction layer is any one of No, Cr, and Ti.

Next, the IB manufacturing method involves gate electrode and gate insulation.

It is formed on the surface of the semiconductor region that becomes the source and drain in a thin film transistor that has an active layer made of amorphous silicon, a semiconductor region with high impurity concentration that becomes the source and drain, and two wiring electrodes connected to these. After exposing the semiconductor layer by removing a layer containing at least an insulating film formed on the amorphous silicon active layer, a metal layer is deposited, and at least a wiring electrode of this metal layer is exposed. It is characterized by etching away the other parts. The method is characterized in that semiconductor regions with high impurity concentration, which become sources and drains, are formed by discharging and decomposing doping impurity gas and injecting it into the i-layer amorphous silicon using an electric field.

(Function) In a-8i TPT, the field effect mobility is small, and the channel length is desired to be as small as 10- or less.

When self-alignment is used, the width of the gate electrode becomes the same as the channel length, but according to the present invention, the distance between the wiring electrodes connected to the source and drain can be made larger than the width of the gate electrode. It becomes possible to achieve alignment accuracy between the gate electrodes to a width greater than or equal to the width of the gate electrode (10- or greater). In other words, between the gate electrode, that is, the end of the channel part, and the wiring electrode connected to the source and drain, at least one of the source and drain sides is spatially separated, but the impurity concentration between them is Since a reaction layer is provided on the surface of the device along with the source and drain semiconductor regions having high resistance to metal, the sheet resistance is reduced and the series resistance at the source or drain can be ignored.

(Example) Hereinafter, an example according to the present invention will be described with reference to FIG. Further, the manufacturing process is shown in FIG. 2, and will be explained based on the same figure.

A gate electrode 2 is patterned on a transparent glass substrate 1. The gate electrode is made of an opaque metal (e.g. MO, 7a,
Cr, etc.). On top of this, a gate insulating film 3. i
Layer amorphous silicon film4. Insulating films 7 for protecting the channel portion are sequentially laminated. The gate insulating film is 5iOX or Si.
About 4000 people for Nx film, 200-500 people for i-layer amorphous silicon film, 5iOy or Si for protective insulating film
The thickness was approximately 2,000 N layers.

A positive resist is applied on top of this, and backside exposure is performed from the glass substrate side. The insulating film is transparent at the wavelength of the exposure light source, and the i-layer a-SL absorbs light but is very thin so that light passes through it.The uppermost resist is exposed except for the part where the gate is present (second Diagram a).

In the figure, 9a is an unexposed resist portion, and 9b is an exposed resist portion. After development, insulating film 7 is formed using the resist as a mask.
etching.

The insulating film 7 protects the surface of the semiconductor in the channel portion and at the same time functions as a mask when forming the next layer.

That is, only the exposed a-5L can be doped with impurities. Doping is performed by decomposing a gas containing phosphine (PH,) by high-frequency discharge and accelerating it with a voltage applied to the substrate.
This was done by injecting phosphorus (P). Set the substrate temperature to 200~3
It is activated by heating to 00℃, and the resistivity is 10'Ωam ~
It became 103Ω■. Note that since 1ra-si is thin, phosphorus was introduced into almost the entire film.

(FIG. 2b) Next, No was deposited on the entire surface by sputtering. The metal film 10 was deposited at room temperature and reacted with a-3i to form a reaction layer 8. This reaction layer 8 is very thin, about 50 to 200, but the sheet resistance was significantly lower than n''a-3i. In the case of No, it was 102 to 10'Ω/mouth.a-
The on-resistance of 3i TPT is 1o"~107 in sheet resistance.
Since it is Ω/gate, the resistance of the reaction layer up to the wiring electrode described later can be made sufficiently smaller than the on-resistance. (Figure 2 C
) Next, a-5i is patterned into an island shape, a contact hole is made, a No. i#1 layer film is deposited, and this is patterned to form a wiring electrode 6.

The wiring electrode 6 is connected to the source, so that it does not overlap with the gate 1-2.
Pattern widely between drains. Mo between the end of the channel and the wiring electrode is removed by etching. (FIG. 2d) From the above process, it can be seen that there is no increase in the number of photolithography operations or processes, except for the A0 sputtering for forming the reaction layer 8. In particular, in the active matrix, which does not use lift-off and requires fabrication of a large number of transistors in a large area, the probability of transistor failure is significantly improved compared to when lift-off is used.

It was also found that the reaction layer 8 used here had a low sheet resistance but was thin, and would melt when a large current (several mA or more) was applied to it. Therefore, if there is a pinhole or the like in the gate insulating film and the gate is in contact with a-3L, when the above current flows between the gate, source, and drain, it will melt in the area where only the reaction layer exists, and the gate and wiring Short circuits between electrodes can be prevented in a self-healing manner. Active matrix can prevent serious defects called line defects.

The distance between the gate and the wiring electrode is the allowance for alignment of the wiring electrode with the substrate, and the larger it is, the looser the alignment accuracy of the exposure machine can be, which means that a simpler exposure machine can be used. . In addition, as the display area of the glass substrate increases, warp deformation due to thermal processing becomes a problem.
Since the looser the alignment precision is, the larger the area can be handled, it is also possible to use glass such as soda lime glass, which has a low melting point and is inexpensive but easily deformed, resulting in a reduction in overall costs.

In this example, the reaction layer sheet resistance is 10-" to 10-4 times the channel sheet resistance when on, so if the wiring electrode is provided with the same width as the channel width, the distance between the gate wiring electrode and the channel If the channel length is 5 to IO/ffi, it is possible to have a minimum separation of 50 μm, and it can be said that sufficient alignment margin can be obtained even for a 40-inch diagonal display.

In this embodiment, impurities were implanted into the i-layer a-5i by plasma doping, but ion implantation may also be used. In addition, A0 was used as the metal forming the reaction layer, but Cr
It has been confirmed that Ti has a similar effect.

Next, another embodiment is shown in FIG. In this case, after patterning the insulating film 7 by backside exposure as shown in FIG.
Approximately 200 people will deposit the n middle layer. Thereafter, a negative resist is applied, and the resist is exposed again by backside exposure to remove only the top of the gate, and the n-middle layer is removed by etching.

After forming the n+ layer, the TPT is completed using the same process as described above.

This method has the advantage that the n+ layer has high film quality and good bonding characteristics with the i layer because doping is not performed.

Next, yet another embodiment is shown in FIG. Although the wiring electrode is provided on the opposite side of the gate across the semiconductor in the above example, it may be provided on the same side. The n middle layer was formed by doping.

Further, as another embodiment of the present invention, a planar type is shown in FIG. This is I-layer A-5L.

The gate insulating film and the gate 11 are laminated in this order, and the gate 1
Simultaneously with the patterning of step 1, the gate insulating film 31 is also patterned, the exposed i-layer portion is doped, and metal for forming a reaction layer is deposited and etched. The wiring electrode can be formed apart from the gate.

In this case, a feature is that backside exposure is unnecessary.

Furthermore, after forming the wiring electrodes in advance, the TPT can be manufactured using the same process as shown in FIG. 5, and this is shown in FIG.

Above, from FIG. 4 to FIG. 6, examples with different TPT structures have been shown, but in each case, the wiring electrode can be formed in various ways, and the selection can be made depending on the material, layout, etc. of the wiring part in the active matrix. It expands the

〔Effect of the invention〕

According to the present invention, it is possible to significantly reduce the accuracy of alignment between the wiring electrode connected to the source and drain and the gate or semiconductor layer.

In particular, with self-alignment, source and drain n+ (
In combination with forming p÷)a-5i, it is possible to expand the margin of alignment accuracy while suppressing variations in TPT characteristics due to exposure deviation over a large area, realizing a large area and high performance of the active matrix. do. A margin in alignment accuracy gives a margin in the performance of the exposure machine, making it possible to use an inexpensive exposure machine, resulting in improvements in total cost and throughput. Furthermore, it gives room for the glass to undergo warp deformation, making it possible to use inexpensive glass such as soda lime glass, resulting in a reduction in costs.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a TPT according to an embodiment of the present invention, and FIG.
Figures a and d are cross-sectional views showing the manufacturing process of TPT in order of process, Figures 3 to 6 are cross-sectional views each showing different embodiments, and Figure 7 is a cross-sectional view showing the TPT manufacturing process in order of process. 1...Glass substrate 2.21...Gate electrode 3.31...Gate insulating film 4...I-layer amorphous silicon 5...N+
Layer amorphous silicon (by doping to the i layer) 51, 52...n ten-layer amorphous silicon (by doping during film formation) 6.61.62... Wiring electrode 7... Insulation for protecting the channel part Membrane 8...Reaction layer agent Patent attorney Inoue -M/: Garas λ (1 anti 2: Puto/ in the ditch 1: → 1 nel aho "lay 1 v color [required 1 figure zo α: 10麟1尤t＊2F puD:'Mist Party Shist No. 2 11!Q (%4f)?lo:Metal film Otsu:E6Shiroka Kao 5th Ward 2 (I02) h/: n'4 a -5L !3 Figure 61: Electrical thread Figure 4 Figure 5 Figure 6 q: l-gister end Figure 7

Claims (2)

[Claims] (1) In a thin film transistor having a gate electrode, a gate insulating film, an active layer made of amorphous silicon, a semiconductor region with a high impurity concentration serving as a source and a drain, and two wiring electrodes connected to these, A reaction layer is provided on the surface of a semiconductor region with a high impurity concentration that serves as a source and a drain, and a wiring electrode is connected to this reaction layer, and the wiring electrode is arranged so as not to overlap the gate electrode. Thin film transistor. (2) A source in a thin film transistor having a gate electrode, a gate insulating film, an active layer made of amorphous silicon, a semiconductor region with a high impurity concentration serving as a source and a drain, and two wiring electrodes connected to these, The reaction layer with the metal formed on the surface of the semiconductor region that will become the drain is formed by exposing the semiconductor layer by removing at least the layer containing the insulating film formed on the amorphous silicon active layer, and then depositing the metal layer. A method for manufacturing a thin film transistor, characterized in that the metal layer is formed by etching away at least a portion of the metal layer other than the wiring electrode.