JP2012151417A - Thin-film transistor circuit substrate and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor circuit substrate having a high-performance thin-film transistor without drastically increasing the number of manufacturing steps, and to provide a method of manufacturing the thin-film transistor circuit substrate.SOLUTION: A thin-film transistor circuit substrate has: a gate electrode arranged on an insulation substrate; a gate insulating film arranged on the gate electrode; a semiconductor layer formed of polysilicon arranged on the gate insulating film, and including a channel region located immediately above the gate electrode, a low-concentration impurity region adjacent to the channel region and including an impurity of a higher concentration than the channel region, and a high-concentration impurity region adjacent to the low-concentration impurity region and including an impurity of a higher concentration than the low-concentration impurity region; a protection film arranged on the channel region and the low-concentration impurity region, and in which a film thickness of a part immediately above the channel region is larger than that of a part immediately above the low-concentration impurity region; and an electrode electrically connected to the high-concentration impurity region.

Description

  Embodiments described herein relate generally to a thin film transistor circuit board and a method for manufacturing the same.

  Thin film transistors (hereinafter sometimes referred to simply as TFTs) are widely used in various flat display devices such as liquid crystal display devices and organic electroluminescence display devices. In such a flat display device, the TFT may be incorporated as a drive circuit in addition to being used as a switching element of each pixel. For this reason, high performance of the TFT is required.

  Therefore, there is an increasing need for using a p-Si TFT having a polysilicon (p-Si) semiconductor layer. Such a p-Si TFT has a mainstream of an inverted stagger structure or a top gate TFT structure. In a liquid crystal display device equipped with a backlight, the light intensity of the backlight is increasing year by year in accordance with the demand for higher brightness. For this reason, when a backlight is arranged on the array substrate side, a light leakage current due to the incidence of the backlight light on the channel semiconductor layer of the p-Si TFT may become a problem.

  In order to solve such a problem, for example, in the case of the top gate TFT structure, a configuration in which a backlight metal is shielded by forming a light-shielding metal film under the channel semiconductor layer of the p-Si TFT. Proposed. In such a structure, a process of forming a metal film, a process of patterning the metal film, a process of connecting to a wiring for maintaining a potential so that the metal film is not in a floating state are required, and the number of manufacturing processes is increased. Resulting in.

  On the other hand, in the case of the bottom gate TFT structure, since the gate electrode is originally formed under the channel semiconductor layer, the gate electrode shields the backlight light. For this reason, it is not necessary to increase the number of manufacturing steps.

  However, in the bottom gate TFT structure, the channel length becomes long from the viewpoint of the accuracy (L / S size and alignment accuracy) of the photolithography process, and the ON current does not increase and it is difficult to improve the performance. In addition, a high drain breakdown voltage is required for a product with a high driving voltage of the display element, and an LDD (Light Doped Drain) region must be formed in the case of an N-type TFT. In order to form such an LDD region, the number of manufacturing steps increases.

JP 2000-156504 A

  An object of the present embodiment is to provide a thin film transistor circuit substrate having a high performance thin film transistor and a method for manufacturing the thin film transistor circuit substrate without significantly increasing the number of manufacturing steps.

According to this embodiment,
A channel formed by a gate electrode disposed on an insulating substrate, a gate insulating film disposed on the gate electrode, and polysilicon disposed on the gate insulating film, and located immediately above the gate electrode A region, a low concentration impurity region adjacent to the channel region and containing a higher concentration impurity than the channel region, and a high concentration adjacent to the low concentration impurity region and containing a higher concentration impurity than the low concentration impurity region. A semiconductor layer including a concentration impurity region, a protective film disposed on the channel region and the low concentration impurity region, and a film thickness directly above the channel region is greater than a film thickness directly above the low concentration impurity region; There is provided a thin film transistor circuit substrate comprising an electrode electrically connected to the high concentration impurity region.

According to this embodiment,
A gate electrode is formed on an insulating substrate, a gate insulating film and a semiconductor layer made of polysilicon are sequentially formed on the gate electrode, and a central portion is directly above the gate electrode and on the semiconductor layer. Forming a step-like protective film whose thickness is thicker than the thickness of both ends sandwiching the central part, implanting impurities into the semiconductor layer, and forming a channel region directly under the central part of the protective film Forming a low-concentration impurity region directly below both ends of the protective film, forming a high-concentration impurity region in a region exposed from the protective film, and over the protective film and the semiconductor layer exposed from the protective film Forming an electrode seed layer for plating, forming a plating resist exposing the electrode formation region on the electrode seed layer, and plating the electrode formation region by electrolytic plating using the plating resist as a mask; The power There is provided a method of manufacturing a thin film transistor circuit board, wherein a plating layer is formed on a seed layer, the plating resist is removed, and the electrode seed layer is removed using the plating layer as a mask. .

FIG. 1 is a plan view schematically showing a configuration example of a thin film transistor included in the thin film transistor circuit substrate of the present embodiment. FIG. 2 is a cross-sectional view schematically showing a configuration of a thin film transistor circuit substrate including the thin film transistor shown in FIG. FIG. 3 is a schematic cross-sectional view for explaining an example of a process for forming a gate electrode of the thin film transistor shown in FIG. FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate of the present embodiment. FIG. 5 is a schematic cross-sectional view for explaining an example of a process for forming a protective film. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate of the present embodiment. FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate of the present embodiment. FIG. 8 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate of the present embodiment. FIG. 9 is a cross-sectional view schematically showing a configuration of a thin film transistor circuit substrate including a thin film transistor in a modification of the present embodiment.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a plan view schematically showing a configuration example of a thin film transistor A provided in the thin film transistor circuit board of the present embodiment.

  The thin film transistor A includes a gate electrode WG, a semiconductor layer SC, a source electrode WS, a drain electrode WD, and the like. The gate electrode WG is, for example, one of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), chromium (Cr), or at least one of these. It is formed by an alloy including one. Such a gate electrode WG is electrically connected to a gate wiring (not shown).

  The semiconductor layer SC is located above the gate electrode WG and is made of polysilicon (p-Si). The source electrode WS and the drain electrode WD are located above the semiconductor layer SC. For example, copper (Cu), magnesium (Mg), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W) , Tantalum (Ta), chromium (Cr), or an alloy containing at least one of them. The source electrode WS is electrically connected to a source wiring (not shown).

  FIG. 2 is a cross-sectional view schematically showing the configuration of the thin film transistor circuit substrate 1 including the thin film transistor A shown in FIG. The cross-sectional view of the thin film transistor A shown here corresponds to a cross-sectional view taken along the line II-II.

  That is, the thin film transistor circuit substrate 1 is formed by using an insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The thin film transistor circuit substrate 1 includes a thin film transistor A formed on an insulating substrate 10. In the illustrated example, the thin film transistor circuit substrate 1 includes a gate lead portion B and a capacitor C.

  On the insulating substrate 10, the gate electrode WG constituting the thin film transistor A, the gate wiring GL of the gate lead-out portion B, and the auxiliary capacitance line CL of the capacitor C are arranged. The gate line GL and the auxiliary capacitance line CL can be formed of the same material as the gate electrode WG. Note that, here, the gate electrode WG, the gate wiring GL, and the auxiliary capacitance line CL are illustrated as a single layer, but may be a stacked body in which a plurality of conductive layers are stacked.

  A base insulating film 11 is disposed on the insulating substrate 10. The base insulating film 11 does not cover the gate electrode WG, the gate wiring GL, and the storage capacitor line CL, but is positioned therebetween. Such a base insulating film 11 is formed of, for example, a silicon oxide film (SiO).

  A gate insulating film 12 is disposed on the gate electrode WG and the base insulating film 11. The gate insulating film 12 is also disposed on a part of the gate line GL and the auxiliary capacitance line CL. Such a gate insulating film 12 is formed of, for example, a silicon oxide film (SiO).

  The semiconductor layer SC is disposed on the gate insulating film 12. Further, the end face of the semiconductor layer SC is located immediately above the end face of the gate insulating film 12. The semiconductor layer SC constituting the thin film transistor A includes a channel region SCC located immediately above the gate electrode WG, a low concentration impurity region SCL adjacent to the channel region SCC and containing a higher concentration impurity than the channel region SCC, and a low concentration It includes a high concentration impurity region SCH that is adjacent to the impurity region SCL and contains a higher concentration impurity than the low concentration impurity region SCL.

  The low concentration impurity region SCL is formed on both sides of the channel region SCC. The high concentration impurity region SCH is formed at both ends of the semiconductor layer SC with the channel region SCC and the low concentration impurity region SCL interposed therebetween. One high concentration impurity region SCH functions as a source region SCS, and the other high concentration impurity region SCH functions as a drain region SCD. Note that such a low concentration impurity region SCL and a high concentration impurity region SCH contain phosphorus (P) as an impurity. The channel region SCC contains almost no impurities.

  In the gate lead-out part B and the capacitor C, the semiconductor layer SC disposed on the gate insulating film 12 contains an impurity having a concentration similar to that of the high-concentration impurity region SCH.

  The protective film PT is disposed on the channel region SCC and the low concentration impurity region SCL of the semiconductor layer SC. The protective film PT is formed in a stepped shape in which the film thickness T1 immediately above the channel region SCC is thicker than the film thickness T2 directly above the low-concentration impurity region SCL. In the present embodiment, the film thickness corresponds to the length along the normal direction of the main surface of the insulating substrate 10.

  The high concentration impurity region SCH of the semiconductor layer SC is exposed from the protective film PT. Further, the protective film PT is not disposed on the gate lead portion B and the capacitor C. For this reason, in the gate lead-out portion B and the capacitor C, the semiconductor layer SC is exposed from the protective film PT. Such a protective film PT is formed of, for example, a silicon oxide film (SiO) or a silicon nitride film (SiN).

  As electrodes constituting the thin film transistor, the source electrode WS and the drain electrode WD are each electrically connected to the high concentration impurity region SCH. The source electrode WS and the drain electrode WD are formed to be separated from each other, and a central portion having the thickness T1 of the protective film PT is exposed between them.

  The source electrode WS is electrically connected to the source region SCS which is one high concentration impurity region SCH. The drain electrode WD is electrically connected to the drain region SCD which is the other high concentration impurity region SCH.

  The source electrode WS and the drain electrode WD are a stacked body in which two conductive layers are stacked. That is, the source electrode WS and the drain electrode WD include a first conductive layer E1 and a second conductive layer E2 stacked on the first conductive layer E1. In the illustrated example, the first conductive layer E1 is stacked on the high concentration impurity region SCH and the protective film PT. The second conductive layer E2 has a thickness greater than that of the first conductive layer E1. For example, immediately above the high-concentration impurity region SCH, the first conductive layer E1 has a film thickness T11, while the second conductive layer E2 has a film thickness T21 larger than the film thickness T11.

  The first conductive layer E1 is formed with a substantially uniform film thickness along the steps of the high concentration impurity region SCH, the end portion having the film thickness T2 of the protective film PT, and the central portion having the film thickness T1. That is, in the first conductive layer E1, the film thickness T11 immediately above the high-concentration impurity region SCH is substantially the same as the film thickness T12 directly above the protective film PT. The film thicknesses T11 and T12 of the first conductive layer E1 are, for example, about 50 nm. For example, the first conductive layer E1 is formed of a copper alloy containing at least magnesium (Mg) and aluminum (Al).

  On the other hand, the second conductive layer E2 is not easily affected by the underlying step, and its upper surface is substantially flat. That is, in the second conductive layer E2, the film thickness T21 immediately above the high concentration impurity region SCH is thicker than the film thickness T22 directly above the protective film PT. Such second conductive layer E2 is formed of, for example, copper (Cu).

  The lead electrode BE of the gate lead portion B is in contact with the gate wiring GL through a contact hole formed in the gate insulating film 12. The capacitance forming part CE of the capacitor C is formed on the semiconductor layer SC. In the example shown here, the extraction electrode BE and the capacitor formation portion CE are a stacked body in which the first conductive layer E1 and the second conductive layer E2 are stacked in the same manner as the source electrode WS and the like. Note that the extraction electrode BE and the capacitance forming portion CE may be a single layer, which may be a single layer or a laminate, for example, copper (Cu), magnesium (Mg). ), Aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), chromium (Cr), or an alloy containing at least one of these. .

  Next, a method for manufacturing the thin film transistor circuit board will be described.

  FIG. 3 is a schematic cross-sectional view for explaining an example of a process for forming the gate electrode WG of the thin film transistor A shown in FIG.

  First, as shown by (A) in the figure, a gate seed layer GSL is formed on the insulating substrate 10. In such a gate seed layer GSL, after forming a seed layer material on the insulating substrate 10, a resist is formed immediately above a region where the gate seed layer GSL is to be formed, and this resist is used as a mask for the seed layer material. Is formed by selectively removing. The resist applied at this time is formed of a resin material patterned by a photolithography process. The gate seed layer GSL is formed of, for example, copper (Cu) alone or an alloy containing copper (Cu) as a main component.

  Then, for example, a silicon oxide film IS is formed on the insulating substrate 10 and the gate seed layer GSL as shown in FIG. Then, as shown by (C) in the drawing, a base insulating film 11 exposing the gate seed layer GSL is formed on the insulating substrate 10. Such a base insulating film 11 is formed by forming a resist in a region corresponding to the silicon oxide film IS immediately above the gate seed layer GSL and selectively removing the silicon oxide film IS using the resist as a mask. Is done. The resist applied at this time is formed of a resin material patterned by a photolithography process.

  Then, as shown by (D) in the figure, the plating layer ML is formed on the gate seed layer GSL by electrolytic plating using the base insulating film 11 as a mask. This plating layer ML is formed of, for example, copper (Cu). As a result, the gate electrode WG made of a stacked body of the gate seed layer GSL and the plating layer ML is formed. Since the upper surface WGT of the gate electrode WG formed in this way forms a substantially flat plane with the upper surface 11T of the base insulating film 11, the base of the semiconductor layer formed in the subsequent process can be flattened. It becomes possible.

  Here, the manufacturing process of the gate electrode WG has been described. However, the gate wiring GL and the auxiliary capacitance line CL may be manufactured by a similar method. Further, as a method for manufacturing the gate electrode WG, the gate line GL, the auxiliary capacitance line CL, etc., a method simpler than the above method may be applied. For example, the gate electrode WG, the gate wiring GL, and the auxiliary capacitance line CL may be formed by forming a gate material on the insulating substrate 10 and patterning the gate material by a photolithography process.

  FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate 1 of the present embodiment.

  First, as shown by (A) in the figure, the gate electrode WG is formed on the insulating substrate 10. In the example shown here, similarly, the gate wiring GL and the auxiliary capacitance line CL are formed on the insulating substrate 10. On the insulating substrate 10, a base insulating film 11 exposing the gate electrode WG, the gate wiring GL, and the auxiliary capacitance line CL is formed.

  Subsequently, as shown by (B) in the drawing, the gate insulating film 12 and the semiconductor layer SC are sequentially formed on the gate electrode WG. Thereafter, the semiconductor layer SC is crystallized to form a polysilicon (p-Si) semiconductor layer.

  Subsequently, as shown by (C) in the drawing, a protective film material PTM functioning as an etching stopper layer is formed on the semiconductor layer SC. This protective film material PTM is formed of, for example, a silicon oxide film or a silicon nitride film. Then, a protective film resist R1 for patterning the protective film material PTM is formed on the protective film material PTM. This protective film resist R1 is formed in a stepped shape in which the film thickness of the central part is thicker than the film thickness of both end parts sandwiching the central part by exposing the photosensitive resin material to halftone. The protective film resist R1 is formed immediately above the gate electrode WG. The channel length of the thin film transistor formed thereafter is determined by the resolution of the exposure machine applied in the photolithography process for forming this protective film resist R1.

  FIG. 5 is a schematic cross-sectional view for explaining an example of a process for forming the protective film PT.

  As shown in FIG. 4C, after forming the protective film resist R1 on the protective film material PTM, as shown in FIG. 5A, the protective film resist R1 is formed by dry etching. The exposed protective film material PTM is removed. Then, as shown in FIG. 5B, both ends of the protective film resist R1 are removed by ashing. As a result, the protective film material PTM located immediately below both ends of the protective film resist R1 is exposed from the protective film resist R1.

  Then, as shown in FIG. 5C, the protective film material PTM exposed from the protective film resist R1 is not etched and completely removed by dry etching, but a film immediately below the protective film resist R1. Reduce film thickness over thickness. As a result, the film thickness at the center is T1, and the film thickness at both ends sandwiching the center is T2 which is thinner than the film thickness T1 (however, the film thickness T2 is a finite value larger than zero. , 50 to 130 nm) is formed. This protective film PT is formed immediately above the gate electrode WG and on the semiconductor layer SC.

  FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate 1 of the present embodiment.

  As shown in FIG. 5C, a step-like protective film PT is formed on the semiconductor layer SC, and then left on the protective film PT as shown in FIG. The protective film resist R1 is removed.

  Subsequently, as shown in FIG. 6B, impurities are implanted into the semiconductor layer SC to form a channel region SCC immediately below the central portion PTC of the protective film PT. A low concentration impurity region SCL is formed immediately below, and a high concentration impurity region SCH is formed in a region exposed from the protective film PT.

  In this embodiment, phosphorus (P) is implanted in two portions as impurities. In the first impurity implantation step, impurities are implanted into the semiconductor layer SC exposed from the protective film PT. At this time, impurities are implanted under a low acceleration condition (for example, 20 keV) in which impurities are not implanted into the semiconductor layer SC immediately below the central portion PTC of the protective film PT and the semiconductor layers SC immediately below both end portions PTS. In the second impurity implantation step, impurities are implanted into the semiconductor layer SC immediately below both end portions PTS of the protective film PT and the semiconductor layer SC exposed from the protective film PT. At this time, the impurities are implanted under a high acceleration condition (for example, 80 keV) that does not cause the impurities to be implanted into the semiconductor layer SC immediately below the central portion PTC of the protective film PT.

  That is, in the semiconductor layer SC, a region in which impurities are hardly implanted in the two impurity implantation steps becomes the channel region SCC, and almost no impurities are implanted in the first impurity implantation step, and the second impurity implantation step. Thus, the region into which the impurity has been implanted becomes the low concentration impurity region SCL, and the region into which the impurity has been implanted in the first impurity implantation step and the second impurity implantation step becomes the high concentration impurity region SCH. When forming the channel region SCC, not only the acceleration conditions for impurity implantation but also other implantation conditions such as the thickness of the protective film PT are set as appropriate.

  Thereafter, thermal annealing is performed to perform hydrogenation and activation.

  Subsequently, as shown in FIG. 6C, a resist R2 is formed on the protective film PT and the semiconductor layer SC. The resist R2 is patterned into a shape for forming a contact hole necessary for contact with the gate wiring GL and removing an unnecessary semiconductor layer SC.

  FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate 1 of the present embodiment.

  As shown in FIG. 6C, after forming the resist R2 on the protective film PT and the semiconductor layer SC, as shown in FIG. 7A, using the resist R2 as a mask, the semiconductor layer SC. Then, the gate insulating film 12 is removed by etching. As described above, the semiconductor layer SC and the gate insulating film 12 are collectively etched, so that their end faces are aligned. Thereafter, the resist R2 is removed.

  Subsequently, as shown in FIG. 7B, an electrode seed layer ESL for plating is formed on the protective film PT and the semiconductor layer SC exposed from the protective film PT. The electrode seed layer ESL is formed of, for example, a copper alloy. Such an electrode seed layer ESL is formed on the entire surface of the substrate by sputtering, and is a thin film having a thickness of about 50 nm. For this reason, the electrode seed layer ESL is formed not only on the protective film PT and the semiconductor layer SC but also on the base insulating film 11 and the gate wiring GL.

  Subsequently, as shown in FIG. 7C, a plating resist R3 exposing the electrode formation region is formed on the electrode seed layer ESL. The plating resist R3 applied at this time is formed of a resin material patterned by a photolithography process. The plating resist R3 is formed so as not to have a forward taper shape. That is, the plating resist R3 is formed in a reverse taper shape or a shape having a cross section perpendicular to the upper surface of the electrode seed layer ESL. The electrode region exposed from the plating resist R3 is a region where the source electrode WS and the drain electrode WD will be formed later. In the illustrated example, the extraction electrode BE and the capacitance forming portion CE are further formed. It also includes areas.

  FIG. 8 is a schematic cross-sectional view for explaining a manufacturing process of the thin film transistor circuit substrate 1 of the present embodiment.

  After the plating resist R3 is formed as shown in FIG. 7C, the electrode formation region is plated by electrolytic plating using the plating resist R3 as a mask as shown in FIG. A plating layer EM is formed on the electrode seed layer ESL. The plating layer EM is made of copper, for example. At this time, since the plating resist R3 has a reverse taper shape or a shape having a cross section perpendicular to the upper surface of the electrode seed layer ESL, the plating layer EM has a forward taper shape or the electrode seed layer ESL. It is formed in a shape having a cross section perpendicular to the upper surface.

  Such a plating layer EM is formed in a region where the source electrode WS and the drain electrode WD are formed. In the example shown here, the plating layer EM is also formed in the region where the extraction electrode BE and the capacitance forming portion CE are formed.

  Subsequently, as shown in FIG. 8B, the plating resist R3 is removed. As a result, the electrode seed layer ESL is exposed except for the portion directly below the plating layer EM. Then, as shown in FIG. 8C, patterning is performed using the plating layer EM as a mask, and the electrode seed layer ESL is removed. In the region where the electrode seed layer ESL is removed, the protective film PT, the semiconductor layer SC, the base insulating film 11 and the like are exposed.

  Thereby, the stacked body of the electrode seed layer ESL and the plating layer EM is separated, and the source electrode WS and the drain electrode WD are formed. In the example shown here, the extraction electrode BE and the capacitance forming portion CE are also formed at the same time. In the source electrode WS, the drain electrode WS, the extraction electrode BE, and the capacitance forming portion CE, the electrode seed layer ESL corresponds to the first conductive layer E1, and the plating layer EM corresponds to the second conductive layer E2.

  When the electrode seed layer ESL is removed by such patterning, since the electrode seed layer ESL is a thin film, the etching conversion difference (that is, the electrode seed layer ESL located immediately below the plating resist R3 before the etching) The difference between the area and the area of the electrode seed layer ESL located immediately below the plating resist R3 after etching is substantially zero.

  According to the present embodiment described above, the protective film PT functioning as an etching stopper layer is formed in a step shape, and the amount of ions implanted into the semiconductor layer SC is adjusted using the difference in film thickness of the protective film PT. The N− region and the N + region can be formed without greatly increasing the number of manufacturing steps.

  In addition, the channel length of the thin film transistor manufactured in the present embodiment is determined by the resolution of the exposure machine for forming the protective film resist R1 for forming the protective film PT. At this time, since it is possible to perform patterning at the resolution limit of the exposure machine in the process of forming the protective film resist R1, the channel length can be shortened even though the bottom gate structure is provided.

  Therefore, a high-performance thin film transistor (N-type bottom gate p-Si TFT) having a high drain breakdown voltage can be formed. In addition, since the thin film transistor can be formed in a small size, not only the performance of the thin film transistor is improved, but also the effect of improving the aperture ratio of the high-definition pixel product and reducing the frame width is obtained.

  Further, according to the present embodiment, the electrodes constituting the thin film transistor are formed by electrolytic plating. Since the plating resist R3 formed before such electrolytic plating is not formed in a forward taper shape, the plating layer EM is not formed in a reverse taper shape. Therefore, even when a protective insulating film or the like covering the thin film transistor is formed later, it is possible to prevent a problem that the insulating film is interrupted.

  Moreover, according to this embodiment, the electrode which comprises a thin-film transistor is formed of the laminated body of at least 2 layers. Among these, the first conductive layer E1 or the plating seed layer ESL that contacts the semiconductor layer SC is formed of a copper alloy containing at least magnesium (Mg) and aluminum (Al), and is stacked on the first conductive layer E1. When the conductive layer E2 or the plating layer EM is formed of copper, the first conductive layer E1 functions as a diffusion prevention layer that prevents diffusion of copper from the second conductive layer E2 to the semiconductor layer SC. For this reason, it is possible to maintain the thin film transistor with high performance.

  Next, a modification of the thin film transistor circuit substrate 1 of the present embodiment will be described.

  FIG. 9 is a cross-sectional view schematically showing a configuration of the thin film transistor circuit substrate 1 including the thin film transistor A in a modification of the present embodiment.

  The thin film transistor A of the modification shown here is different from the example shown in FIG. 2 in that the shapes of the source electrode WS and the drain electrode WD are different. That is, the source electrode WS and the drain electrode WD shown here are formed on the high concentration impurity region SCH of the semiconductor layer SC and are not in contact with the protective film PT. The thin film transistor A having such a structure can be formed only by changing the pattern of the plating resist R3 shown in FIG.

  According to such a modification, the parasitic capacitance of the thin film transistor A can be reduced as compared with the example shown in FIG.

  As described above, according to this embodiment, it is possible to provide a thin film transistor circuit substrate including a high performance thin film transistor and a method for manufacturing the thin film transistor circuit substrate without significantly increasing the number of manufacturing steps.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Thin film transistor circuit board 10 ... Insulating substrate A ... Thin film transistor WG ... Gate electrode WS ... Source electrode WD ... Drain electrode SC ... Semiconductor layer SCC ... Channel region SCL ... Low concentration impurity region SCH ... High concentration impurity region PT ... Protective film PTC ... Center part PTS ... Both ends E1 ... First conductive layer (ESL ... Electrode seed layer) E2 ... Second conductive layer (EM ... Plating layer)

Claims (10)

A gate electrode disposed on an insulating substrate;
A gate insulating film disposed on the gate electrode;
A channel region formed of polysilicon disposed on the gate insulating film and positioned immediately above the gate electrode; a low-concentration impurity region adjacent to the channel region and containing a higher concentration of impurities than the channel region; And a semiconductor layer including a high concentration impurity region adjacent to the low concentration impurity region and including a higher concentration impurity than the low concentration impurity region;
A protective film disposed on the channel region and the low-concentration impurity region, and a film thickness immediately above the channel region is greater than a film thickness directly above the low-concentration impurity region;
An electrode electrically connected to the high concentration impurity region;
A thin film transistor circuit board comprising:   The electrode includes a first conductive layer stacked on the high-concentration impurity region and the protective film, and a second conductive layer stacked on the first conductive layer and thicker than the first conductive layer. The thin film transistor circuit board according to claim 1, comprising: In the first conductive layer, the film thickness immediately above the high-concentration impurity region is substantially the same as the film thickness directly above the protective film,
3. The thin film transistor circuit substrate according to claim 2, wherein the second conductive layer has a film thickness immediately above the high-concentration impurity region larger than a film thickness immediately above the protective film. The first conductive layer is formed of a copper alloy containing at least magnesium (Mg) and aluminum (Al),
4. The thin film transistor circuit board according to claim 2, wherein the second conductive layer is made of copper (Cu). Forming a gate electrode on an insulating substrate;
A gate insulating film and a semiconductor layer made of polysilicon are sequentially formed on the gate electrode,
A step-like protective film is formed immediately above the gate electrode and on the semiconductor layer, and the film thickness of the central part is thicker than the film thickness of both ends sandwiching the central part,
Impurities are implanted into the semiconductor layer, a channel region is formed immediately below the central portion of the protective film, a low-concentration impurity region is formed immediately below both end portions of the protective film, and a region exposed from the protective film is formed. Forming a high concentration impurity region,
Forming an electrode seed layer for plating on the protective film and the semiconductor layer exposed from the protective film;
Forming a plating resist exposing the electrode formation region on the electrode seed layer,
Plating the electrode formation region by electrolytic plating using the plating resist as a mask to form a plating layer on the electrode seed layer;
Removing the plating resist;
A method of manufacturing a thin film transistor circuit board, wherein the electrode seed layer is removed using the plating layer as a mask. The gate electrode is
Forming a gate seed layer on the insulating substrate;
Forming a base insulating film exposing the gate seed layer on the insulating substrate;
6. The method of manufacturing a thin film transistor circuit board according to claim 5, wherein the thin film transistor circuit board is formed by electrolytic plating using the base insulating film as a mask. The protective film is
Forming a protective film material on the semiconductor layer;
A stepwise protective film resist is formed on the protective film material, the film thickness at the center being thicker than the film thickness at both ends sandwiching the center.
Removing the protective film material exposed from the protective film resist by dry etching;
Remove both ends of the protective film resist by ashing,
Etching the protective film material exposed from the protective film resist by dry etching to reduce the film thickness below the film thickness immediately below the protective film resist,
7. The method of manufacturing a thin film transistor circuit substrate according to claim 5, wherein the protective film resist is formed by removing the resist for the protective film.   The channel region, the low-concentration impurity region, and the high-concentration impurity region implant impurities into the semiconductor layer exposed from the protective film, and the semiconductor layer and the protective film immediately below both ends of the protective film 8. The method of manufacturing a thin film transistor circuit substrate according to claim 5, wherein an impurity is implanted into the semiconductor layer exposed from the substrate.   9. The thin film transistor circuit substrate according to claim 5, wherein the electrode seed layer is formed by sputtering using a copper alloy containing at least magnesium (Mg) and aluminum (Al). Method.   The method for manufacturing a thin film transistor circuit substrate according to claim 5, wherein the electrode is formed of copper (Cu).

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