KR960015487B1 - Self alignment wiring method - Google Patents
Self alignment wiring method Download PDFInfo
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- KR960015487B1 KR960015487B1 KR1019930013695A KR930013695A KR960015487B1 KR 960015487 B1 KR960015487 B1 KR 960015487B1 KR 1019930013695 A KR1019930013695 A KR 1019930013695A KR 930013695 A KR930013695 A KR 930013695A KR 960015487 B1 KR960015487 B1 KR 960015487B1
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- Prior art keywords
- insulating film
- forming
- film
- photoresist
- wiring
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims abstract 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000000779 smoke Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도(a)-(e)도는 종래의 콘택형성과 배선형성을 나타낸 공정단면도.1 (a)-(e) are process cross-sectional views showing conventional contact formation and wiring formation.
제2도는 본 발명에 시용된 포토-매스크 평면도.2 is a photo-mask plan view used in the present invention.
제3도(a)-(i)는 본 발명의 자기정렬 배선형성 방법을 나타낸 공정단면도.3 (a)-(i) are process cross-sectional views showing the self-aligned wiring forming method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 콘택 12 : 금속패턴11 contact 12 metal pattern
101 : 반도체 기판 102 : 게이트 전극101 semiconductor substrate 102 gate electrode
103 : 제1절연막 104 : 제1감광막103: first insulating film 104: first photosensitive film
105 : 제2절연막 106 : 제2감광막105: second insulating film 106: second photosensitive film
107 : 콘택홀 108 : 금속플럭107: contact hole 108: metal floc
109 : 배선109: wiring
본 발명은 장기 정렬(self-Align)배선에 관한 것으로, 특히 콘택과 배선의 정렬 마진 확보에 적당하도록 한 자기정렬 배선형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to long-aligned wiring, and more particularly, to a method of forming self-aligned wiring, which is suitable for securing alignment margins of contacts and wiring.
제1도(A)-(E)는 종래의 콘택과 배선의 형성방법을 설명하기 위한 공정단면도로써, 이로부터 종래기술의 콘택(소오스 전극)과 배선(비트라인)의 형성방법을 설명하면 다음과 같다.1 (A)-(E) are process cross-sectional views for explaining a conventional method for forming a contact and a wiring. From this, the method of forming a contact (source electrode) and a wiring (bit line) of the prior art will be described below. Same as
먼저 제1도(a)와 같이 반도체 기판(1)상의 활성영역에 트랜지스터를 제조하기 위해 공정을 차례로 수행하여 게이트 전극(2)을 형성한후, 제1도(b)와 같이 노출된 전표면에 절연막(SiO2, SiNx)(3)을 형성하고 양쪽 게이트 전극(2) 사이에 콘택을 형성하기 위해, 전표면에 콘택마스킹용 포토레지스트(4)를 형성한다음, 양게이트 전극(2)사이의 일정폭의 포토레지스트(4)가 제거되도록 패터닝한다.First, as shown in FIG. 1 (a), the gate electrode 2 is formed by sequentially performing a process in order to manufacture a transistor in an active region on the semiconductor substrate 1, and then expose the entire surface as shown in FIG. 1 (b). In order to form an insulating film (SiO 2 , SiNx) 3 on the surface and to form a contact between both gate electrodes 2, a contact masking photoresist 4 is formed on the entire surface, and then the positive gate electrode 2 is formed. The photoresist 4 of a certain width in between is patterned so as to be removed.
이어, 제1도(c)와 같이 노출부분의 절연막(3)을 제거하여 콘택홀을 형성한후, 노출된 전표면에 콘택형성용 금속으로서 텅스텐(5)을 형성하고, 콘택홀내부에 플럭(PLUG)을 형성하기 위한 에치백공정을 수행하여 제1도(d)와 같이 텅스텐 플랙(5a)을 형성한다.Subsequently, as shown in FIG. 1C, the insulating layer 3 of the exposed portion is removed to form a contact hole, and then tungsten 5 is formed on the exposed entire surface as a metal for forming a contact, and a floc is formed in the contact hole. An etch back process for forming PLUG is performed to form the tungsten flag 5a as shown in FIG.
그다음, 전표면에 TiN/Al/TiN을 차례로 증착하여 배선용 금속층(6)을 형성한후, 배선을 패터닝하기 위한 배선패터닝용 마스크로 포토레지스트를 금속층(6)상에 형성하고 텅스텐 플럭(5a)의 상측 영역에 일정폭을 갖는 포토레지스트 패턴(7)을 형성한다.Then, TiN / Al / TiN is deposited on the entire surface in order to form the wiring metal layer 6, and then a photoresist is formed on the metal layer 6 with a wiring patterning mask for patterning the wiring and the tungsten floc 5a. The photoresist pattern 7 having a predetermined width is formed in the upper region of the substrate.
이어, 제1도(e)와 같이 포토레지스트 패턴(7)으로 마스킹 되지 않은 부분의 금속층(6)을 제거한후, 포토레지스트 패턴(7)을 제거하여 금속배선(6a)을 형성한다.Subsequently, as shown in FIG. 1E, the metal layer 6 of the portion not masked with the photoresist pattern 7 is removed, and then the photoresist pattern 7 is removed to form the metal wiring 6a.
상기와 같이 종래 기술은 콘택마스크용 포토레지스트의 두께가 두껍게 형성되고 미세 패턴형성에 어려움이 있고, 금속배선을 형성하기 위한 포토레지스트 노광공정시 포토-매스크의 정렬에 어려움이 있고, 또한 포토레지스트의 두께 때문에 미세패턴을 형성하는데 단점이 있다.As described above, the prior art has a thick thickness of the photoresist for contact mask, difficulty in forming a fine pattern, difficulty in alignment of the photo-mask during the photoresist exposure process for forming metal wiring, and Because of the thickness, there is a disadvantage in forming a fine pattern.
본 발명은 이와같은 종래 기술의 문제점을 해결하기 위해 안출된 것으로, 콘택과 배선의 자기정렬과 배선의 미세 패턴형성을 가능함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to enable self-alignment of contacts and wiring and fine pattern formation of wiring.
이와 같은 목적을 실현하기 위한 본 발명의 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.An embodiment of the present invention for realizing such an object will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 적용된 제1감광막 패턴용 포트-매스크의 평면도를 나타낸 것으로, 투광성 유리기판(11)상에 투과하는 광을 차단하기 위한 복수개의 금속패턴(Cr)(12)이 상호 격리되어 일정간격을 유지하고 일측방향으로 형성되어 있다.2 is a plan view of a port-mask for a first photoresist pattern applied to the present invention, wherein a plurality of metal patterns (Cr) 12 for blocking light transmitted on the transparent glass substrate 11 are isolated from each other. Maintain a constant interval and is formed in one direction.
그리고, 금속패턴(12)은 좁은 폭을 갖는 라인 사이에 중앙이 사각형으로 패턴된 넓은 폭을 갖는 부분이 일정간격으로 형성하고 넓은 폭을 갖는 패턴부분은 양측에 형성된 패턴의 좁은폭 사이에 형성되어 있다.In addition, the metal pattern 12 is formed between the lines having a narrow width with a wide width portion having a central pattern at a constant interval and the pattern portion having a wide width is formed between the narrow width of the pattern formed on both sides have.
따라서, 이와같은 포토마스크를 이용하여 포토레지스트 패턴을 형성하면 일방향으로 진행중 굴곡부분을 갖는 패턴이 형성되고, 이 패턴의 간격이 좁아지는 부분 양측에 일정간격으로 사각형의 패턴이 형성된다.Therefore, when the photoresist pattern is formed using such a photomask, a pattern having a curved portion in progress in one direction is formed, and a square pattern is formed on both sides of the portion where the interval of the pattern is narrowed at regular intervals.
제3도는 (a)-(i)는 본 발명의 실시예를 설명하기 위한 콘택형성 공정단면도를 나타낸 것으로, 이로부터 본 기술을 설명하면 다음과 같다.Figure 3 (a)-(i) is a cross-sectional view of the process for forming a contact for explaining an embodiment of the present invention, when the present technology will be described as follows.
제3도(a)와 같이 반도체 기판(101)에 활성영역과 필드영역을 정의하고 반도체 소자를 제작하기 위한 표준공정을 차례로 실시하여 활성영역에 측벽산화막을 갖는 게이트 전극(102)을 형성한다.As shown in FIG. 3A, a gate electrode 102 having a sidewall oxide film is formed in the active region by sequentially defining an active region and a field region in the semiconductor substrate 101 and performing a standard process for fabricating a semiconductor device.
이어, 제3도(b)와 같이 전표면에 게이트 전극(102)를 절연시키기 위해 제1절연막(LTO, BPSG, SiNx)(103)을 형성한후 제3도(c)와 같이 제1절연막(103)상에 콘택형성용 패턴을 형성하기 위해 제1감광막(104)을 형성하고, 제2도의 콘택형성용 포토마스크를 사용하여 일정폭을 갖는 복수개의 제1감광막 패턴을 선택된 영역에 형성하고 감광막 건조오븐을 사용하여 패턴된 제1감광막(104)을 150°∼200℃의 온도로 경화한다.Subsequently, a first insulating layer LTO, BPSG, SiNx 103 is formed to insulate the gate electrode 102 from the entire surface as shown in FIG. 3B, and then the first insulating layer as shown in FIG. The first photoresist film 104 is formed on the 103 to form a contact formation pattern, and a plurality of first photoresist film patterns having a predetermined width are formed in a selected region by using the contact formation photomask of FIG. The patterned first photosensitive film 104 is cured to a temperature of 150 ° to 200 ° C using a photosensitive film drying oven.
이어 제3도(d)와 같이 노출된 전표면에 PECVD(Plasma Enhenced CVD) 장치를 이용하여 산화막과 BPSG(Boron Phosperus Silica Glass)로 제2절연막(105)을 형성한 후, 에치-백(Etch-back)하여 제1감광막(104)사이에만 제2절연막(105)이 남도록 한다. 이어 제3도(e)와 같이 전표면에 제2감광막(106)을 형성한 후, 콘택형성용 포토-마스크를 이용하여 양쪽 게이트 전극(102) 사이의 위에 위치하는 제2절연막(105)상측의 제2감광막(106)을 제2절연막(105)의 폭보다 넓게 제거한 다음, 노출된 부분의 제1, 2절연막(103, 105)을 제거하여 콘택홀(107)을 형성하고, 제3도(f)와 같이 제1, 2감광막(104, 106)을 제거한다.Subsequently, the second insulating layer 105 is formed of an oxide film and BPSG (Boron Phosperus Silica Glass) using PECVD (Plasma Enhenced CVD) on the exposed entire surface as shown in FIG. back-side) so that the second insulating film 105 remains only between the first photoresist film 104. Subsequently, as shown in FIG. 3E, the second photoresist layer 106 is formed on the entire surface, and then the upper side of the second insulating layer 105 is positioned between the gate electrodes 102 by using a contact forming photomask. The second photoresist layer 106 is formed to be wider than the width of the second insulation layer 105, and then the first and second insulation layers 103 and 105 of the exposed portion are removed to form the contact hole 107. As shown in (f), the first and second photosensitive films 104 and 106 are removed.
이어, 제3도(g)와 같이 게이트 전극(102)사이에 콘택을 형성하기 위해 노출된 전표면 W(텅스텐), Mo(몰리브덴), Ta(탄탈), Ti(티타늄), Co(코발트), Pt(백금) 등을 형성한후, 에치-백하여 감광막 전극사이에 금속플럭(108)을 형성한다.Next, as shown in FIG. 3 (g), the entire surface W (tungsten), Mo (molybdenum), Ta (tantalum), Ti (titanium), Co (cobalt) exposed to form a contact between the gate electrodes 102 is formed. , Pt (platinum) and the like are formed and then etched back to form a metal floc 108 between the photoresist electrodes.
그다음, 제3도(h)와 같이 콘택층(108)상측에 배선을 형성하기 위해 금속(TiN/Al)을 형성한후, 에치-백하고, 잔존하는 제2절연막(105)을 제거하여 제3도(i)와 같이 금속배선(109)을 형성한다.Next, as shown in FIG. 3 (h), metal (TiN / Al) is formed to form wiring on the contact layer 108, and then etched back to remove the remaining second insulating film 105. As shown in FIG. 3 (i), the metal wiring 109 is formed.
상기와 같은 본 기술은 제1감광막을 얇게 형성시켜 해상도를 높일 수 있음으로 미세 패턴이 가능하고, 콘택택매스크의 레티클(Racticle)이 일치하므로 자기정렬이 가능하여 오정렬에 따른 비정합의 문제점을 해결할 수 있어 0.5㎛급 이상의 반도체 공정에 적용이 가능하다.The present technology as described above can increase the resolution by forming the first photoresist film thinly, so that fine patterns are possible. Since the reticle of the contact mask is matched, self-alignment is possible, thereby solving the problem of misalignment due to misalignment. It can be applied to the semiconductor process of 0.5 ㎛ or more.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013695A KR960015487B1 (en) | 1993-07-20 | 1993-07-20 | Self alignment wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013695A KR960015487B1 (en) | 1993-07-20 | 1993-07-20 | Self alignment wiring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950004411A KR950004411A (en) | 1995-02-18 |
| KR960015487B1 true KR960015487B1 (en) | 1996-11-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930013695A KR960015487B1 (en) | 1993-07-20 | 1993-07-20 | Self alignment wiring method |
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| Country | Link |
|---|---|
| KR (1) | KR960015487B1 (en) |
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1993
- 1993-07-20 KR KR1019930013695A patent/KR960015487B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR950004411A (en) | 1995-02-18 |
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