KR0172901B1 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistor Download PDFInfo
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- KR0172901B1 KR0172901B1 KR1019950067259A KR19950067259A KR0172901B1 KR 0172901 B1 KR0172901 B1 KR 0172901B1 KR 1019950067259 A KR1019950067259 A KR 1019950067259A KR 19950067259 A KR19950067259 A KR 19950067259A KR 0172901 B1 KR0172901 B1 KR 0172901B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000005530 etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막 트랜지스터 제조방법에 관한 것이로, 게이트 절연막의 파괴(Break-down)전압을 향상시키는데 적합하도록 한 박막 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor adapted to improve the breakdown voltage of a gate insulating film.
이를 위한 본 발명의 박막 트랜지스터 제조방법은 기판위에 활성층을 형성하는 단계, 상기 활성층의 소정영역에 감광막을 패터닝하는 단계, 상기 감광막을 마스크로 하여 상기 기판이 노출되지 않도록 상기 활성층의 일부를 제거하여 섬모양의 활성층을 형성하는 단계, 상기 섬모양의 활성층을 포함한 기판 전면에 게이트 절연막을 형성하는 단계, 상기 섬모양 활성층을 포함한 게이트 절연막 위에 게이트 전극을 형성하는 단계, 상기 섬모양의 활성층 전극 양측에 소오스/드레인 영역을 형성하는 단계, 상기 게이트 전극을 포함한 기판 전면에 층간 절연막을 형성하는 단계, 상기 제 층간 절연막 및 게이트 절연막을 선택적으로 제거하여 소오스/드레인 영역이 노출되도록 콘택홀을 형성하는 단계, 상기 콘택홀내에 소오스/드레인 전극을 형성하는 단계를 포함하여 이루어진다.In the method of manufacturing a thin film transistor of the present invention, forming an active layer on a substrate, patterning a photoresist film on a predetermined region of the active layer, and removing a portion of the active layer so that the substrate is not exposed using the photoresist as a mask. Forming an active layer having a shape, forming a gate insulating film on the entire surface of the substrate including the island-like active layer, forming a gate electrode on the gate insulating film including the island-like active layer, and source on both sides of the island-like active layer electrode / Forming a drain region, forming an interlayer insulating film over the substrate including the gate electrode, selectively removing the first interlayer insulating film and the gate insulating film to form a contact hole to expose the source / drain region, the Forming a source / drain electrode in the contact hole It comprise.
따라서, 게이트 절연막의 파괴전압을 향상시켜 디바이스 특성이 우수한 박막 트랜지스터를 제작할 수 있다.Therefore, the breakdown voltage of the gate insulating film can be improved to fabricate a thin film transistor having excellent device characteristics.
Description
제1도는 종래의 박막 트랜지스터 제조공정 단면도.1 is a cross-sectional view of a conventional thin film transistor manufacturing process.
제2도는 본 발명의 박막 트랜지스터 제조공정 단면도.2 is a cross-sectional view of the manufacturing process of the thin film transistor of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 다결정 실리콘1 substrate 2 polycrystalline silicon
3 : 게이트 절연막 4 : 게이트 전극3: gate insulating film 4: gate electrode
5 : 층간 절연막 6 : 콘택홀5 interlayer insulating film 6 contact hole
7 : 메탈 8 : 감광막7: metal 8: photosensitive film
본 발명은 박막 트랜지스터 제조방법에 관한 것으로, 게이트 절연막의 파괴(Break-down)전압을 향상시키는데 적합하도록 한 박막 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor adapted to improve the breakdown voltage of a gate insulating film.
이하, 첨부된 도면을 참조하여 종래의 박막 트랜지스터 제조방법을 설명하면 다음과 같다.Hereinafter, a conventional thin film transistor manufacturing method will be described with reference to the accompanying drawings.
제1도는 종래의 박막 트랜지스터 제조공정 단면도이다.1 is a cross-sectional view of a conventional thin film transistor manufacturing process.
제1도 (a)와 같이, 유리와 같은 절연성 기판(1)위에 다결정 실리콘(2)을 형성하고 사진석판술 및 식각공정으로 상기 다결정 실리콘(2)을 선택적으로 제거하여 섬(Island) 모양으로 패터닝한다.As shown in FIG. 1 (a), polycrystalline silicon 2 is formed on an insulating substrate 1 such as glass, and the polycrystalline silicon 2 is selectively removed by photolithography and etching to form islands. Pattern.
제1도 (b)와 같이, 열산화공정으로 상기 다결정 실리콘(2) 전면에 게이트 절연막(3)을 형성하고, 상기 게이트 절연막(3)을 포함한 기판(1) 전면에 게이트 전극(4) 물질을 형성한다.As shown in FIG. 1B, a gate insulating film 3 is formed on the entire surface of the polycrystalline silicon 2 by a thermal oxidation process, and a gate electrode 4 material is formed on the entire surface of the substrate 1 including the gate insulating film 3. To form.
이때, 상기 다결정 실리콘(2)의 가장자리 부분(A)에 있는 상기 게이트 절연막(3)은 두께가 얇게 형성된다.At this time, the gate insulating film 3 at the edge portion A of the polycrystalline silicon 2 is thinly formed.
제1도 (c)와 같이, 사진석판술 및 식각공정으로 상기 게이트 전극(4) 물질을 선택적으로 제거하여 상기 게이트 전극(4)을 패터닝하고, 상기 게이트 전극(4)을 마스크로하여 기판(1) 전면에 불순물을 이온주입하고 열처리공정으로 주입된 이온을 활성화시켜 상기 게이트 전극(4) 양측에 소오스/드레인 영역을 형성한다.As shown in FIG. 1 (c), the gate electrode 4 is patterned by selectively removing the material of the gate electrode 4 by photolithography and etching processes, and the substrate is formed using the gate electrode 4 as a mask. 1) An ion is implanted into the entire surface of the impurity and the ion implanted in the heat treatment process is activated to form source / drain regions on both sides of the gate electrode 4.
제1도 (d)와 같이, 상기 게이트 전극(4)을 포함한 기판(1) 전면에 층간 절연막(5)을 형성하고 사진석판술 및 식각공정으로 상기 층간 절연막(5) 및 게이트 절연막(3)을 선택적으로 제거하여 상기 소오스/드레인 영역이 노출되도록 콘택홀(6)을 형성한다.As shown in FIG. 1D, an interlayer insulating film 5 is formed on the entire surface of the substrate 1 including the gate electrode 4, and the interlayer insulating film 5 and the gate insulating film 3 are formed by photolithography and etching. Is selectively removed to form contact holes 6 to expose the source / drain regions.
제1도 (e)와 같이, 상기 소오스/드레인 영역과 전기적으로 연결되도록 상기 콘택홀(6)내 및 상기 층간 절연막(5) 일부분에 메탈(7)을 형성한다.As shown in FIG. 1E, a metal 7 is formed in the contact hole 6 and a part of the interlayer insulating layer 5 so as to be electrically connected to the source / drain region.
그러나 이와 같은 종래의 박막 트랜지스터 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, such a conventional thin film transistor manufacturing method has the following problems.
상기 제1도 (b)에 도시된 바와 같이, 열산화공정으로 게이트 절연막을 형성할 경우 A부분의 게이트 절연막의 두께가 얇게 형성되므로 디바이스(Device)의 게이트 절연막의 파괴전압 특성이 크게 저하된다.As shown in FIG. 1B, when the gate insulating film is formed by the thermal oxidation process, the thickness of the gate insulating film of the A portion is formed to be thin, which greatly reduces the breakdown voltage characteristic of the gate insulating film of the device.
즉, 디바이스 제작후, 게이트 절연막의 파괴전압이 가장자리 부분(A)의 절연막 특성에 좌우되기 때문에 A부분의 절연막 두께가 얇아지면 파괴전압 특성이 저하된다.That is, after fabrication of the device, the breakdown voltage of the gate insulating film depends on the insulating film characteristics of the edge portion A, so that the breakdown voltage characteristics of the A portion become thinner.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써, 게이트 절연막의 두께를 일정하게 형성하여 게이트 절연막의 파괴전압을 향상시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has an object of improving the breakdown voltage of the gate insulating film by forming a constant thickness of the gate insulating film.
이와 같은 목적을 달성하기 위한 본 발명의 박막 트랜지스터의 제조방법은 기판위에 활성층을 형성하는 단계, 상기 활성층의 소정영역에 감광막을 패터닝하는 단계, 상기 감광막을 마스크로 하여 상기 기판이 노출되지 않도록 상기 활성층의 일부를 제거하여 섬모양 활성층을 형성하는 단계, 상기 섬모양의 활성층을 포함한 기판 전면에 게이트 절연막을 형성하는 단계, 상기 섬모양 활성층을 포함한 게이트 절연막위에 게이트 전극을 형성하는 단계, 상기 게이트 전극 양측에 소오스/드레인 영역을 형성하는 단계, 상기 게이트 전극을 포함한 기판 전면에 층간 절연막을 형성하는 단계, 상기 층간 절연막 및 게이트 절연막을 선택적으로 제거하여 소오스/드레인 영역이 노출되도록 콘택홀을 형성하는 단계, 상기 콘택홀내에 소오스/드레인 전극을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a thin film transistor of the present invention for achieving the above object comprises the steps of forming an active layer on a substrate, patterning a photosensitive film in a predetermined region of the active layer, the active layer so that the substrate is not exposed using the photosensitive film as a mask Forming a island active layer by removing a portion of the island, forming a gate insulating film on the entire surface of the substrate including the island active layer, forming a gate electrode on the gate insulating film including the island active layer, and both sides of the gate electrode. Forming a source / drain region on the substrate, forming an interlayer insulating layer on the entire surface of the substrate including the gate electrode, selectively removing the interlayer insulating layer and the gate insulating layer to form a contact hole to expose the source / drain region, Source / drain electrodes are formed in the contact holes. It is characterized by the yirueojim including the steps:
상기와 같은 본 발명의 박막 트랜지스터의 제조방법은 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The manufacturing method of the thin film transistor of the present invention as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명의 박막 트랜지스터 제조공정 단면도이다.2 is a cross-sectional view of the manufacturing process of the thin film transistor of the present invention.
제2도 (a)와 같이, 유리와 같은 절연성 기판(1)위에 활성층인 다결정 실리콘(2)을 형성하고, 상기 다결정 실리콘(2)의 소정영역에 감광막(8)을 패터닝한다.As shown in FIG. 2A, a polycrystalline silicon 2 as an active layer is formed on an insulating substrate 1 such as glass, and the photosensitive film 8 is patterned in a predetermined region of the polycrystalline silicon 2.
제2도 (b)와 같이, 상기 패터닝된 감광막(8)을 마스크로 하여 상기 기판(1)이 노출되지 않도록 상기 다결정 실리콘(2)의 일부를 제거하여 섬(Island)모양의 다결정 실리콘(2)을 형성한다.As shown in FIG. 2B, a portion of the polycrystalline silicon 2 is removed so that the substrate 1 is not exposed by using the patterned photoresist 8 as a mask, and island-like polycrystalline silicon 2 is removed. ).
이때, 다결정 실리콘(2)은 패터닝된 감광막(8)이 도포된 부분을 제외한 나머지 부분을 완전히 제거하지 않고 상기 기판(1)위에 일부분이 남아 있게 된다.At this time, a portion of the polycrystalline silicon 2 remains on the substrate 1 without completely removing the remaining portions except for the portion where the patterned photoresist 8 is applied.
제2도 (c)와 같이, 상기 감광막(8)을 제거하고 상기 다결정 실리콘(2)을 포함한 기판 전면에 게이트 절연막(3)을 형성한다.As shown in FIG. 2C, the photoresist film 8 is removed to form a gate insulating film 3 on the entire surface of the substrate including the polycrystalline silicon 2.
이때, 게이트 절연막(3)은 열산화공정으로 상기 다결정 실리콘(2)의 일부분을 산화시켜 형성된다.In this case, the gate insulating film 3 is formed by oxidizing a part of the polycrystalline silicon 2 by a thermal oxidation process.
제2도 (d)와 같이, 상기 게이트 절연막(3)위에 게이트 전극물질을 증착하고 사진석판술 및 식각공정으로 상기 게이트 전극물질을 선택적으로 제거하여 게이트 전극(4)을 형성한다.As shown in FIG. 2 (d), a gate electrode material is deposited on the gate insulating film 3, and the gate electrode material is selectively removed by photolithography and etching to form the gate electrode 4.
그리고, 상기 게이트 전극(4)을 마스크로 하여 기판(1) 전면에 불순물 이온을 주입하고 열처리 공정으로 주입된 이온을 활성화 시켜 게이트 전극(4) 양측에 소오스/드레인 영역을 형성한다.The impurity ions are implanted into the entire surface of the substrate 1 using the gate electrode 4 as a mask, and the ions implanted by the heat treatment process are activated to form source / drain regions on both sides of the gate electrode 4.
제2도 (e)와 같이, 상기 게이트 전극(4)을 포함한 기판(1) 전면에 층간 절연막(5)을 형성하고 사진석판술 및 식각공정으로 상기 층간 절연막(5) 및 게이트 절연막(3)을 선택적으로 제거하여 상기 소오스/드레인 영역이 노출되도록 콘택홀(6)을 형성한다.As shown in FIG. 2E, an interlayer insulating film 5 is formed on the entire surface of the substrate 1 including the gate electrode 4, and the interlayer insulating film 5 and the gate insulating film 3 are formed by photolithography and etching. Is selectively removed to form contact holes 6 to expose the source / drain regions.
제2도 (f)와 같이, 상기 소오스/드레인 영역과 전기적으로 연결되도록 상기 콘택홀(6)내 및 상기 층간 절연막(5) 일부분에 메탈(7)을 형성한다.As shown in FIG. 2F, a metal 7 is formed in the contact hole 6 and a part of the interlayer insulating layer 5 so as to be electrically connected to the source / drain region.
이상에서 설명한 바와 같이, 본 발명의 박막 트랜지스터의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the thin film transistor of the present invention has the following effects.
게이트 절연막의 두께를 일정하게 형성함으로써 게이트 절연막의 파괴전압 특성을 크게 향상시킬 수 있으므로 디바이스 특성이 우수한 박막 트랜지스터를 제작할 수 있고 신뢰성이 높은 액정표시 판넬(Panel)의 제작이 가능하다.Since the breakdown voltage characteristic of the gate insulating film can be greatly improved by forming the thickness of the gate insulating film uniformly, a thin film transistor having excellent device characteristics can be manufactured and a highly reliable liquid crystal display panel can be manufactured.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067259A KR0172901B1 (en) | 1995-12-29 | 1995-12-29 | Method of manufacturing thin film transistor |
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| KR1019950067259A KR0172901B1 (en) | 1995-12-29 | 1995-12-29 | Method of manufacturing thin film transistor |
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| KR0172901B1 true KR0172901B1 (en) | 1999-02-01 |
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| US6667494B1 (en) * | 1997-08-19 | 2003-12-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and semiconductor display device |
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