KR100223917B1 - The structure of a mos transistor - Google Patents
The structure of a mos transistor Download PDFInfo
- Publication number
- KR100223917B1 KR100223917B1 KR1019960026099A KR19960026099A KR100223917B1 KR 100223917 B1 KR100223917 B1 KR 100223917B1 KR 1019960026099 A KR1019960026099 A KR 1019960026099A KR 19960026099 A KR19960026099 A KR 19960026099A KR 100223917 B1 KR100223917 B1 KR 100223917B1
- Authority
- KR
- South Korea
- Prior art keywords
- mos transistor
- gate electrode
- semiconductor substrate
- gate
- present
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 MOS 트랜지스터에 관한 것으로 커브 모양의 게이트 구조를 갖도록 함으로써 좁은 면적에서도 게이트의 유효폭을 크게하여 MOS 트랜지스터의 구동능력을 그만큼 크게 한 MOS 트랜지스터의 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a structure of a MOS transistor having a curved gate structure which increases the effective width of the gate even in a small area, thereby increasing the driving capability of the MOS transistor.
이와같은 본 발명의 MOS 트랜지스터의 구조는 반도체 기판과 상기 반도체 기판 위에 커브 모양으로 형성되는 게이트 전극과, 그리고 상기 게이트 전극 양측의 반도체 기판에 형성되는 소오스/드레인 영역을 포함하여 구성된 것이다.The structure of the MOS transistor of the present invention includes a semiconductor substrate, a gate electrode formed in a curved shape on the semiconductor substrate, and a source / drain region formed in the semiconductor substrate on both sides of the gate electrode.
Description
제 1 도는 일반적인 MOS트랜지스터의 공정단면도1 is a process sectional view of a typical MOS transistor
제 2 도는 종래의 MOS트랜지스터의 구조 단면도2 is a structural cross-sectional view of a conventional MOS transistor.
제 3 도는 본 발명의 MOS트랜지스터의 구조 평면도3 is a structural plan view of the MOS transistor of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 소오스 20 : 게이트10: source 20: gate
30 : 드레인30: drain
본 발명은 MOS(Metal Oxide Semiconductor) 트랜지스터에 관한 것으로, 특히 힐버트(Hilbert)커브 모양의 게이트를 갖도록 한 MOS 트랜지스터의 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal oxide semiconductor (MOS) transistors, and more particularly, to a structure of a MOS transistor having a Hilbert curve gate.
이하, 첨부된 도면을 참조하여 일반적인 MOS 트랜지스터의 제작공정을 설명하면 다음과 같다,Hereinafter, a manufacturing process of a general MOS transistor will be described with reference to the accompanying drawings.
먼저, 제1도(a)-(d)는 일반적인 MOS트랜지스터의 공정단면도이다.First, (a)-(d) is a process sectional view of a general MOS transistor.
제1도 (a)에서와 같이 반도체 기판(1)위에 제1게이트 절연막(2) 및 폴리 실리콘(3)을 차례로 형성한다.As shown in FIG. 1A, the first gate insulating film 2 and the polysilicon 3 are sequentially formed on the semiconductor substrate 1.
다음, 상기 형성된 표면에 화학기상증착(CVD) 또는 스퍼터(Sputter)장비를 이용하여 실리사이드막(Silicide)(4)를 형성하고 감광막(Photo Resist)(5)을 차례로 형성한후, 차후 공정에서 형성하고자 하는 게이트 영역의 표면에 감광막(5)를 선택적으로 패터닝(Patterning)한다.Next, a silicide film 4 is formed on the formed surface by using chemical vapor deposition (CVD) or a sputtering device, and a photoresist film 5 is sequentially formed, and then formed in a subsequent process. The photosensitive film 5 is selectively patterned on the surface of the gate region to be made.
이어서, 제1도(b)에서와 같이 상기 패터닝된 감광막(5)를 마스크로 이용하여 이방성 식각공정으로 실리사이드막(4), 폴리 실리콘막(3)을 선택적으로 제거하여 게이트 전극(6)을 형성한다.Subsequently, the silicide layer 4 and the polysilicon layer 3 are selectively removed by anisotropic etching using the patterned photosensitive layer 5 as a mask, as shown in FIG. Form.
상기 게이트 전극(6)을 마스크로 이용하여 게이트 전극(6) 양측의 반도체 기판(1)에 저농도 불순물 이온을 주입하여 저농도 소오스/드레인 영역(7)을 형성한다.Using the gate electrode 6 as a mask, low concentration impurity ions are implanted into the semiconductor substrate 1 on both sides of the gate electrode 6 to form a low concentration source / drain region 7.
이어서, 제1도(c)에서와 같이 게이트 전극(6)을 포함한 반도체 기판(1)전면에 제2절연막(3)을 형성한다.Next, as shown in FIG. 1C, a second insulating film 3 is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 6.
이어, 제1도(d)에서와 같이 상기 제2절연막(3)을 에치 백(etch back)하여 게이트 전극(6) 측면에 절연막 측벽(9)을 형성한다.Next, as shown in FIG. 1D, the second insulating layer 3 is etched back to form an insulating film sidewall 9 on the side of the gate electrode 6.
그리고 상기 게이트 전극(6) 및 절연막 측벽(9)을 마스크로 이용하여 게이트 전극(6) 양측의 반도체 기판(1)에 고농도 불순물 이온을 주입하므로써 LDD구조를 갖는 소오스/드레인 불순물 확산영역(10)을 형성한다.The source / drain impurity diffusion region 10 having the LDD structure is formed by implanting high concentration impurity ions into the semiconductor substrate 1 on both sides of the gate electrode 6 using the gate electrode 6 and the insulating film sidewall 9 as a mask. To form.
이하, 첨부된 도면을 참조하여 종래의 MOS트랜지스터의 구조를 설명하면 다음과 같다.Hereinafter, a structure of a conventional MOS transistor will be described with reference to the accompanying drawings.
첨부된 도면 제2도는 종래의 MOS트랜지스터의 구조단면도이고, 제2도에서와 같이 반도체 기판(1)의 소정부분에 게이트 절연막(2)이 형성되고, 상기 게이트 절연막 위에 평면 모양을 갖는 게이트 전극(4)과 그리고 상기 게이트 전극(4) 양측의 반도체 기판(1)에 소오스(3)와 드레인(5)영역을 갖는 구조이다.2 is a structural cross-sectional view of a conventional MOS transistor, and as shown in FIG. 2, a gate insulating film 2 is formed on a predetermined portion of the semiconductor substrate 1, and a gate electrode having a planar shape on the gate insulating film is formed. 4) and a source 3 and a drain 5 region in the semiconductor substrate 1 on both sides of the gate electrode 4.
일반적으로 MOS 트랜지스터의 구동능력은 게이트의 폭에 비례하므로 큰 구동능력을 갖기 위해서는 그 만큼 게이트의 폭이 넓어야 한다.In general, since the driving capability of the MOS transistor is proportional to the width of the gate, the gate width of the MOS transistor needs to be wide enough to have a large driving capability.
그러나 종래의 MOS트랜지스터의 구조는 구동능력을 크게 할 경우 게이트 전극이 평판 모양이므로 트랜지스터를 다수개 형성할 필요가 있을때 면적의 제약을 받는 문제점이 있었다.However, the conventional MOS transistor structure has a problem of being limited in area when it is necessary to form a plurality of transistors because the gate electrode has a flat plate shape when the driving capability is increased.
본 발명은 이러한 문제점을 해결하기위해 안출한 것으로, 좁은 면적에서도 게이트의 유효폭을 크게하여 MOS트랜지스터의 구동 능력을 향상시키는데 그 목적이 있다.The present invention has been made to solve such a problem, and its object is to improve the driving capability of the MOS transistor by increasing the effective width of the gate even in a small area.
이와 같은 목적을 달성하기 위한 본 발명의 MOS트랜지스터의 구조는 반도체 기판 ; 상기 반도체 기판 위에 커브 모양으로 형성되는 게이트 전극 ; 그리고 상기 게이트 전극 양측의 반도체 기판에 형성되는 소오스/드레인 영역으로 구성됨에 그 특징이 있다.The structure of the MOS transistor of the present invention for achieving the above object is a semiconductor substrate; A gate electrode formed in a curved shape on the semiconductor substrate; And it is characterized in that it consists of a source / drain region formed in the semiconductor substrate on both sides of the gate electrode.
이하, 첨부된 도면을 참조하여 본 발명의 MOS 트랜지스터의 구조를 설명하면 다음과 같다.Hereinafter, the structure of the MOS transistor of the present invention will be described with reference to the accompanying drawings.
제3도는 본 발명의 MOS 트랜지스터의 구조 평면도이다.3 is a structural plan view of the MOS transistor of the present invention.
제3도와 같이 본 발명의 MOS 트랜지스터의 구조는 반도체 기판(도면에 도시하지 않음) 위에 힐버트 커브 모양을 갖는 게이트 전극(20) 이 형성된다.As shown in FIG. 3, in the structure of the MOS transistor of the present invention, a gate electrode 20 having a Hilbert curve shape is formed on a semiconductor substrate (not shown).
여기서, 도면에는 도시되지 않았지만 게이트 전극(20)과 기판 사이에는 게이트 절연막이 형성된다.Although not shown in the drawing, a gate insulating film is formed between the gate electrode 20 and the substrate.
그리고 상기 힐버트 커브 모양의 게이트 전극(20) 양측의 반도체 기판에는 소오스(10)와 드레인(30) 영역이 형성된다.The source 10 and the drain 30 regions are formed on the semiconductor substrates on both sides of the Hilbert curve-shaped gate electrode 20.
이와같은 구조를 갖는 본 발명의 MOS 트랜지스터의 제조방법은 활성영역과 필드영역이 정의된 기판상에 게이트 절연막과 폴리실리콘 등의 도전체 및 감광막을 차례로 증착한 다음, 힐러트 커브 모양을 갖는 게이트 전극 패턴용 마스크를 이용하여 노광 및 현상공정으로 감광막을 패터닝 한다.In the method of manufacturing the MOS transistor of the present invention having such a structure, a gate insulating film, a conductor such as polysilicon, and a photoresist film are sequentially deposited on a substrate having an active region and a field region defined therein, and then a gate electrode having a hillet curve shape. The photosensitive film is patterned by exposure and development processes using a pattern mask.
그리고 패터닝된 감광막을 마스크로 이용하여 상기 도전체 및 게이트 절연막을 선택적으로 제거하여 힐버트 커브 모양의 게이트 전극(20)을 형성한다.The conductor and the gate insulating layer are selectively removed using the patterned photoresist as a mask to form a Hilbert curve-shaped gate electrode 20.
계속해서 상기 게이트 전극(20)을 마스크로 이용하여 기판에 불순물 이온주입으로 소오스/드레인 영역(10,30)을 형성한다.Subsequently, source / drain regions 10 and 30 are formed by implanting impurity ions into the substrate using the gate electrode 20 as a mask.
이상 설명한 바와 같이 본 발명의 MOS 트랜지스터의 구조는 커브 모양의 게이트 전극 구조를 갖으므로 좁은 면적에서도 게이트의 유효폭을 크게 할 수 있기 때문에 MOS 트랜지스터의 구동능력을 그 만큼 크게 할 수 있는 효과가 있다.As described above, since the structure of the MOS transistor of the present invention has a curved gate electrode structure, the effective width of the gate can be increased even in a small area, thereby increasing the driving capability of the MOS transistor.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960026099A KR100223917B1 (en) | 1996-06-29 | 1996-06-29 | The structure of a mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960026099A KR100223917B1 (en) | 1996-06-29 | 1996-06-29 | The structure of a mos transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980006487A KR980006487A (en) | 1998-03-30 |
| KR100223917B1 true KR100223917B1 (en) | 1999-10-15 |
Family
ID=19464915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960026099A KR100223917B1 (en) | 1996-06-29 | 1996-06-29 | The structure of a mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100223917B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236572A (en) * | 1988-07-27 | 1990-02-06 | Hitachi Ltd | Semiconductor device |
| JPH0399469A (en) * | 1989-09-12 | 1991-04-24 | Fujitsu Ltd | Semiconductor device |
| US5323036A (en) * | 1992-01-21 | 1994-06-21 | Harris Corporation | Power FET with gate segments covering drain regions disposed in a hexagonal pattern |
-
1996
- 1996-06-29 KR KR1019960026099A patent/KR100223917B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236572A (en) * | 1988-07-27 | 1990-02-06 | Hitachi Ltd | Semiconductor device |
| JPH0399469A (en) * | 1989-09-12 | 1991-04-24 | Fujitsu Ltd | Semiconductor device |
| US5323036A (en) * | 1992-01-21 | 1994-06-21 | Harris Corporation | Power FET with gate segments covering drain regions disposed in a hexagonal pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980006487A (en) | 1998-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2847490B2 (en) | Method for manufacturing transistor | |
| KR100212455B1 (en) | Process for fabricating semiconductor device with dual gate structure | |
| JP3528422B2 (en) | Method for manufacturing thin film transistor | |
| KR100223917B1 (en) | The structure of a mos transistor | |
| KR100396686B1 (en) | Method for forming contact hole of semiconductor device | |
| KR100280527B1 (en) | MOS transistor manufacturing method | |
| KR100295652B1 (en) | Methd for fabricating salicide of semiconductor device | |
| KR19990050035A (en) | How to form a transistor | |
| US7186603B2 (en) | Method of forming notched gate structure | |
| KR20010045138A (en) | Manufacturing method for semiconductor device | |
| KR100215871B1 (en) | Method for fabricating semiconductor device | |
| KR100537273B1 (en) | Method for manufacturing semiconductor device | |
| KR100280537B1 (en) | Semiconductor device manufacturing method | |
| KR0157902B1 (en) | Method of manufacturing semiconductor device | |
| KR0172901B1 (en) | Method of manufacturing thin film transistor | |
| KR100347244B1 (en) | Method for manufacturing semiconductor device | |
| KR0172832B1 (en) | Method of fabricating semiconductor device | |
| KR100470126B1 (en) | Method for forming gate of semiconductor element | |
| KR100223918B1 (en) | Structure of semiconductor devices and the manufacturing method thereof | |
| KR960012574B1 (en) | Manufacturing method of semiconductor device | |
| JP3221777B2 (en) | Manufacturing method of thin film transistor | |
| JPH03171671A (en) | Semiconductor device and manufacture thereof | |
| KR100567047B1 (en) | Menufacturing method for mos transistor | |
| KR100186518B1 (en) | Method of fabricating semiconductor device | |
| KR100232218B1 (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130620 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20140618 Year of fee payment: 16 |
|
| LAPS | Lapse due to unpaid annual fee |