JP2012049554A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in a crystallization method utilizing a metal element in which: impurity elements contained at high concentration necessary for gettering interrupt recrystallization in the subsequent annealing.SOLUTION: Gettering is performed in a manner that an impurity region including a rare gas element is formed in a semiconductor film and a metal element included in the semiconductor film is segregated to the impurity region through thermal treatment and laser annealing. Then, a substrate provided with the semiconductor film (semiconductor film substrate) is irradiated with laser light from above and below the substrate for heating a gate electrode. By the heat, the impurity region overlapping with a part of the gate electrode is heated. This can perform recovery of the crystallinity and activation of the impurity element in the impurity region overlapping with a part of the gate electrode.

Description

  The present invention relates to a semiconductor device manufactured by including annealing of a semiconductor film using a laser beam (hereinafter referred to as laser annealing) and a manufacturing method thereof. Note that the semiconductor device here includes an electro-optical device such as a liquid crystal display device and a light-emitting device and an electronic device including the electro-optical device as a component.

  A technique for crystallizing or improving crystallinity by subjecting a semiconductor film formed on an insulating substrate such as glass to laser annealing has been widely studied. Silicon is often used for the semiconductor film.

  In recent years, there has been a remarkable movement to increase the area of substrates for improving mass production efficiency, and the substrate size of 600 × 720 mm is becoming the standard for newly constructed mass production factory lines. It is difficult to process a synthetic quartz glass substrate on such a large area substrate with the current technology, and even if it can be done, it will not decrease to the price that can be established as an industry. An example of a material capable of easily manufacturing a large-area substrate is a glass substrate. A glass substrate is less expensive than a synthetic quartz glass substrate that has been often used in the past, and has an advantage that a large-area substrate can be easily manufactured. In addition, the reason why lasers are used favorably for crystallization is that the melting point of the glass substrate is low. The laser can give high energy only to the semiconductor film without increasing the temperature of the substrate so much.

  One glass substrate is called Corning 7059, for example. Corning 7059 is very inexpensive, has good workability, and is easy to increase in area. However, Corning 7059 has a strain point temperature of 593 ° C., and there is a problem with heating at 600 ° C. or higher. One glass substrate is Corning 1737, which has a relatively high strain point temperature. Corning 1737 has a strain point temperature of 667 ° C., which is higher than the strain point temperature of Corning 7059. Even when an amorphous semiconductor film was formed on the Corning 1737 substrate and placed in an atmosphere at 600 ° C. for 20 hours, the substrate was not deformed so as to affect the manufacturing process. However, the heating time of 20 hours is too long for a mass production process, and the heating temperature of 600 ° C. is preferably as low as possible from the viewpoint of cost.

  In order to solve such problems, a new crystallization method has been devised. Details of the method are described in JP-A-7-183540. Here, the method will be briefly described. First, a trace amount of a metal element such as nickel, palladium, or lead is added to the amorphous semiconductor film. As the addition method, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. After the addition, for example, when an amorphous semiconductor film is placed in a nitrogen atmosphere at 550 ° C. for 4 hours, a crystalline semiconductor film with good characteristics can be obtained. The optimal heating temperature, heating time, etc. for crystallization depend on the amount of the metal element added and the state of the amorphous semiconductor film.

  However, the technique has a problem that the metal element used for promoting crystallization remains in a high resistance layer (channel formation region or offset region). Since the metal element easily flows electricity, the resistance of the region that should be the high resistance layer is lowered. As a result, the off-current increases, and the stability and reliability of the TFT characteristics, such as variations among individual elements, are impaired.

  In order to solve this problem, a technique (gettering technique) for removing a metal element for promoting crystallization from a crystalline semiconductor film has been developed and disclosed in Japanese Patent Laid-Open No. 10-270363. In the gettering technique, first, an element belonging to Group 15 is selectively added to the crystalline semiconductor film and heat treatment is performed. By the heat treatment, the metal element in the region to which the element belonging to Group 15 is not added (gettering region) is released from the gettering region, diffuses, and is added to the region to which the element belonging to Group 15 is added ( Gettering area). As a result, the metal element can be removed or reduced in the gettering region, and the heating temperature at the time of gettering can be 600 ° C. or less that the glass substrate can withstand. It has also been confirmed that metal elements can be gettered by introducing not only elements belonging to Group 15 but also elements belonging to Group 13.

  Since the crystalline semiconductor film formed through such a manufacturing process has high mobility, a thin film transistor (TFT) is formed using the crystalline semiconductor film, for example, in an active matrix type electro-optical device or the like. It is actively used.

  Active matrix liquid crystal display devices include pixel circuits that display images for each functional block, and drive circuits for controlling pixel circuits such as shift register circuits, level shifter circuits, buffer circuits, and sampling circuits based on CMOS circuits. Are formed on a single substrate.

  In a pixel circuit of an active matrix liquid crystal display device, a TFT (pixel TFT) is disposed in each of tens to millions of pixels, and a pixel electrode is provided in each of the pixel TFTs. A counter electrode is provided on the counter substrate side with the liquid crystal interposed therebetween, and a kind of capacitor using the liquid crystal as a dielectric is formed. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, and the liquid crystal is driven by controlling the charge to this capacitor, and the transmitted light quantity is controlled to display an image.

  The pixel TFT is composed of an n-channel TFT, and is driven by applying a voltage to the liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, in order to keep power consumption low, it is important that the characteristics required for the pixel TFT have a sufficiently low off-current value (drain current that flows when the TFT is off).

  As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. A so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film is known as means for preventing deterioration of an on-current value due to hot carriers. . With such a structure, it is known that a high electric field in the vicinity of the drain is relaxed, hot carrier injection is prevented, and the deterioration phenomenon is effective.

  In order to form the GOLD structure, the end portion of the gate electrode has a tapered shape. By adopting such a shape, a step of introducing an impurity element imparting n-type into the semiconductor layer forming the n-channel TFT, and an impurity element imparting p-type to the semiconductor layer forming the p-channel TFT are formed. In the introduction step, a source region and a drain region are formed in a portion that does not overlap with the gate electrode in one doping process, and an LDD region having a concentration gradient along the taper shape is formed below the taper of the gate electrode. Can be formed.

  In addition, in the doping process, the energy of ions implanted into the semiconductor film is much larger than the binding energy of the elements forming the semiconductor film. For this reason, ions implanted into the semiconductor film blow off elements forming the semiconductor film from lattice points to cause defects in the crystal. Therefore, heat treatment is often performed after the doping treatment in order to recover the defects and to activate the implanted impurity element at the same time. Examples of the heat treatment include a thermal annealing method using a furnace annealing furnace, a laser annealing method, and a rapid thermal annealing method (RTA method). In addition, activating the impurity element is an important process for making the region to which the impurity element is added a low-resistance region and functioning as an LDD region, a source region, and a drain region.

An element belonging to Group 15 is an ion doping method (a method in which PH ₃ or the like is dissociated with plasma and ions are accelerated by an electric field and injected into a semiconductor film, and basically does not perform mass separation of ions. In the case where phosphorus is introduced for gettering, the required phosphorus concentration is 1 × 10 ²⁰ / cm ³ or more. Addition of an element belonging to Group 15 by ion doping causes amorphousness of the semiconductor film, but an increase in the concentration of the element belonging to Group 15 is a problem because it hinders recrystallization by subsequent heat treatment. . In addition, the addition of a high-concentration Group 15 element is problematic because it increases the processing time required for doping and reduces the throughput in the doping process.

Further, an element belonging to Group 15 is an impurity element imparting n-type, and p required for reversing the conductivity type of an element belonging to Group 15 added to the source region and drain region of the p-channel TFT. The concentration of the impurity element that imparts the type (for example, an element belonging to Group 13) needs to be 1.5 to 3 times, and as the recrystallization becomes difficult, the resistance of the source region and the drain region is increased. It is a problem.

  The present invention is a technique for solving such a problem, effectively removing the metal element remaining in the crystalline semiconductor film obtained by using a metal element that promotes crystallization of the semiconductor film, and In a semiconductor device typified by an active matrix liquid crystal display device manufactured using a TFT by sufficiently recovering the crystallinity of the semiconductor film and activating the impurity element, the operating characteristics and reliability of the semiconductor device are improved. The goal is to realize improvements.

  In the present invention, in order to recover the crystallinity of the impurity region overlapping with a part of the gate electrode and activate the impurity element, the surface side of the semiconductor film substrate (in this specification, the surface on which the film is formed). And the gate electrode heated by the laser beam heats the impurity region. At this time, the substrate may be heated to about 450 ° C. By heating the substrate simultaneously with the laser light irradiation, the crystallinity of the impurity region can be recovered and the impurity element can be activated.

  Further, according to the present invention, in order to restore the crystallinity of the impurity region overlapping with a part of the gate electrode and activate the impurity element, the back surface side of the semiconductor film substrate (in this specification, a film is formed). The gate electrode heated by a part of the laser beam that is irradiated with laser light and transmitted through the semiconductor film heats the impurity region. At this time, the substrate may be heated to about 450 ° C. By heating the substrate simultaneously with the laser light irradiation, the crystallinity of the impurity region can be recovered and the impurity element can be activated.

  Further, a heat resistant material is used as a material for forming the gate electrode. As shown in FIG. 5, an element selected from tungsten (W), tantalum (Ta), titanium (Ti), chromium (Cr) and silver (Ag), or a compound or alloy containing the element as a component is used. May be. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Of course, the gate electrode may be a stacked layer instead of a single layer.

  The impurity element region is a region into which an impurity of one conductivity type is introduced. As the one conductivity type impurity, an element belonging to Group 15 or an element belonging to Group 13 is applied. In addition, hydrogen may be added to the impurity region, and the impurity region includes both one conductivity type impurity and hydrogen.

  The impurity region may be added with an element belonging to Group 15 and an element belonging to Group 13, and the impurity region includes both an element belonging to Group 15 and an element belonging to Group 13.

  The impurity region may include an element belonging to Group 15, an element belonging to Group 13, and hydrogen. The impurity region includes both an element belonging to Group 15, an element belonging to Group 13, and hydrogen. It is.

  Further, in order to irradiate the laser beam from the back side, the laser beam is preferably transmitted through the semiconductor film. FIG. 24A shows the transmittance of an amorphous silicon film having a thickness of 55 nm with respect to the wavelength, and FIG. 24B shows the transmittance of a crystalline silicon film having a thickness of 55 nm with respect to the wavelength. According to FIG. 24, the wavelength of the laser light is desirably 350 nm (preferably 400 nm) or more. Of course, since the transmittance of the laser light varies depending on the semiconductor film and the film thickness to be used, the practitioner may determine as appropriate.

  Further, the present invention provides a semiconductor film that is crystallized using a metal element that promotes crystallization, an impurity region to which a rare gas element (also referred to as a rare gas) is added, and the semiconductor film is formed in the impurity region by heat treatment. And performing gettering by segregating the metal element contained in the substrate, and subsequently irradiating a laser beam from the surface side of the semiconductor film substrate so that the gate electrode heated by the laser beam heats the impurity region. Features.

  In the present invention, the semiconductor film is crystallized using a metal element that promotes crystallization, an impurity region to which a rare gas element (also referred to as a rare gas) is added is formed, and the semiconductor film is formed in the impurity region by heat treatment. The gate electrode heated by a part of the laser light transmitted through the semiconductor film is irradiated with laser light from the back side of the semiconductor film substrate. The impurity region is heated.

  By using the rare gas element, the amount of impurity element introduced can be reduced to about 1/3 of the conventional amount. Therefore, damage at the gate insulating film and the semiconductor film and their interface due to the doping process can be reduced, and the number of trap centers can be reduced. This can improve the reliability when a TFT is manufactured. In addition, since the trap center is reduced, the width of the overlap region between the gate electrode and the impurity region can be reduced. As a result, the transistor can be further miniaturized.

  Moreover, the introduction amount of the metal element can be increased by using the rare gas element. Therefore, the heating time for crystallization can be shortened.

  The rare gas element is one or a plurality selected from He, Ne, Ar, Kr, and Xe, and these ions are accelerated by an electric field and injected into the semiconductor film to form dangling bonds and lattice distortion. Thus, a gettering site can be formed.

  In addition, one conductivity type impurity may be added to the impurity region to which the rare gas element is added, and the impurity region includes both the rare gas element and the one conductivity type impurity. As the one conductivity type impurity, an element belonging to Group 15 or an element belonging to Group 13 is applied. In addition, hydrogen may be added to the impurity region, and the impurity region contains both a rare gas element, one conductivity type impurity, and hydrogen.

  Further, an element belonging to Group 15 and an element belonging to Group 13 may be added to the impurity region to which the rare gas element is added, and the impurity region belongs to the rare gas element, the element belonging to Group 15 and the Group 13 Both elements are included.

  Further, an element belonging to Group 15 or an element belonging to Group 13 and hydrogen may be added to the impurity region to which the rare gas element is added, and the impurity region may be added to the rare gas element, the element belonging to Group 15 or the Group 13. Both the element to which it belongs and hydrogen are included.

  The laser used is preferably a solid-state laser rather than a gas laser. The gas used for the gas laser is generally very expensive, and there is a problem that the manufacturing cost increases when the frequency of gas exchange increases. In addition, replacement of attached equipment such as a laser tube for performing laser oscillation and a gas purifier for removing unnecessary compounds generated during the oscillation process is required every two to three years. Many of these accessory devices are expensive, and there is still a problem that the manufacturing cost increases. Therefore, if a solid-state laser such as a YAG laser (laser that outputs a laser beam with a crystal rod as a resonant cavity) is used, the running cost (which means the cost generated during operation) can be reduced compared to a gas laser. This is because it can.

  In addition, when the semiconductor film substrate is irradiated with laser light from the surface side of the semiconductor film substrate, the laser light may be irradiated obliquely onto the semiconductor film substrate.

    Further, there are an amorphous semiconductor film and a crystalline semiconductor film as the semiconductor film, and in addition to the amorphous silicon film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. .

  By applying the present invention as described above, a semiconductor film in which gettering of a metal element, recovery of crystallinity of a semiconductor film, and activation of an impurity element are sufficiently performed can be obtained, and the performance of a semiconductor device can be improved. Can greatly improve. For example, when a TFT is taken as an example, the gettering of a metal element is sufficiently performed, so that an off-current value can be reduced and variation in an off-current value can be suppressed. In addition, when the crystallinity of the semiconductor film is sufficiently restored, the channel formation region becomes a high resistance region, and leakage current can be reduced. In addition, when the impurity element is sufficiently activated, the region to which the impurity element is added can be made to function as an LDD region, a source region, and a drain region by using a low resistance region.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) A simple configuration perfectly adapted to a conventional TFT manufacturing process.
(B) The amount of impurity element introduced can be reduced. Therefore, damage due to doping treatment can be reduced in the gate insulating film, the semiconductor film, and the interface thereof.
(C) The crystallinity of the semiconductor film into which the impurity element is introduced is easily recovered.
(D) The impurity element can be sufficiently activated.
(E) The metal element used for promoting crystallization can be sufficiently removed.
(F) The width of the overlap region between the gate electrode and the low-concentration impurity region can be reduced. This allows further miniaturization of the transistor.
(G) This is a method capable of producing a TFT having excellent electrical characteristics while satisfying the above advantages.

The figure which shows the structure of a laser apparatus. The figure which shows the structure of the optical system of a laser apparatus. The figure which shows an example of the laser annealing method of this invention. 10A and 10B show a manufacturing process of a TFT until formation of a gate electrode. The figure which shows the reflectance with respect to the wavelength in the example of a conductive layer material. 10A and 10B show a manufacturing process of a TFT until formation of a gate electrode. 10A and 10B show a manufacturing process of a TFT until formation of a gate electrode. Sectional drawing which shows the example of the manufacturing process of pixel TFT and TFT of a driver circuit. Sectional drawing which shows the example of the manufacturing process of pixel TFT and TFT of a driver circuit. Sectional drawing which shows the example of the manufacturing process of pixel TFT and TFT of a driver circuit. Sectional drawing which shows the example of the manufacturing process of pixel TFT and TFT of a driver circuit. FIG. 6 is a top view illustrating a pixel in a pixel portion. Sectional drawing which shows the manufacturing process of an active-matrix liquid crystal display device. FIG. 6 is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light emitting device. FIG. 4A is a top view of a light-emitting device. FIG. 5B is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light-emitting device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. FIG. 6 is a cross-sectional structure diagram of a pixel portion of a light emitting device. The figure which shows the resistance value which performed the laser process after gettering. Sectional drawing which shows the manufacturing process of an active-matrix liquid crystal display device. The figure which shows the electrical property when a TFT is produced by applying the present invention. FIG. 6A illustrates a state of laser light irradiation from above a semiconductor film. FIG. 5B is a diagram showing a state of laser light irradiation from below the semiconductor film. (A) The figure which shows the transmittance | permeability with respect to the wavelength in an amorphous silicon film. (B) The figure which shows the transmittance | permeability with respect to the wavelength in a crystalline silicon film.

  An embodiment of the present invention will be described. FIG. 1A illustrates a structure of a laser irradiation apparatus. This laser irradiation apparatus includes a laser oscillator 101, an optical system 201 that processes laser light (preferably a second harmonic) using the laser oscillator 101 as a linear source, and a stage 102 that fixes a translucent substrate. The stage 102 includes a heater 103 and a heater controller 104, and can heat the substrate to 450 ° C. A substrate 106 on which a semiconductor film is formed is provided over the stage 102.

  Note that when the laser light output from the laser oscillator 101 is modulated into the second harmonic or the third harmonic, a wavelength modulator including a nonlinear optical element may be provided immediately after the laser oscillator 101.

  Next, a method for holding the substrate 106 in the laser irradiation apparatus having the structure illustrated in FIG. 1A will be described with reference to FIG. The substrate 106 held on the stage 102 is set in a reaction chamber 107 and irradiated with linear laser light using the laser 101 as an oscillation source. The reaction chamber can be in a reduced pressure state or an inert gas atmosphere by an exhaust system or a gas system (not shown), and can be heated to about 450 ° C. without contaminating the semiconductor film.

  Further, the stage 102 can move in the reaction chamber along the guide rail 108, and the entire surface of the substrate can be irradiated with linear laser light. The laser light is incident from a quartz window (not shown) provided on the upper surface of the substrate 106. In FIG. 1B, a transfer chamber 109, an intermediate chamber 110, and a load / unload chamber 111 are connected to the reaction chamber 107, and the chambers are separated by gate valves 112 and 113.

  A cassette 114 capable of holding a plurality of substrates is installed in the load / unload chamber 111, and the substrates are transferred by a transfer robot 115 provided in the transfer chamber 109. Substrate 106 ′ represents the substrate being transferred. With such a configuration, laser annealing can be continuously performed under reduced pressure or in an inert gas atmosphere.

  Next, the configuration of the optical system 201 that linearizes laser light will be described with reference to FIG. 2A is a view of the optical system 201 as viewed from the side, and FIG. 2B is a view of the optical system 201 as viewed from the top.

  Laser light using the laser 101 as an oscillation source is split in the vertical direction by a cylindrical array lens 202. This divided laser beam is further divided in the horizontal direction by the cylindrical lens 203. That is, the laser light is finally divided into a matrix by the cylindrical array lenses 202 and 203.

The laser light is once condensed by the cylindrical lens 204. At that time, it passes through the cylindrical lens 205 immediately after the cylindrical lens 204.
Thereafter, the light is reflected by the mirror 206, passes through the cylindrical lens 207, and reaches the irradiation surface 208.

  At this time, the laser light projected on the irradiation surface 208 shows a linear irradiation surface. That is, it means that the cross-sectional shape of the laser light transmitted through the cylindrical lens 207 is linear. The homogenization in the width direction (short direction) of the laser beam processed into a linear shape is performed by the cylindrical array lens 202, the cylindrical lens 204, and the cylindrical lens 207. Further, the homogenization of the laser beam in the length direction (long direction) is performed by the cylindrical array lens 203 and the cylindrical lens 205.

  Next, a structure for recovering the crystallinity of the impurity region overlapping the part of the gate electrode and activating the impurity element with the laser light of the present invention will be described with reference to FIG. FIG. 3 shows a state of irradiation of the substrate 106 and the laser beam in FIG.

In FIG. 3, 311 is formed up to the gate electrode of the TFT.
Here, a method for forming the gate electrode of the TFT will be described with reference to FIGS.
First, the transparent substrate 300 is a glass substrate, a synthetic quartz glass substrate, a crystallized glass substrate, or a plastic substrate. As the base insulating film 301, an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy) may be used by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Needless to say, the base insulating film is not a single layer but may be a stacked layer.

  Then, a semiconductor film 303 having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, or the like). There is no limitation on the material of the semiconductor film, but the semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy. A metal element for promoting crystallization is added to the semiconductor film to form a metal-containing layer 304, and heat treatment is performed to crystallize the semiconductor film. Of course, other known crystallization methods (laser crystallization method and the like) may be combined.

  After the crystallized semiconductor film is patterned, an insulating film 306 is formed using an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy), and then a conductive film 306 is formed. There is no particular limitation on the material of the conductive film, but the conductive film may be formed using an element selected from Ta, W, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Needless to say, the conductive film may be a stacked layer instead of a single layer. Subsequently, etching is performed to form a gate electrode 307 having a tapered end.

  Then, an impurity element is introduced by performing a doping process. In the doping treatment, one or more elements selected from rare gas elements and an impurity element imparting n-type or an impurity element imparting p-type are introduced by an ion doping method, an ion implantation method, or the like. One or more elements selected from rare gas elements, an impurity element imparting n-type conductivity, and an impurity element imparting p-type conductivity may be introduced. In addition, hydrogen may be added. Needless to say, the step of introducing a rare gas element and the step of introducing an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be performed separately. By the doping process, a region 303 into which the impurity element is introduced at a high concentration, a region 304 into which the impurity element is introduced at a low concentration by a taper at the end of the gate electrode, and a region (channel formation region) 305 into which the impurity element is not introduced are formed. Then, heat treatment is performed to getter the metal element. By the heat treatment, the metal element moves from the channel formation region to the region to which the impurity element is added, so that the channel formation region can be a high resistance region.

    FIG. 3 shows a method for sufficiently recovering the crystallinity of the region where the rare gas element is introduced. Laser light processed into a linear shape via the optical system 201 described in FIG. 2 (only the cylindrical lens 207 is shown) heats the gate electrode 307, and a part of the gate electrode 307 is heated by the heat. The impurity region 309 overlapping with is heated. (FIG. 23 (A))

  FIG. 23B shows another method for sufficiently recovering the crystallinity of a region into which a rare gas element is introduced. As shown in FIG. 23B, when laser light 317 is irradiated from the back side of the semiconductor substrate, part of the laser light passes through the semiconductor film to heat the gate electrode, and heat 318 from the gate electrode and laser The impurity region 309 overlapping with part of the gate electrode 307 is heated by the light 317.

  As described above, according to the present invention, it is possible to process a laser beam (preferably a laser beam using a solid laser as an oscillation source) into a linear shape, and irradiate the gate electrode with the laser beam. The heated gate electrode can heat the impurity region overlapping with a part of the gate electrode. Further, the source region and the drain region must be low resistance regions as compared with the LDD region. However, since the laser light is irradiated without passing through the gate electrode, the impurity element is sufficiently activated.

  Furthermore, since the stage 102 of the laser irradiation apparatus is provided with the heater 103 and the heater controller 104, it becomes possible to irradiate the laser beam while heating the substrate to about 450 ° C., and to recover the crystallinity more efficiently. In addition, activation of impurity elements can be performed.

  The present invention having the above-described configuration will be described in more detail with the following embodiments.

In this embodiment, an example is shown in which laser irradiation is performed after gettering is performed by adding argon among rare gas elements (one or more selected from As, He, Ne, Ar, Kr, and Xe). .

First, a 10 ppm nickel acetate-containing aqueous solution was applied to a 50 nm amorphous silicon film as a semiconductor film, and then crystallized by dehydrogenation treatment at 500 ° C. for 1 hour and heat treatment at 550 ° C. for 4 hours. A crystalline semiconductor film was used. After this crystallized semiconductor film was patterned, a 90 nm silicon oxide film was formed. Next, after passing through a 90 nm silicon oxide film, phosphorus was implanted into the crystalline semiconductor film, and then argon was implanted. At this time, the phosphorus injection conditions were 5% PH ₃ diluted with hydrogen, an acceleration voltage of 80 keV, and a dose of 1.5 × 10 ¹⁵ / cm ² . The time required for implantation is about 8 minutes, and phosphorus of an average concentration of 2 × 10 ²⁰ / cm ³ can be implanted into the crystalline semiconductor film. On the other hand, argon was implanted at an acceleration voltage of 90 keV and a dose of 2 × 10 ¹⁵ or 4 × 10 ¹⁵ / cm ² . Next, gettering was performed by performing a heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

  Next, excimer laser light was irradiated under conditions of laser energy. Then, the experimental result which measured sheet resistance is shown in FIG.

As shown in FIG. 20, by irradiating the laser beam, the sheet resistance value could be reduced to a level where there is no problem in the device characteristics.

  The present invention irradiates a laser beam after forming the gate electrode, and the gate electrode heated by the laser beam recovers the crystallinity of the impurity region overlapping with a part of the gate electrode and activates the impurity element. is there. Although FIG. 20 shows the case where the gate electrode is not formed, the sheet resistance value can be reduced to a level where there is no problem in terms of device characteristics. Therefore, if the present invention is applied and the means for heating the impurity region further by the gate electrode is increased, the sheet resistance value can be reduced with the lower laser energy shown in FIG. This can further reduce the running cost.

In this embodiment, a pulse oscillation type excimer laser is used as the laser beam, but there is no particular limitation, and a continuous emission excimer laser, a YAG laser, or a YVO ₄ laser may be used.

  Examples of the present invention will be described. FIG. 1A illustrates a structure of a laser irradiation apparatus. This laser irradiation apparatus includes a laser oscillator 101, an optical system 201 that processes laser light (preferably a second harmonic) using the laser oscillator 101 as a linear source, and a stage 102 that fixes a translucent substrate. The stage 102 includes a heater 103 and a heater controller 104, and can heat the substrate to 100 to 450 ° C. A substrate 106 on which a semiconductor film is formed is provided over the stage 102.

  Note that when the laser light output from the laser oscillator 101 is modulated into the second harmonic or the third harmonic, a wavelength modulator including a nonlinear optical element may be provided immediately after the laser oscillator 101. In this embodiment, an Nd: YAG laser is used as the laser oscillator 101, and laser light modulated to a second harmonic by a nonlinear optical element is used. However, since the Nd: YAG laser is a highly coherent laser, a thin film polarizing element (TFP) and a polarizing plate are installed in front of the optical system 201, and laser light oscillated from the laser oscillator 101 is obtained. It is desirable to add an optical path length to a part of the light to prevent interference on the irradiated surface.

  Next, a method for holding the substrate 106 in the laser irradiation apparatus having the structure illustrated in FIG. 1A will be described with reference to FIG. The substrate 106 held on the stage 102 is set in a reaction chamber 107 and irradiated with linear laser light using the laser 101 as an oscillation source. The reaction chamber can be in a reduced pressure state or an inert gas atmosphere by an exhaust system or a gas system (not shown), and can be heated to about 450 ° C. without contaminating the semiconductor film.

  Further, the stage 102 can move in the reaction chamber along the guide rail 108, and the entire surface of the substrate can be irradiated with linear laser light. The laser light is incident from a quartz window (not shown) provided on the upper surface of the substrate 106. In FIG. 1B, a transfer chamber 109, an intermediate chamber 110, and a load / unload chamber 111 are connected to the reaction chamber 107, and the chambers are separated by gate valves 112 and 113.

  A cassette 114 capable of holding a plurality of substrates is installed in the load / unload chamber 111, and the substrates are transferred by a transfer robot 115 provided in the transfer chamber 109. Substrate 106 ′ represents the substrate being transferred. With such a configuration, laser annealing can be continuously performed under reduced pressure or in an inert gas atmosphere.

  Next, the configuration of the optical system 201 that linearizes laser light will be described with reference to FIG. 2A is a view of the optical system 201 as viewed from the side, and FIG. 2B is a view of the optical system 201 as viewed from the top.

  Laser light using the laser 101 as an oscillation source is split in the vertical direction by a cylindrical array lens 202. This divided laser beam is further divided in the horizontal direction by the cylindrical lens 203. That is, the laser light is finally divided into a matrix by the cylindrical array lenses 202 and 203.

The laser light is once condensed by the cylindrical lens 204. At that time, it passes through the cylindrical lens 205 immediately after the cylindrical lens 204.
Thereafter, the light is reflected by the mirror 206, passes through the cylindrical lens 207, and reaches the irradiation surface 208.

  At this time, the laser light projected on the irradiation surface 208 shows a linear irradiation surface. That is, it means that the cross-sectional shape of the laser light transmitted through the cylindrical lens 207 is linear. The homogenization in the width direction (short direction) of the laser beam processed into a linear shape is performed by the cylindrical array lens 202, the cylindrical lens 204, and the cylindrical lens 207. Further, the homogenization of the laser beam in the length direction (long direction) is performed by the cylindrical array lens 203 and the cylindrical lens 205.

  Next, a structure for recovering the crystallinity of the impurity region overlapping the part of the gate electrode and activating the impurity element with the laser light of the present invention will be described with reference to FIG. FIG. 3 shows a state of irradiation of the substrate 106 and the laser beam in FIG.

  Here, a method for forming the gate electrode of the TFT will be described with reference to FIGS. First, the transparent substrate 300 is a glass substrate, a synthetic quartz glass substrate, a crystallized glass substrate, or a plastic substrate. In this embodiment, a synthetic quartz glass substrate is used as the translucent substrate.

  As the base insulating film 301, an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy) may be used by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Needless to say, the base insulating film is not limited to a single layer but may be a stacked layer. In this embodiment, a silicon oxide film having a thickness of 150 nm is formed by plasma CVD.

    Then, a semiconductor film 303 having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, or the like). There is no limitation on the material of the semiconductor film, but the semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this embodiment, an amorphous silicon film having a thickness of 50 nm is formed by plasma CVD. Then, a metal element that promotes crystallization is added to the semiconductor film to form a metal-containing layer 304. As a method for introducing the metal element, plasma treatment, vapor deposition, sputtering, ion implantation, solution coating, or the like may be used. In this embodiment, an aqueous nickel acetate solution (concentration by weight of 15 ppm, volume 5 ml) is applied to the surface of the amorphous silicon film by spin coating. Then, heat treatment is performed to crystallize the semiconductor film. Since the heating time and temperature depend on the semiconductor film and the metal element to be added, the practitioner may determine appropriately. In this example, the substrate is exposed to a nitrogen atmosphere at 550 ° C. for 4 hours. After patterning of the crystallized semiconductor film, the insulating film 306 is formed by a known means (sputtering method, LPCVD method, plasma CVD method, or the like) with an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy). Form with.

    Subsequently, a conductive film 306 is formed. There is no particular limitation on the material of the conductive film, but the conductive film may be formed using an element selected from Ta, W, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Needless to say, the conductive film may be a stacked layer instead of a single layer. In this embodiment, a conductive film 306 made of a W film having a thickness of 400 nm is formed.

Subsequently, etching is performed to form a gate electrode 307 having a tapered end. A mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as an etching process, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are set to 25/25 / Etching was performed by generating a plasma by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa at a pressure of 10 (sccm). Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By this etching process, the W film is etched so that the end portion of the conductive layer is tapered. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
In the above etching treatment, by making the shape of the resist mask suitable, the end portion of the conductive layer is tapered due to the effect of the bias voltage applied to the substrate side. The angle of this taper portion is 15 to 45 °. Reference numeral 305 denotes a gate insulating film, and a region not covered with the conductive layer 306 is etched by about 20 to 50 nm to form a thinned region.

Then, an impurity element is introduced by performing a doping process. In the doping treatment, one or more elements selected from rare gas elements and an impurity element imparting n-type or an impurity element imparting p-type are introduced by an ion doping method, an ion implantation method, or the like. One or more elements selected from rare gas elements, an impurity element imparting n-type conductivity, and an impurity element imparting p-type conductivity may be introduced. In addition, hydrogen may be added. Needless to say, the step of introducing a rare gas element and the step of introducing an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be performed separately. By the doping process, a region 303 into which the impurity element is introduced at a high concentration, a region 304 into which the impurity element is introduced at a low concentration by a taper at the end of the gate electrode, and a region (channel formation region) 305 into which the impurity element is not introduced are formed. In this example, phosphorus was used as an element belonging to Group 15, and argon was used as a rare gas element. The phosphorus injection conditions were 5% PH ₃ diluted with hydrogen, an acceleration voltage of 80 keV, and a dose of 1.5 × 10 ¹⁵ / cm ² . The time required for implantation is about 8 minutes, and phosphorus of an average concentration of 2 × 10 ²⁰ / cm ³ can be implanted into the crystalline semiconductor film. On the other hand, argon was implanted at an acceleration voltage of 90 keV and a dose of 2 × 10 ¹⁵ / cm ² .

    Subsequently, heat treatment is performed to getter the metal element. By the heat treatment, the metal element moves from the channel formation region to the region to which the impurity element is added, so that the channel formation region can be a high resistance region. In this example, gettering was performed by performing heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

    FIG. 3 shows a method for sufficiently recovering the crystallinity of the impurity region overlapping with a part of the gate electrode. Laser light processed into a linear shape via the optical system 201 described in FIG. 2 (only the cylindrical lens 207 is shown) heats the gate electrode 307, and a part of the gate electrode 307 is heated by the heat. The impurity region overlapping with is heated.

  As described above, according to the present invention, it is possible to process a laser beam (preferably a laser beam using a solid laser as an oscillation source) into a linear shape, and irradiate the gate electrode with the laser beam. The heated gate electrode can heat the impurity region overlapping with a part of the gate electrode. Further, the source region and the drain region must be low resistance regions as compared with the LDD region. However, since the laser light is irradiated without passing through the gate electrode, the impurity element is sufficiently activated.

  Furthermore, since the stage 102 of the laser irradiation apparatus is provided with the heater 103 and the heater controller 104, it becomes possible to irradiate the laser beam while heating the substrate to about 450 ° C., and to recover the crystallinity more efficiently. In addition, activation of impurity elements can be performed.

   In this embodiment, a case where laser annealing is performed on a semiconductor film substrate that has undergone a manufacturing process different from that in Embodiment 2 will be described.

Here, a method for forming the gate electrode of the TFT will be described with reference to FIGS. First, according to the second embodiment, the state of FIG. Note that FIG.
Shows the same state as FIG.

  Then, a first heat treatment is performed to crystallize the semiconductor film. Since the heating time and temperature depend on the semiconductor film and the metal element to be added, the practitioner may determine appropriately. In this example, the substrate is exposed to a nitrogen atmosphere at 550 ° C. for 4 hours.

Subsequently, a mask 755 is formed and a first doping process is performed to selectively introduce an impurity element into the semiconductor film. In the doping treatment, one or more elements selected from rare gas elements and an impurity element imparting n-type or an impurity element imparting p-type are introduced by an ion doping method, an ion implantation method, or the like. One or more elements selected from rare gas elements, an impurity element imparting n-type conductivity, and an impurity element imparting p-type conductivity may be introduced. In addition, hydrogen may be added. In this embodiment, argon is implanted by an ion doping method at an acceleration voltage of 90 keV and at a dose of 2 × 10 ¹⁵ / cm ² .

  Then, second heat treatment is performed to move the metal element used for promoting crystallization to a region into which the impurity element is introduced (gettering). In this embodiment, gettering is performed by performing heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

  The region where the metal element is gettered is etched, and the mask is removed to form a semiconductor layer. Then, the insulating film 758 is formed using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) using an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy).

  Subsequently, a conductive film 759 is formed. There is no particular limitation on the material of the conductive film, but the conductive film may be formed using an element selected from Ta, W, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Needless to say, the conductive film may be a stacked layer instead of a single layer. In this example, a conductive film 756 made of a W film having a thickness of 400 nm was formed. The W film is formed by sputtering using a W target.

    Subsequently, etching is performed to form a gate electrode 760 having a tapered end. A mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed. In the etching process, by making the shape of the mask made of resist suitable, the end portion of the conductive layer is tapered due to the effect of the bias voltage applied to the substrate side. The angle of this taper portion is 15 to 45 °. Reference numeral 708 denotes a gate insulating film, and a region not covered with the conductive layer 760 is etched by about 20 to 50 nm to form a thinned region.

Then, an impurity element is introduced by performing a doping process. In the doping treatment, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is introduced by an ion doping method, an ion implantation method, or the like. By the doping process, a region 761 into which the impurity element is introduced at a high concentration, a region 762 into which the impurity element is introduced at a low concentration by a taper at the end of the gate electrode, and a region (channel formation region) 763 into which the impurity element is not introduced are formed. In this example, phosphorus was used as an element belonging to Group 15. The phosphorus injection conditions were 5% PH ₃ diluted with hydrogen, an acceleration voltage of 80 keV, and a dose of 1.5 × 10 ¹⁵ / cm ² . The time required for implantation is about 8 minutes, and phosphorus of an average concentration of 2 × 10 ²⁰ / cm ³ can be implanted into the crystalline semiconductor film.

  Then, heat treatment is performed to getter the metal element. By the heat treatment, the metal element moves from the channel formation region to the region to which the impurity element is added, so that the channel formation region can be a high resistance region. In this example, gettering was performed by performing heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

  Then, the crystallinity of the impurity region overlapping with a part of the gate electrode is sufficiently recovered by the method shown in FIG.

  Furthermore, since the stage 102 of the laser irradiation apparatus is provided with the heater 103 and the heater controller 104, it becomes possible to irradiate the laser beam while heating the substrate to about 450 ° C., and to recover the crystallinity more efficiently. In addition, activation of impurity elements can be performed.

   In this example, a case where laser annealing is performed on a semiconductor film substrate that has undergone a manufacturing process different from those in Example 2 and Example 3 will be described.

    Here, a method for forming the gate electrode of the TFT will be described with reference to FIG. First, according to Embodiment 2, a state in which the semiconductor film 303 in FIG. 4A is formed is obtained. Note that portions corresponding to those in FIG. 4A are denoted by the same reference numerals in FIG.

  After the insulating film 770 having an opening is formed by a known means (sputtering method, LPCVD method, plasma CVD method, or the like) with an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy). Then, a metal element that promotes crystallization is added to form the metal-containing layer 304. As a method for introducing the metal element, plasma treatment, vapor deposition, sputtering, ion implantation, solution coating, or the like may be used. A first heat treatment is performed to crystallize the semiconductor film. Since the heating time and temperature depend on the semiconductor film and the metal element to be added, the practitioner may determine appropriately. In this example, the substrate is exposed to a nitrogen atmosphere at 550 ° C. for 4 hours.

Subsequently, a first doping process is performed to selectively introduce an impurity element into the semiconductor film. In the doping process, one or more elements selected from rare gas elements are introduced by an ion doping method, an ion implantation method, or the like. Alternatively, one or more elements selected from rare gas elements and an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be introduced. One or more elements selected from rare gas elements, an impurity element imparting n-type conductivity, and an impurity element imparting p-type conductivity may be introduced. In addition, hydrogen may be added. In this embodiment, argon is implanted by an ion doping method at an acceleration voltage of 90 keV and at a dose of 2 × 10 ¹⁵ / cm ² .

  Then, second heat treatment is performed to move the metal element used for promoting crystallization to a region into which the impurity element is introduced (gettering). In this embodiment, gettering is performed by performing heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

  The semiconductor layer 773 is formed by partly etching the insulating film 770 and the semiconductor film. Then, the insulating film 774 is formed using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) using an insulating film containing silicon such as a silicon oxide film or a silicon nitride oxide film (SiOxNy).

  Subsequently, a conductive film 775 is formed. There is no particular limitation on the material of the conductive film, but the conductive film may be formed using an element selected from Ta, W, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Needless to say, the conductive film may be a stacked layer instead of a single layer. In this embodiment, a conductive film 775 made of a W film having a thickness of 400 nm is formed.

    Subsequently, etching is performed to form a gate electrode 776 having a tapered end. A mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed. In the etching process, by making the shape of the mask made of resist suitable, the end portion of the conductive layer is tapered due to the effect of the bias voltage applied to the substrate side. The angle of this taper portion is 15 to 45 °. Reference numeral 708 denotes a gate insulating film, and a region not covered with the conductive layer 760 is etched by about 20 to 50 nm to form a thinned region.

Then, a second doping process is performed to introduce an impurity element. In the doping treatment, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is introduced by an ion doping method, an ion implantation method, or the like. By the doping process, a region 777 into which the impurity element is introduced at a high concentration, a region 778 into which the impurity element is introduced at a low concentration by a taper at the end of the gate electrode, and a region (channel formation region) 779 into which the impurity element is not introduced are formed. In this embodiment, phosphorus is used as an impurity element imparting n-type. The phosphorus injection conditions were 5% PH ₃ diluted with hydrogen, an acceleration voltage of 80 keV, and a dose of 1.5 × 10 ¹⁵ / cm ² . The time required for implantation is about 8 minutes, and phosphorus of an average concentration of 2 × 10 ²⁰ / cm ³ can be implanted into the crystalline semiconductor film.

  Then, the crystallinity of the impurity region overlapping with a part of the gate electrode is sufficiently recovered by the method shown in FIG.

  Further, since the stage 102 of the laser irradiation apparatus is provided with the heater 103 and the heater controller 104, it is possible to irradiate the laser beam while heating the substrate to 100 to 450 ° C. Recovery and activation of impurity elements can be performed.

  In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

  First, in this embodiment, a substrate 320 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 320 may be a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Next, a base film 321 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 320. Although a two-layer structure is used as the base film 321 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, a silicon oxynitride film 321a formed by using a plasma CVD method and using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is formed to 10 to 200 nm (preferably 50 to 100 nm). To do. In this embodiment, a 50 nm thick silicon oxynitride film 301a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) was formed. Next, as a second layer of the base film 301, a silicon oxynitride film 321b formed by using a plasma CVD method and using SiH ₄ and N ₂ O as a reaction gas is formed to have a thickness of 50 to 200 nm (preferably 100 to 150 nm). Stacked to a thickness. In this embodiment, a silicon oxynitride film 321b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.

  Next, a semiconductor film 322 is formed over the base film. As the semiconductor film 322, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy. Subsequently, a thermal crystallization method using a catalyst such as nickel is performed. If gettering of a metal element using Ar is performed in a subsequent step, the amount of metal element introduced is 3 to 50 ppm (preferably 15 to 30 ppm) in a thermal crystallization method using a catalyst such as nickel. be able to. Further, a thermal crystallization method using a catalyst such as nickel may be combined with other known crystallization treatments (laser crystallization method, thermal crystallization method, etc.). The crystalline semiconductor film obtained by performing the patterning is patterned into a desired shape to form semiconductor layers 402 to 406. In this embodiment, a plasma CVD method is used to form a 55 nm amorphous silicon film, and then a solution containing nickel is held on the amorphous silicon film. This amorphous silicon film was dehydrogenated (500 ° C., 1 hour) and then subjected to heat treatment (550 ° C., 4 hours) to form a crystalline silicon film. Then, semiconductor layers 402 to 406 are formed by patterning the crystalline silicon film using a photolithography method.

In the case where a laser crystallization method is also applied to crystallize a semiconductor film, a pulse oscillation type or continuous light emission type excimer laser, YAG laser, YVO ₄ laser, or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film.
The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 800 mJ / cm ² (typically 200 to 700 mJ / cm ^2). ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 300 to 1000 mJ / cm ² (typically 350 to 800 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser beam at this time is set to 50 to 98%. Also good.

  After forming the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

  Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Next, as illustrated in FIG. 8B, a first conductive film 408 with a thickness of 20 to 100 nm and a second conductive film 409 with a thickness of 100 to 400 nm are stacked over the gate insulating film 407. In this embodiment, a first conductive film 408 made of a TaN film with a thickness of 30 nm and a second conductive film 409 made of a W film with a thickness of 370 nm are stacked.
The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, a sputtering method using a target of high purity W (purity 99.9999%) is used, and the W film is formed with sufficient consideration so that impurities are not mixed in from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408 is TaN and the second conductive film 409 is W. However, there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Cu, Cr, and Nd. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.
In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film may be formed of a tantalum nitride (TaN) film, and the second conductive film may be a Cu film.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 25. Etching was performed by generating plasma by applying 500 W of RF (13.56 MHz) power to the coil type electrode at a pressure of 1 Pa at a pressure of 1/25/10 (sccm). Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.

Thereafter, the masks 410 to 415 made of resist are changed to the second etching conditions without removing them, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). Etching was performed for about 30 seconds by applying 500 W RF (13.56 MHz) power to the coil electrode at a pressure of 1 Pa to generate plasma. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 417 to 422 (first conductive layers 417 a to 422 a and second conductive layers 417 b to 422 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 422 is etched and thinned by about 20 to 50 nm.

Then, the first doping process is performed without removing the resist mask, and the noble gas element for gettering the impurity element imparting n-type to the semiconductor layer and the metal element used for promoting crystallization. Add. (FIG. 9A) The doping process may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose of 1 × 10 ^{12 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 60 to 100 keV. If the gettering of the metal element by Ar is applied, the dose can be reduced to about 1/3 of the conventional amount. In this embodiment, the dose is set to 1.5 × 10 ¹⁴ / cm ² and the acceleration voltage is set to 80 keV.
As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. Argon was used as a rare gas element. In this case, the conductive layers 417 to 421 serve as a mask for the impurity element imparting n-type, and the first high-concentration impurity regions 306 to 310 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first high-concentration impurity regions 306 to 310 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . On the other hand, argon was implanted at an acceleration voltage of 90 keV and a dose of 2 × 10 ¹⁵ / cm ² .

Next, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl _2, and O ₂ are used as the etching gas, and the W film is selectively etched. At this time, second conductive layers 428b to 433b are formed by a second etching process. On the other hand, the first conductive layers 417a to 422a are hardly etched, and the second shape conductive layers 428 to 433 are formed.

Next, a second doping process is performed as shown in FIG. 9B without removing the resist mask. In this case, an impurity element imparting n-type conductivity is introduced at a high acceleration voltage of 70 to 120 keV with a lower dose than in the first doping treatment. In this embodiment, the dose is set to 1.5 × 10 ¹⁴ / cm ² and the acceleration voltage is set to 90 keV. The second doping process uses the second shape conductive layers 428 to 433 as a mask, and an impurity element is also introduced into the semiconductor layer below the second conductive layers 428 b to 433 b to newly add a second high concentration impurity. Regions 423a to 427a and low concentration impurity regions 423b to 427b are formed.

Next, after removing the resist mask, new resist masks 434a and 434b are formed, and a third etching process is performed as shown in FIG. 9C. The etching gas is SF ₆ and Cl ₂ , the gas flow rate ratio is 50/10 (sccm), and 500 W of RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.3 Pa to generate plasma. And etching is performed for about 30 seconds. 10 W of RF (13.56 MHz) power is applied to the substrate side (the material stage), and a substantially self-bias voltage that is not substantially applied is applied. In this manner, the TaN film of the p-channel TFT and the pixel portion TFT (pixel TFT) is etched by the third etching process to form third shape conductive layers 435 to 438.

  Next, after removing the resist mask, the gate insulating film 416 is selectively removed by using the second shape conductive layers 428 and 430 and the second shape conductive layers 435 to 438 as masks. 439 to 444 are formed. (Fig. 10 (A))

Next, new resist masks 445a to 445c are formed, and a third doping process is performed. By this third doping treatment, impurity regions 446 and 447 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes the active layer of the p-channel TFT. The second conductive layers 435a and 438a are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity regions 446 and 447 are formed by ion doping using diborane (B ₂ H ₆ ). (FIG. 10B) In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 445a to 445c made of resist. By the first doping process and the second doping process, phosphorus is added to the impurity regions 446 and 447 at different concentrations, respectively, and the concentration of the impurity element imparting p-type in each of the regions is 1 ×. ^By performing the doping treatment so as to be 10 ²⁰ to 1 × 10 ²¹ / cm ³ , no problem arises because it functions as the source region and drain region of the p-channel TFT. Further, if gettering of a metal element by Ar is applied, the dose can be reduced to about こ れ. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added. × 10 ¹⁴ / cm ² , followed by an acceleration voltage of 30 keV and a dose of 2 × 10 ¹⁵ / cm ² .

  Through the above steps, impurity regions are formed in the respective semiconductor layers.

  Next, the resist masks 445a to 445c are removed, and a first interlayer insulating film 461 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 461 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

  Next, as shown in FIG. 10C, heat treatment is performed to recover the crystallinity of the semiconductor layers and to activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, it may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

  Note that in this embodiment, simultaneously with the activation treatment, the impurity regions 423a, 425a, 426a, 446a, and 447a in which nickel used as a catalyst in the crystallization contains high-concentration phosphorus are crystallized. Therefore, the metal element is gettered in the impurity region, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.

  In addition, heat treatment may be performed before forming the first interlayer insulating film. However, if the wiring material used is vulnerable to heat, heating is performed after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring as in this embodiment. It is preferable to perform processing.

  In order to sufficiently recover the crystallinity of the impurity region overlapping with a part of the gate electrode and activate the impurity element sufficiently, the gate electrode heated by the laser beam irradiated from the surface side of the substrate is separated from the part of the gate electrode. The overlapping impurity region is heated. (FIG. 10C) At this time, if a heat treatment is also performed from the back side of the substrate using a heater or the like at the same time, the hydrogenation treatment can be performed with hydrogen contained in the first interlayer film.

  In addition, when a small amount of impurity element (boron or phosphorus) is doped to control the threshold value of the TFT, the crystallinity of the channel formation region is sufficiently restored by irradiation with laser light from the back surface. It will be.

  In the step of performing laser annealing, when heat treatment is not performed at the same time, a step of hydrogenating the semiconductor layer by performing heat treatment at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. It is desirable to do so. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. In this example, an acrylic resin film having a film thickness of 1.6 μm was formed, but a film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp, and having an uneven surface formed.

  In this embodiment, in order to prevent specular reflection, the surface of the pixel electrode is formed with the unevenness by forming the second interlayer insulating film having the unevenness on the surface. In addition, a convex portion may be formed in a region below the pixel electrode in order to make the surface of the pixel electrode uneven to achieve light scattering. In that case, since the convex portion can be formed using the same photomask as that of the TFT, the convex portion can be formed without increasing the number of steps. In addition, this convex part should just be suitably provided on the board | substrate of pixel part area | regions other than wiring and a TFT part. Thus, irregularities are formed on the surface of the pixel electrode along the irregularities formed on the surface of the insulating film covering the convex portions.

  Alternatively, a film whose surface is planarized may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, adding a step such as a known sandblasting method or etching method to make the surface uneven, prevent specular reflection, and increase the whiteness by scattering the reflected light Is preferred.

  In the driver circuit 506, wirings 463 to 467 that are electrically connected to the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.

  In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 11) With this connection electrode 468, the source wiring (lamination of 443b and 449) is electrically connected to the pixel TFT. In addition, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT and further electrically connected to the semiconductor layer 458 functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 470, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.

  As described above, a CMOS circuit including an n-channel TFT 501 and a p-channel TFT 502, a driver circuit 506 having an n-channel TFT 503, and a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.

  The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 423c, a low-concentration impurity region 423b (GOLD region) that overlaps with the first conductive layer 428a which forms part of the gate electrode, and a high function as a source region or a drain region. A concentration impurity region 423a is provided. The p-channel TFT 502 which is connected to the n-channel TFT 501 and the electrode 466 to form a CMOS circuit functions as a channel formation region 446d, impurity regions 446b and 446c formed outside the gate electrode, and a source region or a drain region. A high concentration impurity region 446a is provided. In addition, the n-channel TFT 503 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) that overlaps with the first conductive layer 430a that forms part of the gate electrode, and a high-concentration function as a source region or a drain region. An impurity region 425a is provided.

  The pixel TFT 504 in the pixel portion includes a channel formation region 426c, a low concentration impurity region 426b (LDD region) formed outside the gate electrode, and a high concentration impurity region 426a functioning as a source region or a drain region. In addition, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 447a and 447b functioning as one electrode of the storage capacitor 505. The storage capacitor 505 is formed using an electrode (a stack of 438a and 438b) and semiconductor layers 447a to 447c using the insulating film 444 as a dielectric.

In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

  FIG. 12 shows a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line A-A ′ in FIG. 11 corresponds to a cross-sectional view taken along the chain line A-A ′ in FIG. 12. Further, a chain line B-B ′ in FIG. 11 corresponds to a cross-sectional view taken along the chain line B-B ′ in FIG. 12.

  In order to confirm the effectiveness of the present invention, the electrical characteristics of the TFT fabricated according to Example 5 were measured. The following experiment was conducted using a YAG laser.

However, in this embodiment, boron is implanted at an acceleration voltage of 30 keV and a dose amount of 5 × 10 ¹³ / cm ² in order to control the TFT threshold value. In the example, phosphorus alone was implanted at an acceleration voltage of 80 keV and a dose of 1 × 10 ¹⁵ / cm ² . In this embodiment, the heat treatment and laser annealing steps shown in FIG. 10C are performed for only heat treatment (thermal annealing) and only for laser annealing, and the electrical characteristics of the TFT are measured. Then, comparative evaluation was made. The heat treatment was thermal annealing using a furnace annealing furnace, which was exposed to a temperature of 550 ° C. in a nitrogen atmosphere for 4 hours. Laser annealing was performed from above the substrate using the second harmonic of a YAG laser.

    A TFT was manufactured through these steps, and the electrical characteristics were measured. The result is shown in FIG. FIG. 22A shows an off-current value, FIG. 22B shows a threshold value, and FIG. 22C shows an S value. It can be seen that laser annealing has improved the characteristics over thermal annealing. This also shows that the present invention is extremely effective.

  In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 5 will be described below. FIG. 13 is used for the description.

  First, after obtaining the active matrix substrate in the state of FIG. 11 according to the fifth embodiment, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 572 for maintaining a substrate interval at a desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Next, a counter substrate 569 is prepared. Next, colored layers 570 and 571 and a planarization film 573 are formed over the counter substrate 569. The red colored layer 570 and the blue colored layer 572 are overlapped to form a light shielding portion. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.

  In this example, the substrate shown in Example 5 is used. Therefore, in FIG. 12, which shows a top view of the pixel portion of Example 5, at least the gap between the gate wiring 469 and the pixel electrode 470, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 are provided. It is necessary to shield the light. In this example, the respective colored layers were arranged so that the light-shielding portions formed by the lamination of the colored layers overlapped at the positions where light shielding should be performed, and the counter substrate was bonded.

  As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.

  Next, a counter electrode 576 made of a transparent conductive film was formed over the planarization film 573 in at least the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing process was performed.

  Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 13 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.

  The liquid crystal display panel manufactured as described above can be used as a display portion of various electronic devices.

  Note that this embodiment can be freely combined with Embodiments 1 to 6.

  In this embodiment, a process of manufacturing an active matrix liquid crystal display device different from that in Embodiment 7 from the active matrix substrate manufactured in Embodiment 5 will be described below. FIG. 21 is used for the description.

  First, after obtaining the active matrix substrate in the state of FIG. 11 according to Example 5, an alignment film 1067 is formed on the active matrix substrate of FIG. 11 and a rubbing process is performed. Note that in this embodiment, before forming the alignment film 1067, columnar spacers for maintaining the distance between the substrates are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Next, a counter substrate 1068 is prepared. The counter substrate is provided with a color filter in which a colored layer 1074 and a light shielding layer 1075 are arranged corresponding to each pixel. Further, a light shielding layer 1077 is also provided in the driver circuit portion. A planarizing film 1076 covering the color filter and the light shielding layer 1077 is provided. Next, a counter electrode 1069 made of a transparent conductive film was formed over the planarizing film 176 in the pixel portion, an alignment film 1070 was formed over the entire surface of the counter substrate, and a rubbing process was performed.

  Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 1071. A filler is mixed in the sealant 1071, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 1073 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 1073. In this way, the active matrix liquid crystal display device shown in FIG. 21 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed using the well-known technique.

  The liquid crystal display panel manufactured as described above can be used as a display portion of various electronic devices.

  Note that this embodiment can be freely combined with Embodiments 1 to 6.

  In this example, an example in which a light-emitting device is manufactured using the present invention will be described. In this specification, the light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element includes a layer (light-emitting layer) containing an organic compound from which luminescence (Electro Luminescence) generated by applying an electric field is obtained, an anode layer, and a cathode layer. In addition, luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state, one of these, Or both luminescence is included.

  FIG. 14 is a cross-sectional view of the light emitting device of this example. In FIG. 14, a switching TFT 603 provided over a substrate 700 is formed using the n-channel TFT 503 in FIG. Therefore, the description of the n-channel TFT 503 may be referred to for the description of the structure.

  Note that although a double gate structure in which two channel formation regions are formed is used in this embodiment, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.

  A driver circuit provided over the substrate 700 is formed using the CMOS circuit of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 501 and the p-channel TFT 502 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

  Further, the wirings 701 and 703 function as source wirings of the CMOS circuit, and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring that electrically connects the source wiring 708 and the source region of the switching TFT, and the wiring 705 functions as a wiring that electrically connects the drain wiring 709 and the drain region of the switching TFT.

  Note that the current control TFT 604 is formed using the p-channel TFT 502 of FIG. Accordingly, the description of the p-channel TFT 502 may be referred to for the description of the structure. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

  A wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and 707 is an electrode that is electrically connected to the pixel electrode 710 by being overlaid on the pixel electrode 710 of the current control TFT.

  Reference numeral 710 denotes a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 710 is formed on the flat interlayer insulating film 711 before forming the wiring. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since the light emitting layer formed later is very thin, the presence of a step may cause a light emission failure. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After the wirings 701 to 707 are formed, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or organic resin film containing silicon of 100 to 400 nm.

Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the addition amount of carbon particles or metal particles may be adjusted so that the resistivity is 1 × 10 ⁶ to 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

A light emitting layer 713 is formed on the pixel electrode 710. Although only one pixel is shown in FIG. 14, in this embodiment, light emitting layers corresponding to each color of R (red), G (green), and B (blue) are separately formed. In this embodiment, a low molecular weight organic light emitting material is formed by a vapor deposition method. Specifically, a laminated structure in which a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer and a tris-8-quinolinolato aluminum complex (Alq ₃ ) film having a thickness of 70 nm is provided thereon as a light emitting layer. It is said.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. A light emitting layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer is shown, but a high molecular weight organic light emitting material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer.
Known materials can be used for these organic light emitting materials and inorganic materials.

  Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.

  When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 here refers to a diode formed by the pixel electrode (anode) 710, the light-emitting layer 713, and the cathode 714.

  It is effective to provide a passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the light-emitting layer 713. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing process can be prevented.

  Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film).

  Thus, a light emitting device having a structure as shown in FIG. 14 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.

  Thus, the n-channel TFTs 601 and 602, the switching TFT (n-channel TFT) 603, and the current control TFT (n-channel TFT) 604 are formed on the insulator 501 having the plastic substrate as a base. The number of masks required in the manufacturing process so far is smaller than that of a general active matrix light emitting device.

  That is, the TFT manufacturing process is greatly simplified, and the yield can be improved and the manufacturing cost can be reduced.

  Furthermore, as described with reference to FIGS. 14A and 14B, an n-channel TFT which is resistant to deterioration due to the hot carrier effect can be formed by providing an impurity region overlapping with the gate electrode through an insulating film. Therefore, a highly reliable light emitting device can be realized.

  Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

  Further, the light-emitting device of this example after performing the sealing (or sealing) process for protecting the light-emitting element will be described with reference to FIG. In addition, the code | symbol used in FIG. 14 is quoted as needed.

  FIG. 15A is a top view illustrating a state where the light-emitting element is sealed, and FIG. 15B is a cross-sectional view taken along line C-C ′ in FIG. Reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 806 denotes a pixel portion, and 807 denotes a gate side driver circuit. Reference numeral 901 denotes a cover material, reference numeral 902 denotes a first sealing material, reference numeral 903 denotes a second sealing material, and a sealing material 907 is provided on the inner side surrounded by the first sealing material 902.

  Reference numeral 904 denotes a wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.

  Next, a cross-sectional structure is described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700, and the pixel portion 806 is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to a drain thereof. . The gate side driver circuit 807 is formed using a CMOS circuit (see FIG. 14) in which an n-channel TFT 601 and a p-channel TFT 602 are combined.

  The pixel electrode 710 functions as an anode of the light emitting element. A bank 712 is formed at both ends of the pixel electrode 710, and a light emitting layer 713 and a cathode 714 of the light emitting element are formed on the pixel electrode 710.

  The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with a cathode 714 and a passivation film 567.

  Further, a cover material 901 is bonded to the first seal material 902. Note that a spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element. A sealing material 907 is filled inside the first sealing material 902. Note that an epoxy-based resin is preferably used as the first sealing material 902 and the sealing material 907. The first sealing material 902 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a hygroscopic effect or a substance having an antioxidant effect may be contained in the sealing material 907.

  The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

  In addition, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 can use the same material as the first sealing material 902.

  By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the light emitting layer such as moisture and oxygen enters from the outside. Can be prevented. Therefore, a highly reliable light emitting device can be obtained.

  Note that this embodiment can be freely combined with Embodiments 1 to 6.

  In this embodiment, a light-emitting device having a pixel structure different from that in Embodiment 9 will be described. FIG. 19 is used for the description.

  In FIG. 19, a TFT having the same structure as that of the n-channel TFT 504 in FIG. Of course, the gate electrode of the current control TFT 4501 is electrically connected to the drain wiring of the switching TFT 4402. Further, the drain wiring of the current control TFT 4501 is electrically connected to the pixel electrode 4504.

  In this embodiment, the pixel electrode 4504 made of a conductive film functions as a cathode of the light emitting element. Specifically, an alloy film of aluminum and lithium is used, but a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film added with these elements may be used.

  A light emitting layer 4505 is formed over the pixel electrode 4504. Although only one pixel is shown in FIG. 19, in this embodiment, the light emitting layer corresponding to G (green) is formed by vapor deposition and coating (preferably spin coating). Specifically, a 20 nm thick lithium fluoride (LiF) film is provided as an electron injection layer, and a 70 nm thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

  Next, an anode 4506 made of a transparent conductive film is provided on the light emitting layer 4505. In this embodiment, a conductive film made of a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used as the transparent conductive film.

  When the anode 4506 is formed, a light emitting element 4507 is completed. Note that the light-emitting element 4507 here refers to a diode formed with a pixel electrode (cathode) 4504, a light-emitting layer 4505, and an anode 4506.

  It is effective to provide a passivation film 4508 so as to completely cover the light emitting element 4507. The passivation film 4508 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film is used as a single layer or a combination of stacked layers.

  Further, a sealing material 4509 is provided over the passivation film 4508 and a cover material 4510 is attached thereto. As the sealing material 4509, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorption effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 4510 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film).

  Note that this embodiment can be freely combined with Embodiments 1 to 6.

  The CMOS circuit and the pixel portion formed by applying the present invention and implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EC display, active matrix light emitting display). I can do it. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.

  Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS. 16, 17 and 18.

  FIG. 16A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. The present invention can be applied to the display portion 3003.

  FIG. 16B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. The present invention can be applied to the display portion 3102.

  FIG. 16C illustrates a mobile computer, which includes a main body 3201, a camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

  FIG. 16D illustrates a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.

  FIG. 16E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402.

  FIG. 16F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 3502.

  FIG. 17A illustrates a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to a liquid crystal display device 3808 constituting a part of the projection device 3601 and other driving circuits.

  FIG. 17B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 2702 and other driving circuits.

  Note that FIG. 17C illustrates an example of the structure of the projection devices 3601 and 3702 in FIGS. 17A and 17B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 17D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 2811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 2815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 17D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  However, the projector shown in FIG. 17 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and a light-emitting device is not shown.

  FIG. 18A illustrates a mobile phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. The present invention can be applied to the display portion 3904.

  FIG. 18B illustrates a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003.

  FIG. 18C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-10.

Claims (7)

Forming an amorphous semiconductor film on the substrate;
Adding a metal element for promoting crystallization to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to form a crystalline semiconductor film;
Forming an insulating film on the crystalline semiconductor film;
A conductive film having a tapered cross-sectional shape at the end is formed on the insulating film,
An impurity element is added to the crystalline semiconductor film using the conductive film as a mask, a channel formation region overlapping the conductive film, a first impurity region overlapping a tapered end portion of the conductive film, and the first Forming a second impurity region that is in contact with one impurity region and does not overlap the conductive film;
One or more elements selected from He, Ne, Ar, Kr and Xe are added to the second impurity region using the conductive film as a mask,
Performing a second heat treatment on the crystalline semiconductor film, gettering the metal element contained in the channel formation region into the second impurity region,
Irradiating the crystalline semiconductor film with laser light to heat the conductive film and the second impurity region;
The method for manufacturing a semiconductor device, wherein the conductive film heated by the laser light heats the first impurity region. Forming an amorphous semiconductor film on the substrate;
Adding a metal element for promoting crystallization to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to form a crystalline semiconductor film;
Forming an insulating film on the crystalline semiconductor film;
A conductive film having a tapered cross-sectional shape at the end is formed on the insulating film,
An impurity element is added to the crystalline semiconductor film using the conductive film as a mask, a channel formation region overlapping the conductive film, a first impurity region overlapping a tapered end portion of the conductive film, and the first Forming a second impurity region that is in contact with one impurity region and does not overlap the conductive film;
One or more elements selected from He, Ne, Ar, Kr and Xe are added to the second impurity region using the conductive film as a mask,
Performing a second heat treatment on the crystalline semiconductor film, gettering the metal element contained in the channel formation region into the second impurity region,
Simultaneously irradiating the crystalline semiconductor film with laser light, heating the conductive film and the second impurity region by heating the substrate from below,
The method for manufacturing a semiconductor device, wherein the conductive film heated by the laser light heats the first impurity region. In claim 2,
The method for manufacturing a semiconductor device, wherein the crystalline semiconductor film is heated to 0 to 450 ° C. by a heater when the laser light is irradiated. In any one of Claim 1 thru | or 3,
The method for manufacturing a semiconductor device, wherein the substrate has a light-transmitting property. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device, wherein the impurity element is one or more elements selected from elements belonging to Group 15. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device, wherein the impurity element is one or more elements selected from elements belonging to Group 15 and one or more elements selected from elements belonging to Group 13 . In any one of Claims 1 thru | or 6,
The conductive film is an element selected from Ta, W, Ti, Mo, Cu, Cr, and Nd, or a single layer or a stack made of an alloy material or a compound material containing the element as a main component. A method for manufacturing a semiconductor device.

Images