JPH04101432A - Manufacture of mis-type transistor - Google Patents
Manufacture of mis-type transistorInfo
- Publication number
- JPH04101432A JPH04101432A JP21881390A JP21881390A JPH04101432A JP H04101432 A JPH04101432 A JP H04101432A JP 21881390 A JP21881390 A JP 21881390A JP 21881390 A JP21881390 A JP 21881390A JP H04101432 A JPH04101432 A JP H04101432A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- gate electrode
- polycrystalline silicon
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 abstract description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 28
- 230000005669 field effect Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、Ｍｌ、Ｓ型トランジスタの製造方法に関し、
特に、ＬＤＤ （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａ
ｉｎ） ｊｆｌ造ＭＯ８型電界効果トランジスタの製
造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an Ml, S type transistor,
In particular, LDD (Lightly Doped Dra
in) A method for manufacturing a MO8 type field effect transistor manufactured by JFL.
従来のＬ Ｄ Ｄ構造ＭＯ３型トランジスタの製造方法
を第２図（ａ）、（ｂ）を参照して説明する。A method of manufacturing a conventional LDD structure MO3 type transistor will be explained with reference to FIGS. 2(a) and 2(b).
先ず、第２図（ａ）に示すように、Ｐ型シリコン基板２
０１表面にＬＯＣＯ８法によりフィールド酸化膜２０２
を形成して素子領域を区画したのち、その素子領域のＰ
型シリコン基板２０１の表面を酸化し、ゲート酸化膜２
０３を形成し、フォトエツチング法により、Ｎ型多結晶
シリコンのゲート電極２０４を形成する。その後、イオ
ン注入法によりリン（ＳＩＰ＋）を注入しＮ型の低濃度
拡散層２０５−１，２０５−２を形成する。その後、Ｃ
ＶＤ法により酸化シリコン膜を基板上に形成し、異方性
エツチングによりエッチバックを行いゲート電極２０４
の側壁にのみ酸化シリコン膜を残してスペーサ２１３を
形成する。その後、第２図（ｂ）に示すように、イオン
注入法にて、ひ素（７５ＡＳ＋）を注入し、Ｎ型の高濃
度拡散層２１０−１，２１０−２を形成し、イオン注入
のダメージ回復及びひ素の活性化の為、９００°Ｃ程度
の熱処理を行っていた。First, as shown in FIG. 2(a), a P-type silicon substrate 2 is
Field oxide film 202 is formed on the surface of 01 by LOCO8 method.
After dividing the element region by forming
The surface of the mold silicon substrate 201 is oxidized to form a gate oxide film 2.
03 is formed, and a gate electrode 204 of N-type polycrystalline silicon is formed by photoetching. Thereafter, phosphorus (SIP+) is implanted by ion implantation to form N-type low concentration diffusion layers 205-1 and 205-2. After that, C
A silicon oxide film is formed on the substrate by the VD method, and etched back by anisotropic etching to form the gate electrode 204.
A spacer 213 is formed leaving the silicon oxide film only on the sidewalls. After that, as shown in FIG. 2(b), arsenic (75AS+) is implanted using the ion implantation method to form N-type high concentration diffusion layers 210-1 and 210-2, and the damage caused by the ion implantation is recovered. In order to activate arsenic, heat treatment was performed at approximately 900°C.
この従来のＬ Ｄ Ｄ ）−ランジスタの製造方法では
、スペーサ形成のためのエッチバック時にゲート酸化膜
もエツチングされイオンでシリコン基板を直接たたくこ
とが多く将来ソース・トレインを形成する領域にダメー
ジか残る。In this conventional manufacturing method for LDD)-transistors, the gate oxide film is also etched during the etch-back process for spacer formation, and ions often directly hit the silicon substrate, leaving damage in the area where the source train will be formed in the future. .
また、Ｎ型の高濃度拡散層の形成のためのイオン注入時
にアモルファス化したソース・ドレイン領域の再結晶化
及び、注入したヒ素の活性化をすべく、９００℃程度の
熱処理を行うと、スペーサのエツジ部直下のアモルファ
ス化した層はその層の下部の単結晶シリコン層を核にし
て同相エピタキシャル成長する。しかしその際、スペー
サ直下のアモルファス化した層は、スペーサにより強く
固定されている為、再結晶化の際に応力を受は結晶欠陥
２１４が発生し易い。In addition, heat treatment at approximately 900°C is performed to recrystallize the source/drain regions that became amorphous during ion implantation to form an N-type high concentration diffusion layer and to activate the implanted arsenic. The amorphous layer immediately below the edge of the layer grows in-phase epitaxially using the single crystal silicon layer below the layer as a nucleus. However, at this time, since the amorphous layer directly under the spacer is strongly fixed by the spacer, crystal defects 214 are likely to occur when it receives stress during recrystallization.
以上二つの理由により、接合漏れ電流が増加するという
問題があった。Due to the above two reasons, there is a problem in that the junction leakage current increases.
本願箱１の発明のＭＩＳ型電界効果トランジスタの製造
方法は、第１導電型半導体基板上にゲート絶縁膜を形成
し、該ゲート絶縁膜上にゲート電極を形成した後、該ゲ
ート電極をマスクにイオン注入を行ない前記半導体基板
と逆導電型の低濃度拡散層を形成する工程と、前記半導
体基板上に一様に多結晶シリコン膜、絶縁膜の順に被着
する工程と、該絶縁膜を異方性エツチングにより、前記
ゲート電極の側壁にのみ残す工程と、該側壁にのみ残し
た絶縁膜をマスクに前記多結晶シリコン膜を等方性エツ
チングし、前記絶縁膜と前記ゲート電極側壁との間にの
み残す工程と、前記ゲート電極、多結晶シリコン膜及び
絶縁膜をマスクにイオン注入を行ない前記低濃度拡散層
と同導電型の高濃度拡散層を形成する工程と所定温度で
アニールする工程とを有している。The method for manufacturing an MIS field effect transistor according to the invention in Box 1 includes forming a gate insulating film on a first conductivity type semiconductor substrate, forming a gate electrode on the gate insulating film, and then using the gate electrode as a mask. A step of performing ion implantation to form a low concentration diffusion layer of a conductivity type opposite to that of the semiconductor substrate, a step of uniformly depositing a polycrystalline silicon film and an insulating film on the semiconductor substrate in that order, and a step of depositing the insulating film in a different manner. A step of isotropically etching the polycrystalline silicon film to leave it only on the sidewalls of the gate electrode, and isotropically etching the polycrystalline silicon film using the insulating film left only on the sidewalls as a mask to remove the etching between the insulating film and the sidewalls of the gate electrode. a step of performing ion implantation using the gate electrode, polycrystalline silicon film, and insulating film as a mask to form a high concentration diffusion layer of the same conductivity type as the low concentration diffusion layer; and a step of annealing at a predetermined temperature. have.
又、本願箱２の発明のＭＩＳ型電界効果トランジスタの
製造方法は、第１導電型半導体基板上にゲート絶縁膜を
形成し、ゲート絶縁膜上にゲート電極を形成した後、該
ゲート電極をマスクにイオン注入を行ない前記半導体基
板と逆導電型の低濃度拡散層を形成する工程と、前記半
導体基板上に一様に多結晶シリコン膜、絶縁膜の順に被
着する工程と、該絶縁膜を異方性エツチングにより、前
記ゲート電極の側壁にのみ残す工程と、前記ゲート電極
及び絶縁膜をマスクにイオン注入を行ない前記低濃度拡
散層と同導電型の高濃度拡散層を形成する工程と、前記
側壁にのみ残した絶縁膜をマスクに、前記多結晶シリコ
ン膜を等方性エツチングし、前記絶縁膜と前記ゲート電
極側壁との間にのみ残す工程と、所定温度でアニールす
る工程とを有している。Further, in the method for manufacturing an MIS field effect transistor according to the invention of Application Box 2, a gate insulating film is formed on a first conductivity type semiconductor substrate, a gate electrode is formed on the gate insulating film, and then the gate electrode is masked. a step of performing ion implantation to form a low concentration diffusion layer of a conductivity type opposite to that of the semiconductor substrate; a step of uniformly depositing a polycrystalline silicon film and an insulating film on the semiconductor substrate in that order; and a step of uniformly depositing the insulating film on the semiconductor substrate. a step of leaving only on the side walls of the gate electrode by anisotropic etching; a step of performing ion implantation using the gate electrode and the insulating film as a mask to form a high concentration diffusion layer of the same conductivity type as the low concentration diffusion layer; The polycrystalline silicon film is isotropically etched using the insulating film left only on the side walls as a mask, and the polycrystalline silicon film is left only between the insulating film and the side wall of the gate electrode. The method includes annealing at a predetermined temperature. are doing.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｅ）は本願節１の発明の一実施例のＬ
ＤＤ構造ＭＯ３型電界効果トランジスタの製造方法を説
明するための工程順断面図である。FIGS. 1(a) to (e) are L of an embodiment of the invention of Section 1 of the present application.
FIG. 3 is a step-by-step cross-sectional view for explaining a method of manufacturing a DD structure MO3 field effect transistor.
まず第１図（ａ＞に示すようにＰ型シリコン基板１０１
上に、Ｌ ＯＣＯＳ法により厚さ６００ｎｍのフィール
ド酸化膜１０２を形成して区画した素子領域のシリコン
表面を９００ ’Ｃで酸化し、厚さ２０ｎｍのゲート酸
化膜１０３を形成する。First, as shown in FIG. 1 (a), a P-type silicon substrate 101
A field oxide film 102 with a thickness of 600 nm is formed thereon by the LOCOS method, and the silicon surface of the divided device region is oxidized at 900'C to form a gate oxide film 103 with a thickness of 20 nm.
その後、フォトエツチング法により多結晶シリコンのゲ
ート電極１０４（厚さ３００ｎｍ）のパターニングを行
い、このゲート電ｉ ］、 ０４及びフィールド酸化膜
１０２をマスクにして、セルファライン法によりリン（
３１ｐ＋）をイオン注入しくエネルギー：４０ｋｅＶ、
ドーズ量：３×１０１３ｃ ｍ−２） 、Ｎ型の低濃度
拡散層１０５１．１０５−２を形成する。Thereafter, a polycrystalline silicon gate electrode 104 (thickness: 300 nm) is patterned by a photoetching method, and phosphorus (
31p+) ion implantation energy: 40 keV,
Dose amount: 3×10 13 cm −2 ), an N-type low concentration diffusion layer 1051.105-2 is formed.
次に第１図（ｂ）に示すように、ＣＶＤ法により、多結
晶シリコン膜１０６（厚さ５０ｎｍ）。Next, as shown in FIG. 1(b), a polycrystalline silicon film 106 (thickness: 50 nm) is formed by CVD.
酸化シリコン膜１０７（厚さ２００ｎｍ）を順次成長す
る。A silicon oxide film 107 (200 nm thick) is sequentially grown.
その後第１図（ｃ）に示すように、異方性エツチング（
ＲＩＥ）により、酸化シリコン膜をエッチバックし、ゲ
ート電極１０４の側壁にスペーサ絶縁膜１０８を形成す
る。この時のエッチバックにおいてエツチングガスとし
て、ＣＨＦ３＋８２を用いれば、酸化シリコン膜と多結
晶シリコン膜との選択比は５：１以上とれる為、スペー
サ絶縁膜１０８を形成する際に、基板を直接たなくこと
かなく、ダメージは全くない。After that, as shown in FIG. 1(c), anisotropic etching (
The silicon oxide film is etched back by RIE) to form a spacer insulating film 108 on the sidewalls of the gate electrode 104. If CHF3+82 is used as the etching gas in this etch-back, the selectivity ratio between the silicon oxide film and the polycrystalline silicon film is 5:1 or more, so when forming the spacer insulating film 108, the substrate is not directly etched. There is no damage at all.
次に第１図（ｄ）に示すように多結晶シリコン膜を弗酸
及び硝酸を含むエツチング液でエツチングし、スペーサ
シリコン膜１０９を形成する。この時、等方性エツチン
グの為に多結晶シリコン膜はスペーサ絶縁膜１０８のエ
ツジより０．１μｍ程度、サイドエッチされる。その後
、ヒ素（７５Ａｓ＋）をイオン注入しくエネルギー７０
ｋ ｅ Ｖ 、 ドーズ量５ Ｘ １０１５ｃ ｍ−
２） 、少なくとも８００°Ｃ１好ましくは９００°Ｃ
１１０分程度のアニールを行いＮ型の高濃度拡散層１１
０−１゜１１０−２を形成する。この時イオン注入によ
りアモルファス化したシリコンか再結晶するが、スペー
サシリコン膜１０９がスペーサ絶縁膜１０８のエツジよ
り０．１μｍ内側にくるので、スペーサ絶縁膜］０８と
アモルファス化したシリコン層との間にすき間ができる
為、応力を受けることを回避てき、結晶欠陥の発生を防
ぐことができる。Next, as shown in FIG. 1(d), the polycrystalline silicon film is etched with an etching solution containing hydrofluoric acid and nitric acid to form a spacer silicon film 109. At this time, the polycrystalline silicon film is side-etched by about 0.1 μm from the edge of the spacer insulating film 108 due to isotropic etching. After that, arsenic (75As+) is ion-implanted with an energy of 70
k e V, dose amount 5 x 1015 cm-
2) at least 800°C, preferably 900°C
Annealing is performed for about 110 minutes to form an N-type high concentration diffusion layer 11.
0-1°110-2 is formed. At this time, the silicon made amorphous by the ion implantation recrystallizes, but since the spacer silicon film 109 is located 0.1 μm inside the edge of the spacer insulating film 108, there is a gap between the spacer insulating film 08 and the amorphous silicon layer. Since there are gaps, stress can be avoided and crystal defects can be prevented from occurring.
次に、第１図（ｅ）に示すように、従来法により、層間
絶縁膜１１１を形成し、コンタクト穴を形成し、Ａｆｆ
ｌ配線１１２−１，１１２−２をパターニングすれば、
ＬＤＤ構造ＭＯ３型電界効果トランジスタが完成する。Next, as shown in FIG. 1(e), by a conventional method, an interlayer insulating film 111 is formed, a contact hole is formed, and an Aff.
If the l wirings 112-1 and 112-2 are patterned,
The LDD structure MO3 field effect transistor is completed.
尚、本実施例ではゲート電極として多結晶シリコン層を
用いたが高融点金属及び高融点金属のシリサイド膜を用
いてもよい。また、Ｐ型シリコン基板をＮ型シリコン基
板として、Ｐ型電界効果トランジスタを形成してもよい
。また、アニールを９００℃で行ったが、８００℃以上
であれば、充分再結晶化されることが一般に知られてい
る。In this embodiment, a polycrystalline silicon layer is used as the gate electrode, but a refractory metal or a silicide film of a refractory metal may also be used. Furthermore, a P-type field effect transistor may be formed by using an N-type silicon substrate instead of a P-type silicon substrate. Further, although annealing was performed at 900°C, it is generally known that sufficient recrystallization can be achieved at temperatures above 800°C.
次に、本願節２の発明の一実施例について説明する。Next, an embodiment of the invention of Section 2 of the present application will be described.
先に説明した実施例と同様の工程を経て酸化シリコン膜
のスペーサ絶縁膜１０８を形成した後（第１図（Ｃ））
多結晶シリコン層１０６（膜厚３０ｎｍ）をエツチング
する前に、ヒ素（７１ＡＳツをイオン注入（エネルギー
＋１５０ｋｅＶ、 ドーズ量： ５ Ｘ １０１５ｃ
ｍ−２）する。ここで多結晶シリコン１−０６膜厚を３
０ｎｍ、注入エネルギーを１５０ｋｅＶにしたのは多結
晶シリコン層１０６を通して注入するためである。その
後多結晶シリコン膜を弗酸及び硝酸を含むエツチング液
でエツチングし、スペーサシリコン膜１０９を形成した
後、９００℃、１０分程度のアニールを行う。After forming the spacer insulating film 108 of silicon oxide film through the same process as in the previously described embodiment (FIG. 1(C))
Before etching the polycrystalline silicon layer 106 (thickness: 30 nm), arsenic (71AS) was ion-implanted (energy +150 keV, dose: 5 x 1015c).
m-2). Here, the polycrystalline silicon 1-06 film thickness is 3
The reason why the thickness was 0 nm and the implantation energy was 150 keV was because the implantation was performed through the polycrystalline silicon layer 106. Thereafter, the polycrystalline silicon film is etched with an etching solution containing hydrofluoric acid and nitric acid to form a spacer silicon film 109, followed by annealing at 900° C. for about 10 minutes.
この実施例では、基板表面を一様に覆った多結晶シリコ
ン膜（導電層）を通して、ヒ素（７１Ａｓツのイオン注
入を行うので、注入時のチャージアップによるゲート酸
化膜の劣化、破壊を軽減できる利点がある。In this example, arsenic (71As) ions are implanted through a polycrystalline silicon film (conductive layer) that uniformly covers the substrate surface, so deterioration and destruction of the gate oxide film due to charge-up during implantation can be reduced. There are advantages.
以上説明したように本願第１．第２の発明は、スペーサ
として多結晶シリコン膜と絶縁膜の二種類で形成してお
り、スペーサ形成方法としてます絶縁膜を異方性エツチ
ングしてスペーサ絶縁膜を形成したのち、その下層の多
結晶シリコン膜をスペーサ絶縁膜をマスクにして等方性
エツチングをしサイドエッチさせることで、絶縁膜のエ
ッチバック時に基板表面のシリコン層を直接たたかない
こと及び高濃度拡散層の形成のためのイオン注入によっ
て生じた基板表面のアモルファス化したシリコン層の再
結晶化時にスペーサの応力による影響を受けない為、結
晶欠陥の発生を防止できることにより、接合漏れ電流を
低減できるという効果を有している。また、本願第２の
発明は、前述の多結晶シリコン膜のエツチング前に高濃
度拡散層を形成するためのイオン注入を行なうので、ゲ
ート絶縁膜の破壊を防止できる効果も有している。As explained above, the first part of the present application. In the second invention, the spacer is formed using two types of films, a polycrystalline silicon film and an insulating film, and the method for forming the spacer is to form a spacer insulating film by anisotropically etching the insulating film, and then to form a polycrystalline silicon film and an insulating film. By performing isotropic etching and side etching of the crystalline silicon film using the spacer insulating film as a mask, it is possible to avoid directly hitting the silicon layer on the substrate surface when etching back the insulating film, and to form a highly concentrated diffusion layer. Since it is not affected by the stress of the spacer during recrystallization of the amorphous silicon layer on the substrate surface caused by ion implantation, it has the effect of reducing junction leakage current by preventing the occurrence of crystal defects. . Further, the second invention of the present application has the effect of preventing destruction of the gate insulating film because ion implantation is performed to form a high concentration diffusion layer before etching the polycrystalline silicon film described above.
第１図（ａ）〜（ｅ）は本願第１の発明及び第２の発明
それぞれの一実施例を説明するための工程順断面図、第
２図（ａ）、（ｂ）は従来例を説明するための工程順断
面図である。FIGS. 1(a) to (e) are cross-sectional views in order of steps for explaining one embodiment of the first invention and the second invention of the present application, and FIGS. 2(a) and (b) are sectional views of the conventional example. FIG. 3 is a step-by-step sectional view for explaining the process.
１０１．２０１・Ｐ型シリコン基板、１０２゜２０２・
・フィールド酸化膜、１０３，２０３・・・ゲート酸化
膜、１０４，２０４・・・ゲート電極、１．０５−１，
１０５−２，２０５−１，２０５−２・・・Ｎ型の低濃
度拡散層、１０６・・・多結晶シリコン層、１０７・・
・酸化シリコン膜、］−０８・スペーサ絶縁膜、１０９
・・スペーサシリコン膜、１１０１．１１０〜２，２１
０−１，２１０−２・・・Ｎ型の高濃度拡散層、１１１
・・・層間酸化膜、１１２］、、１１２−２・・・Ａｆ
ｆｌ配線、２１３・・・スペーサ、２１４・・・結晶欠
陥。101.201・P-type silicon substrate, 102°202・
・Field oxide film, 103,203...Gate oxide film, 104,204...Gate electrode, 1.05-1,
105-2, 205-1, 205-2... N-type low concentration diffusion layer, 106... Polycrystalline silicon layer, 107...
・Silicon oxide film, ]-08 ・Spacer insulating film, 109
...Spacer silicon film, 1101.110-2,21
0-1, 210-2... N-type high concentration diffusion layer, 111
... interlayer oxide film, 112], 112-2...Af
fl wiring, 213... spacer, 214... crystal defect.
Claims (1)
該ゲート絶縁膜上にゲート電極を形成した後、該ゲート
電極をマスクにイオン注入を行ない前記半導体基板と逆
導電型の低濃度拡散層を形成する工程と、前記半導体基
板上に一様に多結晶シリコン膜、絶縁膜の順に被着する
工程と、該絶縁膜を異方性エッチングにより、前記ゲー
ト電極の側壁にのみ残す工程と、該側壁にのみ残した絶
縁膜をマスクに前記多結晶シリコン膜を等方性エッチン
グし、前記絶縁膜と前記ゲート電極側壁との間にのみ残
す工程と、前記ゲート電極、多結晶シリコン膜及び絶縁
膜をマスクにイオン注入を行ない前記低濃度拡散層と同
導電型の高濃度拡散層を形成する工程と所定温度でアニ
ールする工程とを有することを特徴とするＭＩＳ型トラ
ンジスタの製造方法。 ２、第１導電型半導体基板上にゲート絶縁膜を形成し、
ゲート絶縁膜上にゲート電極を形成した後、該ゲート電
極をマスクにイオン注入を行ない前記半導体基板と逆導
電型の低濃度拡散層を形成する工程と、前記半導体基板
上に一様に多結晶シリコン膜、絶縁膜の順に被着する工
程と、該絶縁膜を異方性エッチングにより、前記ゲート
電極の側壁にのみ残す工程と、前記ゲート電極及び絶縁
膜をマスクにイオン注入を行ない前記低濃度拡散層と同
導電型の高濃度拡散層を形成する工程と、前記側壁にの
み残した絶縁膜をマスクに、前記多結晶シリコン膜を等
方性エッチングし、前記絶縁膜と前記ゲート電極側壁と
の間にのみ残す工程と、所定温度でアニールする工程と
を有することを特徴とするＭＩＳ型トランジスタの製造
方法。[Claims] 1. Forming a gate insulating film on a first conductivity type semiconductor substrate,
After forming a gate electrode on the gate insulating film, ion implantation is performed using the gate electrode as a mask to form a low concentration diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and A step of depositing a crystalline silicon film and an insulating film in this order, a step of leaving the insulating film only on the side walls of the gate electrode by anisotropic etching, and a step of depositing the polycrystalline silicon film using the insulating film left only on the side walls as a mask. A step of isotropically etching the film to leave only a portion between the insulating film and the side wall of the gate electrode, and ion implantation using the gate electrode, polycrystalline silicon film, and insulating film as a mask to form the same layer as the low concentration diffusion layer. A method for manufacturing an MIS type transistor, comprising the steps of forming a conductive type high concentration diffusion layer and annealing at a predetermined temperature. 2. Forming a gate insulating film on the first conductivity type semiconductor substrate,
After forming a gate electrode on the gate insulating film, ion implantation is performed using the gate electrode as a mask to form a low concentration diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and a polycrystalline layer is uniformly formed on the semiconductor substrate. a step of depositing a silicon film and an insulating film in this order; a step of leaving the insulating film only on the side walls of the gate electrode by anisotropic etching; and ion implantation using the gate electrode and the insulating film as a mask to remove the low concentration. A process of forming a highly concentrated diffusion layer of the same conductivity type as the diffusion layer, and isotropic etching of the polycrystalline silicon film using the insulating film left only on the sidewalls as a mask, and etching the insulating film and the sidewalls of the gate electrode. 1. A method for manufacturing an MIS transistor, comprising: a step of leaving only a part of the wafer in between, and a step of annealing at a predetermined temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21881390A JPH04101432A (en) | 1990-08-20 | 1990-08-20 | Manufacture of mis-type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21881390A JPH04101432A (en) | 1990-08-20 | 1990-08-20 | Manufacture of mis-type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04101432A true JPH04101432A (en) | 1992-04-02 |
Family
ID=16725747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21881390A Pending JPH04101432A (en) | 1990-08-20 | 1990-08-20 | Manufacture of mis-type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04101432A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869872A (en) * | 1995-07-10 | 1999-02-09 | Nippondenso Co., Ltd. | Semiconductor integrated circuit device and manufacturing method for the same |
| US7238965B2 (en) | 2003-04-17 | 2007-07-03 | Samsung Sdi Co., Ltd. | Thin film transistor and method for fabricating the same with step formed at certain layer |
-
1990
- 1990-08-20 JP JP21881390A patent/JPH04101432A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869872A (en) * | 1995-07-10 | 1999-02-09 | Nippondenso Co., Ltd. | Semiconductor integrated circuit device and manufacturing method for the same |
| US7238965B2 (en) | 2003-04-17 | 2007-07-03 | Samsung Sdi Co., Ltd. | Thin film transistor and method for fabricating the same with step formed at certain layer |
| US7674659B2 (en) | 2003-04-17 | 2010-03-09 | Samsung Mobile Display Co., Ltd. | Method for fabricating a thin film transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05109737A (en) | Manufacture of thin film transistor | |
| JPH0355984B2 (en) | ||
| JPH0212836A (en) | Manufacture of semiconductor device | |
| JPS6252963A (en) | Manufacture of bipolar transistor | |
| JPH0513426A (en) | Semiconductor device | |
| JP2571004B2 (en) | Thin film transistor | |
| JPH04101432A (en) | Manufacture of mis-type transistor | |
| JPH04277617A (en) | Manufacture of semiconductor device | |
| JPS6197967A (en) | Semiconductor device and manufacture thereof | |
| JPH0750418A (en) | Manufacturing method of semiconductor device | |
| JP3088556B2 (en) | Semiconductor device manufacturing method | |
| JPS6247151A (en) | Formation of mutual connection on substrate | |
| JP2856603B2 (en) | Method for manufacturing semiconductor device | |
| JPS6238869B2 (en) | ||
| KR100265824B1 (en) | Method for fabricating transistor of ldd structure | |
| JP2513312B2 (en) | Method for manufacturing MOS transistor | |
| JPH04165629A (en) | Mos semiconductor device | |
| JPH067557B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPH0637103A (en) | Bipolar transistor and its manufacture | |
| JPH0475349A (en) | Manufacture of semiconductor device | |
| JPS61248461A (en) | Manufacture of stacked cmos fet | |
| JPH06188259A (en) | Manufacture of semiconductor device | |
| JPS61251164A (en) | Manufacture of bi-mis integrated circuit | |
| JPH0582071B2 (en) | ||
| JPS5834951B2 (en) | Manufacturing method of semiconductor device |