JP5685633B2 - Display device - Google Patents

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JP5685633B2
JP5685633B2 JP2013210800A JP2013210800A JP5685633B2 JP 5685633 B2 JP5685633 B2 JP 5685633B2 JP 2013210800 A JP2013210800 A JP 2013210800A JP 2013210800 A JP2013210800 A JP 2013210800A JP 5685633 B2 JP5685633 B2 JP 5685633B2
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film
conductive layer
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insulating film
layer
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JP2014038352A (en
JP2014038352A5 (en
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荒尾 達也
達也 荒尾
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株式会社半導体エネルギー研究所
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Description

The present invention relates to a transistor formed on an insulator, particularly a field effect transistor, typically a MOS (Metal Oxide Semiconductor) transistor or a thin film transistor (Thin Film).
A liquid crystal display device using a semiconductor device such as a transistor (hereinafter referred to as a TFT) as a switching element of a pixel portion, a liquid crystal display device including a driver circuit formed from the semiconductor device, and the liquid crystal display device as a display portion It relates to the electric appliance used.

2. Description of the Related Art Liquid crystal display devices in which liquid crystal is sandwiched between a pair of substrates and an electric field is applied between the pair of substrates and display is performed by alignment of the liquid crystals are actively used as monitors for personal computers and television display devices. I came.

Furthermore, a liquid crystal display device in which a drive circuit is built on a single substrate has been realized by improving the crystallization technique of a semiconductor film.

By the way, a high field effect mobility is required for the TFT of the driving circuit, but a characteristic of low leakage current is required for the TFT used as a switching element in each pixel of the pixel portion. It is important to hold the electric charge (signal), and a leak current that occurs even during the holding time in which the TFT is turned off causes a decrease in image quality and a decrease in contrast.

However, the TFT has a problem that when the semiconductor layer is irradiated with light, photoexcitation occurs and a light leakage current is generated. Therefore, a light shielding film that covers the TFT is formed so that light is not applied to the semiconductor layer by sufficiently shielding the light, and even if a leak current is generated, the signal can be retained for one frame period. It was important to secure capacity.

Therefore, in Japanese Patent No. 2924506, as a structure capable of forming a storage capacitor and blocking light leakage, an interlayer film is formed after forming the source electrode and the drain electrode, and a light shielding film made of aluminum is formed on the interlayer film. And forming an anodic oxide film made of Al 2 O 3 on the top and side surfaces of the light shielding film, forming a transparent pixel electrode thereon, and forming the light shielding film / Al
A pixel structure having a storage capacitor composed of 2 O 3 film / transparent pixel electrode is disclosed.

The capacitance of the storage capacitor element (hereinafter referred to as “capacitance”) is inversely proportional to the thickness of the capacitor insulating film (referred to herein as a dielectric film sandwiched between electrodes made of a pair of conductors) and is capacitively insulated. It is proportional to the dielectric constant of the film and the surface area of the electrode. Therefore, in the structure of the above-mentioned Japanese Patent No. 2924506, since the capacitive insulating film between the light shielding film and the transparent pixel electrode is made of an anodic oxide film and is almost constant, there is almost no region where the light shielding film and the transparent pixel electrode overlap. It can function as a storage capacitor element.

However, the liquid crystal display device has a problem in that a display defect is caused by a liquid crystal alignment defect.
The alignment failure of the liquid crystal is caused by the step or unevenness on the surface of the pixel electrode, and the unevenness of the alignment film is caused by this step or unevenness. It will cause. In the structure of the above-mentioned Japanese Patent No. 2924506, as shown in FIG. 1A, the step of the pixel electrode is outside the region shielded by the light-shielding film (the region where light is transmitted), resulting in poor alignment of the liquid crystal. There was a problem such as light loss.

However, in a display device composed of a stack of a large number of layers, a step or unevenness is inevitably generated on the surface of the pixel electrode, and the step or unevenness also affects the surface of the alignment film, resulting in a decrease in contrast due to exposure to light. . Therefore, a method of flattening the step or unevenness of the pixel electrode in the pixel electrode, particularly in a region where light is transmitted and contributes to the display of the pixel has been considered.

Therefore, a method of forming a pixel electrode by forming a light shielding film on the element substrate side and flattening a step generated by the formation is considered. However, in this method, when a storage capacitor element is formed between the light shielding film and the pixel electrode, the interlayer distance between the light shielding film and the pixel electrode is increased as shown in FIG. There is a problem that a region functioning as an element is narrowed, and a sufficient storage capacity cannot be secured.

A slight off-leakage current that flows while the TFT is turned off causes a decrease in contrast and non-uniform image quality as a panel. In order to compensate for this, a storage capacitor element must be formed. However, when the storage capacitor element is formed in another region, for example, as shown in FIG. 1C, the active layer of the TFT is extended to extend from the semiconductor layer, the gate insulating film, and the conductive layer on the gate insulating film. When the storage capacitor element is formed, the aperture ratio of the pixel is reduced, and the display performance is deteriorated in terms of brightness.

In view of the problems as described above, it is an object to realize a semiconductor device having a capacitor element that can flatten a pixel electrode in order to suppress alignment defects of liquid crystal and obtain a sufficient storage capacity without reducing an aperture ratio. To do.

The present invention is a semiconductor device having a thin film transistor and a storage capacitor element, wherein the light shielding film on the thin film transistor, the capacitive insulating film on the light shielding film, the conductive layer on the capacitive insulating film, and the insulating film on the conductive layer, A semiconductor device having a pixel electrode on an insulating film, wherein the conductive layer and the pixel electrode are electrically connected, and the storage capacitor element includes the light shielding film, the capacitive insulating film, and the conductive layer. It is characterized by becoming.

The present invention also includes a light shielding film on a thin film transistor, a capacitive insulating film on the light shielding film, a conductive layer on the capacitive insulating film, an insulating film on the conductive layer, and a pixel electrode on the insulating film, and the holding The capacitive element includes the light shielding film, the capacitive insulating film, and the conductive layer, and the conductive layer and the pixel electrode are in contact with each other through an aperture provided in the insulating film. It is characterized by being formed on the light shielding film.

The present invention is also a semiconductor device having a thin film transistor and a storage capacitor element, wherein the light shielding film on the thin film transistor, the capacitive insulating film on the light shielding film, the conductive layer on the capacitive insulating film, and the insulating film on the conductive layer And the pixel electrode on the insulating film, wherein the storage capacitor element includes the light shielding film, the capacitor insulating film, and the conductive layer, and the conductive layer and the conductive layer through an opening provided in the insulating film. The pixel electrode is in contact with the insulating film, and the step of the pixel electrode due to the capacitive insulating film and the conductive layer is flattened. The inner wall of the opening and the step are on the light shielding film. It is characterized by being.

The present invention is also a semiconductor device having a thin film transistor and a storage capacitor element, wherein the light shielding film on the thin film transistor, the capacitive insulating film on the light shielding film, the conductive layer on the capacitive insulating film, and the insulating film on the conductive layer The pixel electrode on the insulating film, and the storage capacitor element includes the light-shielding film, the capacitor insulating film, and the conductive layer, and the conductive layer and the pixel at an opening provided in the insulating film. The electrode is in contact with the electrode, and a step between a pixel electrode and a pixel electrode adjacent to the pixel electrode is planarized with an insulating film.

The present invention is also a semiconductor device having a thin film transistor and a storage capacitor element, wherein the light shielding film on the thin film transistor, the capacitive insulating film on the light shielding film, the conductive layer on the capacitive insulating film, and the insulating film on the conductive layer And the pixel electrode on the insulating film, wherein the storage capacitor element includes the light shielding film, the capacitor insulating film, and the conductive layer, and the conductive layer and the pixel at an opening provided in the insulating film. The conductive layer and the pixel electrode are in contact with an electrode, and end faces are aligned between adjacent pixels.

The present invention is also a semiconductor device having a thin film transistor and a storage capacitor element, wherein the light shielding film on the thin film transistor, the capacitive insulating film on the light shielding film, the conductive layer on the capacitive insulating film, and the insulating film on the conductive layer And the pixel electrode on the insulating film, wherein the storage capacitor element includes the light shielding film, the capacitor insulating film, and the conductive layer, and the conductive layer and the pixel at an opening provided in the insulating film. The capacitor insulating film, the conductive layer, and the pixel electrode are in contact with an electrode, are formed independently in each pixel, and end faces between adjacent pixels are aligned. .

The conductive layer formed on the capacitor insulating film is electrically connected so as to have the same potential as the pixel electrode, and includes a light shielding film, a capacitor insulating film on the light shielding film, and a conductive layer on the capacitor insulating film. By applying a storage capacitor element made of the above, a sufficient storage capacitor can be obtained without reducing the aperture ratio.

In addition, a planarizing film made of an insulating film is formed on the conductive layer in order to prevent a liquid crystal alignment failure due to a step or unevenness on the surface of the pixel electrode in a region where light is transmitted (region contributing to display).
By forming this flat film, the step of the pixel electrode is formed on the light-shielding film, so that even if alignment film rubbing processing becomes uneven and alignment defects occur, display is not affected. It has become.

Note that in the present invention, a liquid crystal display device in which a liquid crystal is sandwiched between a pair of substrates and a thin film transistor is used as a switching element of each pixel and a connector such as an FPC or TAB is connected to a driving circuit. A liquid crystal display device in which a unit and a drive circuit are integrally formed (hereinafter referred to as an integrally formed liquid crystal display device), and a controller having a function for driving a drive circuit in the integrally formed liquid crystal display device and displaying an image on a pixel portion The present invention can be applied to all liquid crystal display devices having a connected liquid crystal display device and a microcomputer for controlling the controller. In this specification, all these liquid crystal display devices are also referred to as semiconductor devices.

As disclosed in the present invention, by forming a capacitive insulating film on a light shielding film, a conductive layer on the capacitive insulating film, and electrically connecting the conductive layer and the pixel electrode to have the same potential, The entire region where the light shielding film and the pixel electrode overlap can be effectively used as the storage capacitor element. Further, by using the present invention, a storage capacitor element having a sufficient capacity can be formed without reducing the aperture ratio of the pixel.

Note that in the present invention, regardless of the shape of the TFT, a capacitor wiring is formed over a light-shielding film made of a conductive material for shielding the TFT, a conductive layer is formed over the capacitor wiring, and a potential is applied from the pixel electrode to the conductive layer. Is effective because it can function as a storage capacitor element.

FIG. 6 illustrates a conventional storage capacitor element. 4A and 4B illustrate a region functioning as a storage capacitor element of the present invention. The figure explaining the area | region which functions as the conventional storage capacitor | condenser element. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of an electric appliance. The figure which shows an example of an electric appliance. The figure which shows an example of an electric appliance.

  In this embodiment mode, a structure of a pixel portion of a semiconductor device of the present invention will be described.

A structure of a semiconductor device of the present invention is shown in FIG. A TFT 11 is formed on the substrate 10. The TFT includes a semiconductor layer 12 having at least a channel formation region and a source region or a drain region, a gate insulating film 13 formed on the semiconductor layer 12, a gate electrode 14 formed on the gate insulating film 13, and each TFT. Source wirings and drain wirings 15a and 15b for electrically connecting the two are formed.

The source wiring 15a and the drain wiring 15b are connected to a region (source region or drain region) in which an impurity element is added to the semiconductor layer 12 at a high concentration.

An interlayer insulating film 16 is formed on the gate electrode 14, the source wiring 15 a and the drain wiring 15 b, and a light shielding film 17 for TFT (particularly a channel formation region) is formed on the interlayer insulating film 16.

A capacitive insulating film 18 is formed on the light shielding film 17. On the capacitive insulating film 18, the conductive layer 1
9 is formed. After forming the conductive layer 19, a planarizing film 20 made of an insulating material is formed, and then a pixel electrode 21 is formed. The conductive layer 19 and the pixel electrode 21 are in contact with each other through a contact hole formed in the planarization film 20 and are formed to have the same potential. As described above, the step (end portion of the light shielding film 17) 22 generated by covering the light shielding film 17 with the insulating film is not on the light transmitting region but on the light shielding film 17. The pixel structure disclosed in the present invention is characterized in that a storage capacitor is formed by a capacitor insulating film 18 on the light shielding film 17 and a conductive layer 19 on the capacitor insulating film 18.

In addition, the liquid crystal alignment disorder due to a step in a light transmitting region is suppressed.

The light shielding film 17 may be formed as a single layer or a stacked layer using an element selected from Al, Ti, W, and Cr or an alloy material containing the element as a main component.

The capacitor insulating film 18 may be formed using a silicon oxide film formed by a CVD method, a sputtering method, or the like, or an inorganic insulating film such as a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film. However, if there is an organic insulating film having the characteristics of a high dielectric constant and a low leakage current, an organic insulating film may be used.

The conductive layer 19 may be formed using an element selected from Al, Ti, and W, an alloy material containing the element as a main component, or ITO. Note that when importance is attached to the light shielding property to the TFT, an element selected from Al, Ti, and W having a high light shielding property or an alloy material containing the element as a main component may be used.

Furthermore, a storage capacitor can be formed by the interlayer insulating film 16 on the drain wiring 15 b and the light shielding film 17 on the interlayer insulating film 16.

The planarizing film 20 made of an insulating film is formed using an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or a solution coating material called SOG (spin on glass). do it. Alternatively, one or more kinds of materials selected from organic insulating films such as acrylic and polyimide may be used.

By providing the conductive layer 19 as in the present invention and making the pixel electrode and the conductive layer have the same potential,
Since the region where the upper light-shielding film and the pixel electrode overlap with each other can be used as a storage capacitor element without waste, the storage capacitor can be increased as compared with the conventional structure shown in FIG.

An actual mask diagram is shown in FIG. 2B as an example of the present invention (14 μm × 14 μm).
For the sake of simplicity, a light-shielding film and a pixel electrode (ITO) are shown in one pixel designed in (1). Here, the upper light-shielding film, capacitive insulating film, and conductive layer (same potential as the pixel electrode)
When the area that functions as the storage capacitor element is calculated, it is 63.645 μm 2 . In the conventional structure without the conductive layer shown in FIG. 1B, even if the upper light shielding film and the pixel electrode overlap with each other, the area actually functioning as the storage capacitor element is considerably narrower than that of the present invention. . In FIG. 3B, a region functioning as a storage capacitor element with a light-shielding film and a pixel electrode (ITO) is shown by a broken line for simplification of one pixel designed as 14 μm × 14 μm as in FIG. 2B. It was. The area that functions as a storage capacitor element in the conventional structure is 34.905 μm 2. Compared with the present invention, the present invention increases the area that functions as a storage capacitor element 1.82 times without reducing the aperture ratio. Can do.

As described above, the step in the light transmission region of the pixel electrode can be eliminated without increasing the number of steps. This prevents the alignment film from being sufficiently rubbed due to the level difference or unevenness of the pixel electrode, so that the phenomenon of light leakage due to disordered alignment of the liquid crystal can be suppressed. Furthermore, the formation of the conductive layer 19 can ensure about twice the capacity without lowering the aperture ratio as compared with the conventional structure in which the conductive layer is not formed. Therefore, the present invention is effective. is there.

  Note that the present invention can be applied without being limited to the TFT shown in this embodiment.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. Note that in this specification, a substrate in which a driving circuit, a switching element (pixel TFT) in a pixel portion, and a storage capacitor are formed over the same substrate is referred to as an active matrix substrate for convenience.

An insulating film is formed on the surface of a substrate made of glass such as barium borosilicate glass or alumino borosilicate glass represented by Corning 7059 glass or 1737 glass, or a quartz substrate, single crystal silicon substrate, metal substrate or stainless steel substrate. What is formed may be used as a substrate. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In this embodiment, a quartz glass substrate is used.

Next, a lower light shielding film 101 is formed on the quartz substrate 100. The lower light-shielding film 101 is formed with a film thickness of about 300 nm by using a conductive material such as Ta, W, Cr, and Mo that can withstand the processing temperature of this embodiment and its laminated structure. Note that the lower light-shielding film 101 also has a function as a gate wiring, and is hereinafter also referred to as a gate line. In this embodiment, a crystalline silicon film having a thickness of 75 nm is formed, and then a WSix (x = 2.0 to 2.8) having a thickness of 150 nm is formed, and then unnecessary portions are etched to form a lower light shielding film. (Gate line) 101 is formed. The lower light shielding film 101
May be a single-layer structure or a structure in which two or more layers of conductive materials as described above are stacked. In addition, an insulating film may be formed before the base light-shielding film 101 is formed in order to prevent diffusion of contaminants from the substrate.

Then, from an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxide film formed at a high temperature of about 800 ° C. using the LPCVD method on the substrate 100 and the lower light shielding film (gate line) 101. A film thickness of 10 to 650 nm (preferably 50 to 600)
nm) of the base insulating film 102. In this embodiment, a single layer structure is used as the base insulating film 102; however, a structure in which two or more insulating films are stacked may be used to prevent contamination. A silicon oxynitride film (composition ratio: Si = 32%, O = 27%, N = 24%, H = 17%) formed by using a plasma CVD method and using SiH 4 , NH 3 , and N 2 O as reaction gases ) May be formed at 400 ° C. to a film thickness of 580 nm.

Next, an amorphous semiconductor film 103 is formed over the base insulating film 102 (FIG. 4A).
). The amorphous semiconductor film 103 is a known means (a sputtering method, a semiconductor film having an amorphous structure).
LPCVD method, plasma CVD method, etc.) 25-80 nm (preferably 30-
60 nm) in thickness. There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Then, a thermal crystallization method using a catalyst such as nickel is performed to crystallize the semiconductor film. In addition to the thermal crystallization method using a catalyst element such as nickel, a known crystallization treatment (laser crystallization method, thermal crystallization method, etc.) may be performed in combination. In this example, a nickel acetate solution (
The catalyst element-containing layer is formed by spin coating on the entire surface of the film by spin coating to form a catalyst element-containing layer, and heat treatment is performed by exposure to a nitrogen atmosphere at a temperature of 600 ° C. for 12 hours.

Further, crystallization may be performed by combining a laser crystallization method with a thermal crystallization method in which a catalyst element is added. When the laser crystallization method is also applied, a pulse oscillation type or continuous oscillation type gas laser or solid state laser may be used. As the gas laser, excimer laser, Ar laser, Kr
There are lasers, etc., and solid-state lasers include YAG laser, YVO 4 laser, YLF laser,
YAlO 3 laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, and the like can be given. In the case of using these lasers, the laser light emitted from the laser oscillator may be condensed into a linear shape, a rectangular shape, or an elliptical shape by an optical system and irradiated onto the semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 800 mJ / c.
m 2 (typically 200 to 700 mJ / cm 2 ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 30.
It may be 0 to 1000 mJ / cm 2 (typically 350 to 800 mJ / cm 2 ). And width 100 ~
A laser beam condensed linearly at 1000 μm, for example, 400 μm may be irradiated over the entire surface of the substrate. In the case of using a YVO 4 laser, a laser beam emitted from a continuous wave YVO 4 laser of 10W output is converted into a harmonic by a nonlinear optical element, a YVO 4 crystal and a non-linear optical element in a resonator And harmonics may be emitted. At this time, irradiation may be performed in a rectangular or elliptical shape by an optical system, and the energy density is about 0.01 to 100 MW / cm 2 (
Preferably, 0.1 to 10 MW / cm 2 ) is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 0.5 to 2000 cm / s.

When a catalytic element is used in the crystallization process of the semiconductor film, subsequently, gettering is performed to reduce the concentration by moving the catalytic element used to promote crystallization from the semiconductor layer serving as the active region. Process. For gettering, a method disclosed in Japanese Patent Laid-Open No. 10-270363 or a chemical oxide film is formed on a crystalline semiconductor film by treatment with ozone water, and a rare gas element is contained on the chemical oxide film. Any method of moving the catalyst element to the gettering site by forming a gettering site and performing heat treatment may be applied. In this embodiment, a silicon oxide film having a thickness of 50 nm is formed as a mask,
Patterning is performed to obtain masks 104a to 104c having desired shapes. Then, an impurity belonging to the group 15 (typically P (phosphorus)) is selectively introduced into the semiconductor film to introduce the impurity region 105.
a to 105d are formed. Note that the impurity element may be introduced by one or a plurality of methods selected from a plasma doping method, an ion implantation method, and an ion shower doping method. Then, by performing the first heat treatment, the catalytic element can be moved from the semiconductor layer serving as the active region to the impurity regions 105a to 105d, and can be reduced to a level that does not affect the semiconductor characteristics. A TFT having an active region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved (FIG. 4B).

Then, the crystalline semiconductor film is etched to form a semiconductor layer. Here, it is preferable to heat-treat the upper portion of the semiconductor layer by heat treatment in order to form an insulating film and improve the crystallinity of the semiconductor film. For example, after forming a 20 nm silicon oxide film with a low pressure CVD apparatus, heat treatment is performed in a furnace annealing furnace. By this treatment, the upper portion of the semiconductor layer is oxidized. Then, the oxidized portions of the silicon oxide film and the semiconductor layer are removed by etching, so that the semiconductor layers 106 to 108 with improved crystallinity can be obtained.

Further, after forming the semiconductor layers 106 to 108, a trace amount of an impurity element (boron or phosphorus) may be introduced in order to control the threshold value of the TFT.

Then, masks 109a to 109c made of resist are formed, a second impurity element is introduced, and an impurity element imparting n-type conductivity is introduced into the semiconductor layer. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. At this time, since the masks 109a to 109c are formed, the impurity is added to the selected region of the semiconductor layer, and the high concentration impurity regions 110 to 112 are formed. Impurity elements imparting n-type (hereinafter referred to as n-type impurity elements) in a concentration range of 1 × 10 18 to 1 × 10 20 / cm 3 are added to the high-concentration impurity regions 110 to 112 (FIG. 4C
)).

Next, a gate insulating film 113 is formed so as to cover the semiconductor layers 106 to 108. The gate insulating film 113 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to a thickness of 35 nm by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

When a silicon oxide film is used, TEOS (Tetraethyl Orth) is formed by plasma CVD.
o Silicate) and O 2 can be mixed to form a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and discharge at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm 2. .
The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Note that the impurity region may be formed by introducing the impurity element after the gate insulating film 113 is formed.

Then, after forming a contact hole for connecting each TFT to the semiconductor layer and a contact hole for connecting the gate electrode and the gate line 101, a conductive film having a heat resistance of 100 to 500 nm is formed. A film is formed. In this embodiment, a 400 nm-thick W film is formed by sputtering using a W target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF 6 ).

The conductive film is not particularly limited to W, but Ta, W, Ti, Mo, Cu, Cr
, Nd, or an alloy material or compound material containing the element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Further, an AgPdCu alloy may be used. Further, although a single layer structure is used in this embodiment, two or more conductive films may be stacked. Alternatively, a three-layer structure in which a conductive film with low heat resistance such as Al is sandwiched between conductive films with high heat resistance may be used.

Next, a resist mask (not shown) is formed using a photolithography method,
An etching process for forming electrodes and wirings is performed. In this example, ICP (Inductively Coupled Plasma) etching method is used as an etching condition,
CF 4 , Cl 2 and O 2 are used as etching gases, and the respective gas flow ratios are 25:25:
Etching was performed by generating plasma by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa at a pressure of 10 (sccm). 150W on the substrate side (sample stage)
RF (13.56 MHz) power is applied and a substantially negative self-bias voltage is applied. Thus, gate electrodes 114 to 116 and wirings 117 to 121 are formed (FIG. 5A).

Next, the first interlayer insulating film 122 covering the electrodes 114 to 116 and the wirings 117 to 121
Form. The first interlayer insulating film 122 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. In this example,
A silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 122 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Note that a semiconductor region containing an impurity element at a low concentration may be formed in the semiconductor layer using a mask as necessary. For example, a selected region of the semiconductor layer is exposed with a mask made of resist, a dose amount is set to 1 × 10 13 to 5 × 10 14 / cm 2 , an acceleration voltage is set to 5 to 80 keV, and n
An element belonging to Group 15 as an impurity element imparting a type, typically phosphorus (P) or arsenic (
As) is added. Thereby, a low concentration impurity region can be formed in a selective region of the semiconductor layer. An impurity element imparting n-type is added to the low concentration impurity region in a concentration range of 1 × 10 18 to 1 × 10 20 / cm 3 .

Next, heat treatment is performed to recover the crystallinity of the semiconductor layer and to activate the impurity element added to each semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace. The thermal annealing method may be performed at 400 to 1000 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed by heat treatment at 950 ° C. for 4 hours. It was. In addition to the thermal annealing method, a laser annealing method using a YAG laser or the like, or a rapid thermal annealing method (RTA method) can be applied. Note that this heat treatment may be performed before the first interlayer insulating film is formed. However, when the wiring material used is vulnerable to heat, it is preferable to perform heat treatment after forming the first interlayer insulating film in order to protect the wiring and the like as in this embodiment.

Further, a hydrogenation treatment is performed by performing a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 122. Of course, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen
The heat treatment may be performed for 1 to 12 hours.

Next, a second interlayer insulating film 123 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 122. The second interlayer insulating film 123 is preferably a film having a flat surface. Also, a known technique for improving the flatness of the surface, for example, a polishing process called CMP (Chemical Mechanical Polishing) may be used. Second interlayer insulating film 1
23, an acrylic resin film having a thickness of 1 μm is formed, and etching is performed to expose a part of the first interlayer insulating film formed on the gate electrode, the source wiring, and the drain wiring. The surface may be planarized by the interlayer insulating film and the second interlayer insulating film.
In this embodiment, the first interlayer insulating film and the second interlayer insulating film are formed, but of course, a single layer structure may be used. Even in this case, it is desirable to use a film having a flat surface.

Note that in order to function as a storage capacitor between the drain wiring 121 and a light shielding film to be formed later, the thickness of the interlayer insulating film is reduced using CMP or the like, and the distance between the light shielding film and the drain wiring is reduced. Just do it.

Then, an upper light shielding film 124 is formed on the second interlayer insulating film 123 by patterning an element selected from Al, Ti, W, and Cr or an alloy material containing the element as a main component into a desired shape. The upper light shielding film 124 is arranged in a mesh shape so as to shield light other than the opening of the pixel. A light shielding film 125 was also formed in the drive circuit.

Subsequently, an insulating film (hereinafter referred to as a capacitive insulating film) made of a silicon nitride oxide film or a silicon oxynitride film is formed on the upper light shielding film to a thickness of about 50 to 100 nm.
When the ratio of nitrogen is high, the dielectric constant of the capacitor insulating film increases, but at the same time, the leakage current also increases. Therefore, by setting the content ratio of nitrogen and oxygen to about 1: 8 to 2: 1, the film thickness 50 -10
A 0 nm capacitive insulating film is formed.

Subsequently, a conductive layer is formed with a thickness of about 100 to 150 nm on the capacitor insulating film. The conductive layer is
An element selected from Al, Ti, and W, an alloy material containing the element as a main component, or ITO may be used. Thereafter, the upper light shielding films 124 and 125, the capacitor insulating films 126 and 127, and the conductive layers 128 and 129 may be formed by etching into a predetermined shape using a known method.
(FIG. 5B).

Subsequently, a film (hereinafter, referred to as a planarization film) 130 is formed using an insulating film such as a silicon oxide film, polyimide, or acrylic so that the pixel electrode in a region where light is transmitted is planarized.
Then, an opening for connecting the pixel electrode and the conductive layer is formed in the planarizing film, and contact holes for connecting the pixel electrode and the drain electrode are further formed in the planarizing film 130 and the interlayer insulating film 122. 123. Subsequently, the pixel electrode 131 is formed. Pixel electrode 13
1 may be formed with a thickness of 100 nm using a transparent conductive film (ITO). As a result, the pixel electrode 131 and the conductive layer 128 have the same potential. In the pixel electrode formation step, the extraction electrode 132 in the driver circuit is formed.

As described above, a storage capacitor element including the upper light shielding film 124, the capacitor insulating film 126, and the conductive layer 128 (the same potential as the pixel electrode 131) is formed (FIG. 6).

By forming the conductive layer 126 over the capacitor insulating film 126 as in the present invention, the area of the region where charge can be stored as the storage capacitor element can be doubled compared to the conventional case.

Subsequently, the conductive layer 126 is etched using the pixel electrode 131 as a mask to cut off the continuity with adjacent pixels and to make each pixel independent.

As described above, an active matrix substrate in which the driving circuit 204 including the NMOS circuit of the n-channel TFTs 201 and 202 and the pixel portion 205 having the pixel TFT 203 are formed on the same substrate is completed.

In the pixel portion, an upper light shielding film 124 for shielding the pixel TFT 203, a capacitor insulating film 126, and a storage capacitor 206 including a conductive layer 128 (the same potential as the pixel electrode 131) are formed.

Since the gate electrode, the source wiring, and the drain wiring are formed in the same process, the active matrix substrate formed in this way can reduce the number of processes compared to the conventional process. Therefore, the yield can be improved and the cost can be reduced. Further, since the physical distance between the upper light-shielding film and the semiconductor film is shortened, it is possible to prevent the occurrence of leakage current due to light leakage or light diffraction. Further, since the source wiring is directly connected to the semiconductor film, the number of contact holes can be minimized and the aperture ratio when the liquid crystal display device is manufactured can be improved.

In this embodiment, a process for manufacturing a semiconductor device having a structure different from that in Embodiment 1 will be described with reference to FIGS.

In accordance with Embodiment 1, a pixel electrode 131 that is electrically connected to the conductive layer 128 is formed over the planarization film 130. Subsequently, as shown in FIG. 7, the light shielding film 124, the capacitor insulating film 126, the conductive layer 128, and the pixel electrode 131 formed on the second interlayer insulating film 123 are formed between adjacent pixels. A large step (50 nm or more) is flattened by an insulating film 401 made of acrylic, polyimide, or the like.
Next, an alignment film 402 is formed. Since the insulating film 401 is planarized by filling a step between adjacent pixels, unevenness is hardly generated on the surface of the alignment film 402. Thereafter, a rubbing process is performed, and the substrate on which the TFT is formed and the counter substrate are bonded to each other using a sealing material (sealing material). Then, an active matrix liquid crystal display device is manufactured by holding liquid crystal in the meantime. Since this cell assembling process may use a known means, a detailed description is omitted.

By forming the insulating film in the concave portion as described above, it is possible to reduce the difference in unevenness on the surface of the active matrix substrate that is formed by laminating various materials on the substrate.
Thereby, in the rubbing process performed after the alignment film is formed, rubbing unevenness can be suppressed to a minimum, and alignment defects of liquid crystal can be made difficult to occur.

In this embodiment, a process for manufacturing a semiconductor device having a structure different from that in Embodiment 1 will be described with reference to FIGS.

In accordance with Embodiment 1, a light shielding film 301, a capacitor insulating film 302, and a conductive layer 303 are formed.
After that, etching is performed so that the conductive layer 303 slightly enters the light shielding film 301 and the capacitor insulating film 302 as indicated by arrows in FIG. Etching using a mask or over etching may be performed. Accordingly, it is possible to prevent the leakage current from being generated due to contact between the light shielding film 301 and the conductive layer 303.

Further, as shown in FIG. 8B, the light shielding film 311, the capacitor insulating film 312, and the conductive layer 313 are formed.
By performing over-etching so that steps are formed in this order or etching using a mask, the stacking can be smoothed, and the steps and unevenness of the pixel electrode 315 formed after the planarization film 314 is formed are further reduced. can do. Note that reference numeral 315a denotes a pixel electrode of an adjacent pixel.

As described above, a liquid crystal display device having a sufficient storage capacity and capable of performing good display can be realized.

The storage capacitor element made of a conductive layer formed so as to have the same potential as the light shielding film, the capacitor insulating film, and the pixel electrode disclosed in the present invention is formed on the light shielding film that shields light other than the TFT as shown in the first embodiment. It may be formed. In this embodiment, an example will be described with reference to FIGS.

An insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 50 (not shown), a conductive film is formed to form a gate electrode, and is patterned into a desired shape. Gate electrodes 51a to 51c are obtained. As the conductive film, an element selected from Ta, Ti, W, Mo, Cr, or Al, or a conductive film containing any element as a main component may be used.
As the substrate, a substrate made of glass such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a single crystal silicon substrate, a metal substrate, a stainless steel substrate with an insulating film formed thereon, Any plastic substrate having heat resistance that can withstand the processing temperature may be used.

Next, gate insulating films 52a and 52b are formed. The gate insulating film is a silicon oxide film,
A single layer of a silicon nitride film or a silicon oxynitride film, or a stacked structure of any film may be used.

Next, an amorphous silicon film 53 is formed as an amorphous semiconductor film by a thermal CVD method, plasma C
It is formed to a thickness of 10 to 1150 nm by VD method, low pressure CVD method, vapor deposition method or sputtering method. Note that since the gate insulating film 52 and the amorphous silicon film 53 can be formed by the same film formation method, both may be continuously formed. By continuous formation, exposure to the atmosphere is no longer required, contamination of the surface can be prevented, and variations in characteristics of TFTs to be manufactured and variations in threshold voltage can be reduced (FIG. 9A).

Next, in order to crystallize the amorphous silicon film 53, a catalyst element that promotes crystallization is applied (formation of the catalyst element-containing layer 54). Thereafter, heat treatment is performed to form a crystalline silicon film (FIG. 9B).

Note that the semiconductor film may be crystallized by a crystallization method using a continuous wave or pulsed gas laser or a solid-state laser in addition to the heat treatment using a catalytic element. Examples of such a gas laser include an excimer laser, an Ar laser, and a Kr laser, and examples of the solid laser include a YAG laser, a YVO 4 laser, a YLF laser, a YAlO 3 laser, a glass laser, a ruby laser, an alexandride laser, and a Ti laser. : Sapphire laser and the like. In order to obtain a crystal having a large grain size in crystallization of the amorphous semiconductor film, it is preferable to apply the second to fourth harmonics of the fundamental wave using a solid-state laser capable of continuous oscillation. . Typically, the second harmonic (wavelength 532 nm) or the third harmonic (wavelength 355 nm) of an Nd: YVO 4 laser (fundamental wave 1064 nm) may be used.

After the crystallization process is completed, an insulating film 55 that protects the crystalline silicon film (channel formation region) is formed to a thickness of 100 to 400 nm in a later impurity addition process. This insulating film is formed in order to prevent the crystalline silicon film from being directly exposed to plasma when the impurity element is added, and to enable fine concentration control.

Next, using a mask made of resist, an impurity element imparting n-type is added to the crystalline silicon film to be an active layer of the later n-channel TFT to add a region containing the n-type impurity element at a high concentration (rear) Source region or drain region) 56, 57. Subsequently, a p-type impurity element is added to the crystalline silicon film to be an active layer of the later p-channel TFT, and a region (later source region or drain region) 58 containing the p-type impurity element at a high concentration is formed. Form. Note that in the n-channel TFT and the p-channel TFT, a region containing an impurity element at a low concentration (LDD region) may be formed (FIG. 9C).

Next, a step of activating the impurity element added to the crystalline silicon film is performed.
Simultaneously with the activation, the catalytic element applied to the silicon film in the crystallization process is also captured (gettering). As heat treatment conditions, treatment may be performed at 450 to 950 ° C. in an atmosphere having an oxygen concentration of 5 ppm.

Next, the insulating film on the crystalline silicon film is removed, and the crystalline silicon film is patterned into a desired shape and etched to obtain semiconductor layers 59 to 61. Subsequently, an interlayer insulating film 62 is formed. The interlayer insulating film 62 is formed to a thickness of 500 to 1500 nm from an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (FIG. 9D).

Thereafter, contact holes reaching the source region or drain region of each TFT are formed, and wirings 63 to 67 for electrically connecting the TFTs are formed. Subsequently, an interlayer insulating film 68 covering the wirings 63 to 67 is formed (FIG. 10A).
).

Next, a light shielding film 69 is formed to shield the TFT from light irradiation. The light shielding film 69 is an element selected from Al, Ti, W, Cr, an alloy material containing the element as a main component, or a film having a high light shielding property such as a black resin with a thickness of about 100 to 200 nm. A film may be formed.

Thereafter, a capacitive insulating film 70 is formed on the light shielding film 69. As the capacitor insulating film 70, either a silicon oxynitride film or a silicon nitride oxide film may be used.
It may be 0 nm.

Subsequently, a conductive layer 71 is formed on the capacitor insulating film 70. For the conductive layer 71, an element selected from Al, Ti, and W or an alloy material containing the element as a main component may be used. A transparent conductive film (for example, ITO) may be used.

Next, a film (flattening film) 72 for flattening a region through which light of the pixel electrode is transmitted is formed using an insulating film. The planarization film 72 is formed by forming a silicon oxide film with a thickness of about 100 to 200 nm and planarizing it using CMP (Chemical Mechanical Polishing).
In addition, planarization may be performed using a thermosetting resin such as polyimide or acrylic.
After the planarization film 72 is formed, a contact hole for connecting the conductive layer 71 and the pixel electrode to the planarization film 72 and a contact hole for electrically connecting the pixel electrode and the wiring 67 serving as the drain electrode are planarized. A pixel electrode 73 is formed on the insulating film 72 and the interlayer insulating film 68. Note that after the pixel electrode 73 is formed, the conductive layer 71 is patterned and etched to break continuity with the conductive layer 71 formed in the adjacent pixel (FIG. 10B).

In this manner, a storage capacitor element including the light shielding film 69, the capacitor insulating film 70, and the conductive layer 71 having the same potential as the pixel electrode 73 is formed. By forming the conductive layer 71, a region where the light shielding film 69 and the pixel electrode 73 overlap can be functioned as a storage capacitor element without waste.

Further, since the step of the pixel electrode 73 is formed on the light shielding film 69 by forming the planarization film 72 as in the present invention, the alignment disorder and light leakage caused by the step and unevenness of the pixel electrode 73 are caused. Can be prevented.

  As described above, the present invention can be applied without depending on the shape of the TFT.

In this embodiment, a semiconductor device obtained by heat-treating a semiconductor layer including a channel formation region, a source region, and a drain region of a thin film transistor at a high temperature in the semiconductor device having the structure shown in Embodiment 1 including a thin film transistor and a storage capacitor element. An example of using a (typically silicon) film (hereinafter referred to as a high-temperature polysilicon film) will be described.

A lower light-shielding film and a base insulating film that also function as gate lines are formed on a quartz substrate substrate having high heat resistance according to the first embodiment. Subsequently, an amorphous semiconductor film is formed on the base insulating film by using a known method such as an LPCVD method, a PCVD method, or a sputtering method.

Next, heat treatment is performed at 600 ° C. for 24 hours using a furnace, so that a crystalline semiconductor film is formed. Note that although a silicon oxide film is formed on the surface of the semiconductor film in this crystallization treatment, there is no problem because it is a very thin film that can be removed by etching or the like.

Next, after removing the oxide film formed on the surface of the crystalline semiconductor film, heat treatment for forming a gate insulating film is performed. The crystalline semiconductor film is heated at 900 to 1050 ° C. to form an oxide film on the surface of the crystalline semiconductor film. This silicon oxide film is used as a gate insulating film. A silicon oxide film may be formed on the surface of the crystalline semiconductor film by heat treatment so that the crystalline semiconductor film finally has a thickness of 30 to 50 nm.

The crystalline semiconductor film thus obtained by the high-temperature heat treatment has high crystallinity and a semiconductor film that can obtain higher field-effect mobility is used for a semiconductor layer including a channel formation region, a source region, and a drain region. Thus, a TFT having excellent characteristics can be realized, and further, a semiconductor device having high reliability can be realized by using this TFT in a circuit.
This embodiment can be used in combination with the first to fourth embodiments.

In this embodiment, in the semiconductor device having the structure shown in Embodiment 1 including the thin film transistor and the storage capacitor element, the semiconductor layer including the channel formation region, the source region, and the drain region of the thin film transistor is obtained by irradiating laser light. An example of manufacturing using the crystalline semiconductor film will be described.

A lower light-shielding film and a base insulating film that also function as gate lines are formed on the substrate in accordance with the first embodiment. Subsequently, an amorphous semiconductor film is formed on the base insulating film by a known method such as an LPCVD method, a PCVD method, or a sputtering method. Note that a substrate made of glass such as barium borosilicate glass typified by Corning 7059 glass or 1737 glass or alumino borosilicate glass is used.
Alternatively, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed on the surface thereof may be used. Further, a plastic substrate having high heat resistance may be used.

Subsequently, the amorphous semiconductor film is irradiated with laser light. As the laser to be used, a continuous wave or pulsed gas laser or solid state laser is used. There are excimer laser, Ar laser, Kr laser, etc. as gas laser, and YAG laser, YVO as solid laser.
4 laser, YLF laser, YAlO 3 laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, and the like.

As a solid-state laser, a laser using a crystal such as YAG, YVO 4 , YLF, or YAlO 3 doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is applied. The fundamental wave of the laser differs depending on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.

In crystallization of the amorphous semiconductor film, in order to obtain a crystal with a large grain size, it is preferable to apply a second to fourth harmonic of the fundamental wave using a solid-state laser capable of continuous oscillation. Typically,
Second harmonic (532 nm) and third harmonic (3) of Nd: YVO 4 laser (fundamental wave 1064 nm)
55 nm) is applied.

Here, as an example, a method for crystallization using a YVO 4 laser will be described. Laser light emitted from a continuous wave YVO 4 laser having an output of 10 W is converted into a harmonic by a non-linear optical element. Alternatively, a YVO 4 crystal and a nonlinear optical element may be placed in the resonator to emit harmonics. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. The energy density at this time is 0.01-1
About 00 MW / cm 2 (preferably 0.1 to 10 MW / cm 2 ) is required. And 0
. Irradiation is performed by moving the semiconductor film relative to the laser beam at a speed of about 5 to 2000 cm / s.

The crystalline semiconductor film obtained by irradiating with laser light in this manner is a semiconductor layer that includes a channel formation region, a source region, and a drain region as a semiconductor film having high crystallinity and higher field effect mobility. Therefore, a TFT having excellent characteristics can be realized, and a semiconductor device having high reliability can be realized by using this TFT in a circuit. This embodiment can be used in combination with the first to fourth embodiments.

Using the present invention, an active matrix liquid crystal display device (liquid crystal display)
Various electric appliances incorporating the display in the display portion can be completed.

Such electric appliances include projectors (rear type or front type), video cameras, digital cameras, head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.)
Etc. Examples of these are shown in FIGS. 11, 12 and 13.

FIG. 11A illustrates a front type projector, which includes a projection device 2601 and a screen 26.
02 etc. are included.

FIG. 11B shows a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like.

Note that FIG. 11C illustrates a projection device 2601 in FIGS. 11A and 11B.
2 is a diagram illustrating an example of a structure 2702. FIG. The projection devices 2601 and 2702 are the light source optical system 2
801, mirrors 2802, 2804 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, phase difference plate 2809, and projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, in the optical path indicated by an arrow in FIG. 11C, the practitioner appropriately uses an optical lens, a film having a polarization function,
You may provide optical systems, such as a film for adjusting a phase difference, and an IR film.

FIG. 11D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811 and a light source 28.
12, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 11D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

According to the present invention, since light applied to the thin film transistor can be shielded by the light-shielding film, generation of light leakage current can be suppressed even by strong light used in the projector, and a capacitor having sufficient storage capacity Since the element is formed, a signal can be held, display unevenness does not occur, and fine and satisfactory display can be performed. Furthermore, since a sufficient capacitance element can be formed without reducing the aperture ratio, the luminance is sufficient and the power consumption of the light source can be reduced.

FIG. 12A illustrates a personal computer, which includes a main body 2001, an image input unit 2002,
A display portion 2003, a keyboard 2004, and the like are included. The liquid crystal display device of the present invention is provided with the display portion 2003
By applying to the above, a personal computer can be completed. FIG. 12B illustrates a mobile computer (mobile computer), which includes a main body 2101, a camera unit 210.
2, an image receiving unit 2103, an operation switch 2104, a display unit 2105, and the like. The mobile computer can be completed by applying the liquid crystal display device of the present invention to the display portion 2105.
FIG. 12C shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 2201, the display portion 2202, the speaker portion 2203, the recording medium 2204,
An operation switch 2205 and the like are included. This player uses DVD (Dig as a recording medium).
(tial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games and the Internet. The liquid crystal display device of the present invention can be applied to the display portion 2402 and a player using a recording medium can be involved.
According to the present invention, these electric appliances can eliminate liquid crystal alignment defects due to steps or irregularities in the light transmission region of the pixel electrode, and can form a capacitive element that can obtain a sufficient storage capacity. Even when current is generated, a display signal can be held, and a fine display without display unevenness can be realized. Furthermore, since a high aperture ratio can be maintained even when a capacitor element is formed, high luminance can be achieved and power consumption of a light source used for display can be reduced. This leads to lower power consumption of the entire electric appliance.

FIG. 12D illustrates a video camera, which includes a main body 2301, a display portion 2302, and an audio input portion 23.
03, an operation switch 2304, a battery 2305, an image receiving unit 2306, and the like. The video camera can be completed by applying the liquid crystal display device of the present invention to the display portion 2302. FIG. 12E illustrates a digital camera, which includes a main body 2401, a display portion 2402, an eyepiece portion 2403,
An operation switch 2404, an image receiving unit (not shown), and the like are included. The liquid crystal display device of the present invention can be applied to the display portion 2402.
FIG. 12D illustrates a goggle type display including a main body 2501, a display portion 2502, an arm portion 2503, and the like. The liquid crystal display device of the present invention can be applied to the display portion 2502.
FIG. 13A shows a mobile phone, 3001 is a display panel, and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected at a connection portion 3003. An angle θ between the surface of the connection unit 3003 on which the display unit 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed.
Furthermore, a voice output unit 3005, operation keys 3006, a power switch 3007, a voice input unit 3
008. The liquid crystal display device of the present invention can be applied to the display portion 3004 to complete a mobile phone. FIG. 13B illustrates a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, an antenna 3106, and the like. A liquid crystal display device of the present invention can be applied to the display portion 3102 to complete a portable book. Thus, according to the present invention, alignment defects of the liquid crystal can be reduced, so that a fine display without display unevenness can be realized. Further, since the capacitor can be formed while maintaining a high aperture ratio, luminance can be increased and power consumption of a light source used for display can be reduced.
This can reduce the power consumption of the entire electric appliance, and it is only necessary to adopt a small battery weight. Therefore, the entire electric appliance can be reduced in weight.

FIG. 13C illustrates a display, which includes a main body 3201, a support base 3202, and a display portion 3203.
Etc. The liquid crystal display device of the present invention can be applied to the display portion 3203 to complete a display. According to the present invention, a light transmission region (region contributing to display) of a pixel electrode can be flattened and a step can be formed on a light-shielding film, so that liquid crystal alignment defects can be eliminated and display unevenness can be eliminated. In addition, since the storage capacitor can be formed without reducing the aperture ratio, high-luminance and high-definition display can be realized.

As described above, the application range of the present invention is extremely wide, and the present invention can be applied to complete electric appliances in all fields. Moreover, the electric appliance of a present Example is realizable even if it uses any of the liquid crystal display devices produced combining Example 1-6.

Claims (1)

  1. Above the substrate surface, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first insulating layer, the second insulating layer, and the semiconductor layer And having
    The first insulating layer is provided above the first conductive layer,
    The second conductive layer is provided above the first insulating layer;
    The second insulating layer is provided above the second conductive layer,
    The third conductive layer is provided above the second insulating layer,
    The semiconductor layer has a channel formation region of a transistor,
    The first conductive layer is provided above the semiconductor layer and has a region overlapping the channel formation region,
    The first conductive layer has a function of blocking light,
    The fourth conductive layer is provided below the semiconductor layer and has a region overlapping the channel formation region,
    The fourth conductive layer is electrically connected to the gate electrode of the transistor;
    The fourth conductive layer functions as a gate wiring,
    A gate electrode of the transistor is provided above the semiconductor layer;
    The gate electrode of the transistor and the source wiring are formed through a process of etching the same conductive film,
    The fourth conductive layer has a function of blocking light,
    The second insulating layer has a resin,
    The second conductive layer has a region overlapping with the first conductive layer with the first insulating layer interposed therebetween,
    The third conductive layer has a region in contact with the second conductive layer in an opening provided in the second insulating layer;
    In at least one of a plurality of planes including at least one of the plurality of perpendiculars on the substrate surface, the first conductive layer is a region protruding from an end of the first insulating layer. Have
    In the plane, the first insulating layer have a region that protrudes from an end portion of the second conductive layer,
    The display device, wherein the second conductive layer is formed through an etching process using the third conductive layer as a mask .
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