JP4896314B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix display device using a thin film transistor (hereinafter referred to as TFT) as a switching element. More specifically, the present invention relates to a pixel structure of the active matrix display device.
[0002]
[Prior art]
As an active matrix type display device, a liquid crystal display device of a method of driving using TFTs (TFT driving method) is known. Since the liquid crystal display device can control the voltage applied to the liquid crystal for each pixel by a TFT formed on a transparent substrate such as glass, the image is clear and is widely used in OA devices, TVs, and the like. .
[0003]
FIG. 1 shows an equivalent circuit of one pixel in a TFT drive type liquid crystal display device. A pixel TFT 102 is disposed at an intersection between the gate signal line 100 and the source signal line 101, and a gate terminal of the pixel TFT 102 is electrically connected to the gate signal line 100, and an input / output terminal (source or drain terminal) of the pixel TFT 102. ) Is connected to the source signal line 101, and the liquid crystal 103 and the storage capacitor 104 are connected to the other.
[0004]
When the pixel TFT 102 is turned on in response to a signal output from the gate signal line 100 to the pixel TFT 102, the potential of the source signal line 101 is written into the liquid crystal 103 and the storage capacitor 104, and electric charge is accumulated. After that, even when the pixel TFT 102 is turned off, the charges accumulated in the liquid crystal 103 and the storage capacitor 104 try to hold the written potential. The required value of the storage capacitor 104 is determined by the off current, the storage time, the parasitic capacitance, and the like of the pixel TFT 102 serving as a switching element.
[0005]
FIG. 2 is a diagram showing a cross-sectional structure of an example of a conventional storage capacitor. An active layer 201 formed on the glass substrate 200 and a capacitor wiring 203 formed of the same film as the gate wiring are used as electrodes, and a storage capacitor is formed using a gate insulating film 202 formed between the electrodes as a dielectric. is doing. By using the gate insulating film 202 as a dielectric, a highly reliable high-quality storage capacitor can be formed even when the film thickness is thin.
[0006]
Further, the active matrix display device desirably has a light shielding film. FIG. 3 shows, as an example, a cross-sectional structure of the pixel TFT provided with a light shielding film below the pixel TFT. A light shielding film 301 and an insulating film 302 are formed on a glass substrate 300, and an active layer 303, a gate insulating film 304, and a gate wiring 305 for forming a pixel TFT are overlaid thereon. The light-shielding film prevents light leakage and improves contrast, and has an effect of reducing the off-current of the pixel TFT by shielding the pixel TFT. When the off current of the pixel TFT is reduced, the display data retention characteristic is improved, and a good display can be obtained.
[0007]
[Problems to be solved by the invention]
The following points can be mentioned as methods for improving the display quality (image quality) of a conventional active matrix display device and achieving power saving, downsizing, and high reliability of the display device.
[0008]
First, in an active matrix display device, a capacitive element structure capable of securing a sufficient storage capacity even when the area per pixel is reduced as the resolution is increased is obtained. When each pixel has a storage capacitor capable of having a large capacity, display data retention characteristics are improved, and a good display can be obtained.
[0009]
Second, in the active matrix display device, the aperture ratio is not lowered even if a sufficient storage capacity is secured. When each pixel has a high aperture ratio, the light utilization efficiency of the backlight is improved, and power saving and downsizing of the display device can be achieved.
[0010]
Furthermore, by arranging a light shielding film, light leakage is prevented and contrast is improved. Further, by shielding the pixel TFT, the off current of the pixel TFT is reduced, which leads to improvement of display data retention characteristics.
[0011]
The demand to improve the performance of high-definition (miniaturization of pixel TFT), sufficient storage capacity, large aperture ratio, light-shielding film, and active matrix display device is sacrificed if one requirement is increased. It is a mutually conflicting request to become. It is an object of the present invention to improve the performance of an active matrix liquid crystal display device while satisfying these requirements.
[0012]
[Means for Solving the Problems]
In order to satisfy the mutually conflicting requirements, the present inventor considered forming a storage capacitor using a light shielding film. In addition, a method for forming a storage capacitor having a larger capacity without reducing the aperture ratio has been proposed.
[0013]
FIG. 4A is a sectional view showing an example in which the source / drain regions of the pixel TFT are extended to form a light shielding film and a capacitor. A light shielding film 401 and a dielectric (first insulating film) 402 are formed on the glass substrate 400. The active layer 403 is formed by expanding the area of the source / drain region of the pixel TFT, which is electrically connected to the pixel electrode 409, so that a necessary storage capacitor can be secured.
[0014]
The light-shielding film 401 has conductivity and may be connected so as to have a constant potential such as a COMMON potential or a power source outside the pixel region. In the case where the capacitance of the light shielding film 401 is sufficiently larger than the storage capacitance of the pixel, the potential fluctuation of the light shielding film only needs to be sufficiently small without being connected to a constant potential. Thus, a storage capacitor is formed between the active layer 403 and the light shielding film 401.
[0015]
FIG. 4B is a diagram in which in addition to the storage capacitor formed by the light shielding film 401 and the active layer 403, a capacitor wiring 410 is further formed to secure a storage capacitor having a larger capacity. A gate insulating film 404 is formed over the active layer 403, and a capacitor wiring 410 is formed simultaneously with the gate wiring 405. The capacitor wiring 410 is connected to a constant potential such as a COMMON potential or a power supply outside the pixel region, and forms a capacitor with the active layer 403. In this way, a larger holding capacity is secured without reducing the aperture ratio. In FIG. 4B, the gate insulating film formed under the capacitor wiring 410 is thinly formed to increase the storage capacitance.
[0016]
In FIG. 4, a capacitance with the light shielding film 401 disposed below is formed in both the source and drain regions of the pixel TFT. However, it is not desirable to provide a capacitance with the source signal line connected. This is because when a capacitor is formed on the source signal line, a load when a video signal is written to the source signal line increases. Therefore, as shown in FIG. 5, a structure is proposed in which the light-shielding film is divided into two layers so that a capacitor is not formed with the one to which the source signal line is connected.
[0017]
FIG. 5A shows an example using two light shielding films. A first light-shielding film 501 is formed over the glass substrate 500 and insulated by the insulating film 502 to form a second light-shielding film 503. In FIG. 5, the first light-shielding film 501 shields light from the source / drain regions of the pixel TFT connected to the source signal line so as not to have a capacity with the active layer 505. Further, the first light-shielding film 501 is used as a gate signal line by further making contact with the gate wiring 507.
[0018]
The second light shielding film 503 shields light from the source / drain region of the pixel TFT connected to the pixel electrode, and forms a capacitor with the active layer 505. The first light shielding film 501 and the second light shielding film 503 are combined so that light does not enter the active layer 505. FIG. 5B is obtained by providing the capacitor wiring 512 in FIG.
[0019]
Note that the portion that is not shielded by the light shielding film refers to a portion that can be seen from the substrate side. The first light-shielding film 501 and the second light-shielding film 503 should at least shield the channel portion (channel formation region), LDD region, and offset region under the gate electrode of the active layer 505.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
A manufacturing process of a display device (a liquid crystal display device, an EL display device, or the like) using a light-shielding film of an active matrix display device as a capacitor electrode (retention capacitor) according to the present invention will be described with reference to the drawings.
[0021]
【Example】
[Example 1]
Here, a method for manufacturing an active matrix substrate, in particular, a method for manufacturing a pixel portion will be described with reference to FIGS. The pixel portion includes a region (TFT formation region) where a pixel TFT, which is a TFT provided in the pixel, and a display region. In this specification, “electrode” is a part of “wiring”, and for convenience of explanation, “wiring” and “electrode” are used separately, but “wiring” is always included in the word “electrode”. It shall be.
[0022]
In FIG. 6A, a glass substrate or a quartz substrate can be used for the substrate 600. In addition, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used as the substrate. If heat resistance permits, a plastic substrate can be used. Then, as the first light shielding film 601, a polysilicon film 50 nm and a tungsten silicide (W—Si) film 100 nm are stacked in an island shape.
[0023]
A first insulating film 602 is formed over the first light-shielding film 601 (FIG. 6B). In this embodiment, a silicon oxide film having a thickness of 100 to 1000 nm (typically 300 to 500 nm) is used as the first insulating film 602. Note that as the first insulating film 602, a nitride film containing silicon or a silicon oxynitride film may be used. Further, a polysilicon film 50 nm and a tungsten silicide (W—Si) film 100 nm are stacked in an island shape on the first insulating film 602 as the second light shielding film 603.
[0024]
As the first light shielding film 601 and the second light shielding film 602, besides the tungsten film, tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si) Or an alloy film in which the elements are combined can be used.
[0025]
Next, a silicon oxide film is formed to a thickness of 10 to 150 nm as the second insulating film 604 (FIG. 6C). The second insulating film 604 is a dielectric that forms a capacitor with the second light shielding film 603 and the active layer of the TFT. The second light-shielding film 603 is desired to be attached at 300 nm or more, which is twice the thickness of 150 nm of the light-shielding film of this embodiment. However, since the capacity per unit area is reduced, it is at least 300 nm or less, preferably 150 nm. The following is good.
[0026]
Next, an amorphous semiconductor film (in this embodiment, an amorphous silicon film (amorphous silicon film) 605) having a thickness of 10 to 100 nm is formed on the second insulating film 604 by a known deposition method. Note that as the amorphous semiconductor film, an amorphous compound semiconductor film such as an amorphous silicon germanium film can be used in addition to the amorphous silicon film.
[0027]
Then, a semiconductor film (crystalline silicon film in this embodiment) 606 including a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. 7-130652 (corresponding to USP 5,643,826). The technology described in the publication is a catalyst element (one or a plurality of elements selected from nickel, cobalt, tin, lead, palladium, iron, and copper, typical for promoting crystallization in crystallization of an amorphous silicon film, Is a crystallization means using nickel).
[0028]
Specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a crystalline silicon film. In this embodiment, the technique described in the first embodiment of the publication is used, but the technique described in the second embodiment may be used. Note that the crystalline silicon film includes a so-called single crystal silicon film and a polycrystalline silicon film, but the crystalline silicon film formed in this embodiment is a silicon film having a crystal grain boundary.
[0029]
Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable to perform a dehydrogenation treatment by heat treatment at 400 to 550 ° C. for several hours, and to perform a crystallization step with a hydrogen content of 5 atomic% or less. . In addition, the amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, but it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0030]
Alternatively, as another crystallization method, the amorphous silicon film 605 may be irradiated with light (laser light) emitted from a laser to form the crystalline silicon film 606. As the laser, a pulse oscillation type or continuous oscillation type excimer laser may be used, but a continuous oscillation type argon laser may be used. Or Nd: YAG laser or Nd: YVO _Four Laser second harmonic, third harmonic, or fourth harmonic may be used. Furthermore, the beam shape of the laser light may be linear (including rectangular) or rectangular.
[0031]
Further, instead of laser light, light emitted from a lamp (lamp light) may be irradiated (hereinafter referred to as lamp annealing). As the lamp light, lamp light emitted from a halogen lamp, an infrared lamp or the like can be used.
[0032]
The process of performing heat treatment (annealing) with laser light or lamp light in this way is called a light annealing process. Since the light annealing process can be performed at a high temperature in a short time, an effective heat treatment process can be performed with high throughput even when a substrate having low heat resistance such as a glass substrate is used. Of course, since the purpose is annealing, furnace annealing (also referred to as thermal annealing) using an electric furnace can be used instead.
[0033]
In this example, a pulsed excimer laser beam was processed into a linear shape and a laser annealing process was performed. The laser annealing conditions are as follows: XeCl gas is used as the excitation gas, the processing temperature is room temperature, the pulse oscillation frequency is 30 Hz, and the laser energy density is 250 to 500 mJ / cm. ² (Typically 350-400mJ / cm ² ).
[0034]
The laser annealing step performed under the above conditions has an effect of completely crystallizing the amorphous region remaining after the thermal crystallization and reducing defects or the like of the already crystallized crystalline region. Therefore, this step can also be called a step of improving the crystallinity of the semiconductor film by light annealing or a step of promoting the crystallization of the semiconductor film. Such an effect can also be obtained by optimizing the lamp annealing conditions.
[0035]
Next, a protective film 607 is formed on the crystalline silicon film 606 for a subsequent impurity addition step. As the protective film 607, a silicon nitride oxide film or a silicon oxide film with a thickness of 100 to 200 nm (preferably 130 to 170 nm) is used. The protective film 607 is used to prevent the crystalline silicon film 606 from being directly exposed to plasma during the impurity addition step and to enable delicate temperature control.
[0036]
Subsequently, an impurity element imparting p-type conductivity (hereinafter referred to as a p-type impurity element) is added through the protective film 607. As the p-type impurity element, an element belonging to Group 13 of the periodic table, typically boron or gallium can be typically used. This step (referred to as channel doping step) is a step for controlling the TFT threshold voltage. Here, diborane (B ₂ H ₆ Boron was added by ion doping with plasma excitation without mass separation. Of course, an ion implantation method that performs mass separation may be used.
[0037]
1x10 by this process ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three (Typically 5 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three ), A p-type impurity region (a) 608 containing a p-type impurity element (boron in this embodiment) is formed (FIG. 6E).
[0038]
Next, after removing the protective film 607, an unnecessary portion of the crystalline silicon film is removed to form an island-shaped semiconductor film (hereinafter referred to as an active layer) 609 (FIG. 6F).
[0039]
Next, a gate insulating film 610 is formed so as to cover the active layer 609 (FIG. 6G). The gate insulating film 610 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. In this embodiment, plasma CVD is used for N. ₂ O and SiH _Four A silicon nitride oxide film is formed twice using as a raw material. First, a first silicon nitride oxide film (insulating film) is formed to a thickness of 20 nm. Next, the first silicon nitride oxide film (insulating film) in the region where the capacitor wiring is formed is etched. Then, a second silicon nitride oxide film (insulating film) is formed to a thickness of 60 nm. Then, an insulating film (second silicon nitride oxide film) having a thickness of 60 nm is formed under the capacitor wiring, and a gate insulating film (first silicon nitride oxide film + first silicon dioxide nitride film) having a thickness of 80 nm is formed in the channel portion of the TFT. That is, the thickness of the insulating film sandwiched between the active layer and the capacitor wiring is 60 nm, and the thickness of the insulating film sandwiched between the active layer and the gate electrode is 80 nm, which are different in thickness.
[0040]
An n-type impurity region containing phosphorus at a high concentration by adding an n-type impurity element (phosphorus in this embodiment) by covering only with a resist mask 611 while leaving only a portion where an insulating film (gate insulating film) is formed with a thickness of 20 nm. (A) 612 is formed (FIG. 7A). The n-type impurity region (a) 612 includes phosphine (PH _Three ) Using an ion doping method (of course, an ion implantation method may be used), and the phosphorus concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ). In addition, the region where the n-type impurity region (a) 612 is formed contains boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. There is no need to consider the effect of boron.
[0041]
The resist mask 611 is removed, and an opening 613 for making contact with the gate wiring from the first light shielding film is formed (FIG. 7B). In this embodiment, since the first light shielding film plays the role of the gate signal line, a contact connecting the first light shielding film and the gate wiring is formed in the pixel portion.
[0042]
Although not illustrated, a two-layer stacked film of tungsten nitride (WN) with a thickness of 50 nm and tantalum (Ta) with a thickness of 350 nm is formed as the gate wiring 614 (FIG. 7C). Although the gate wiring 614 may be formed using a single-layer conductive film, it is preferable to form a stacked film of two layers or three layers as necessary.
[0043]
Note that as the gate wiring 614, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or an alloy in which the elements are combined. A film (typically, a Mo—W alloy or a Mo—Ta alloy) can be used.
[0044]
Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate wiring 614 as a mask (FIG. 7D). The n-type impurity region (b) 615 thus formed has a concentration (typically 1 × 10 5) higher than the boron concentration added in the channel doping step. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three ) So that phosphorus is added.
[0045]
A resist mask 616 is formed, and an n-type impurity element (phosphorus in this embodiment) is added to form an n-type impurity region (C) 617 containing phosphorus at a high concentration (FIG. 7E). In this process, phosphine (PH _Three ) Using an ion doping method (of course, an ion implantation method may be used), and the phosphorus concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ).
[0046]
The region where the n-type impurity region (C) 617 is formed contains phosphorus or boron which has already been added in the previous step, but phosphorus is added at a sufficiently high concentration. The influence of phosphorus or boron added in step 1 may not be considered.
[0047]
After the resist mask 616 is removed, a fourth insulating film 618 is formed (FIG. 8A). The fourth insulating film 618 is formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof, and has a thickness of 600 nm to 1.5 μm. do it. In this embodiment, the fourth insulating film 618 is made of SiH by plasma CVD. _Four , N ₂ O, NH _Three As a source gas, a 1 μm thick silicon nitride oxide film (however, the nitrogen concentration is 25 to 50 atomic%) is used.
[0048]
Thereafter, a heat treatment step is performed to activate the n-type or p-type impurity element added at each concentration (FIG. 8A). This step can be performed by furnace annealing, laser annealing, or rapid thermal annealing (RTA). Here, the activation process is performed by furnace annealing. The heat treatment is performed in a nitrogen atmosphere at 300 to 650 ° C, preferably 400 to 550 ° C. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours.
[0049]
Thus, when crystallization is performed using a catalytic element, the catalytic element (nickel in this embodiment) used for crystallization of the amorphous silicon film moves in the direction indicated by the arrow, and The n-type impurity region (C) 617 containing phosphorus at a high concentration formed in the step 7 (E) is trapped (gettered). This is a phenomenon caused by the gettering effect of the metal element by phosphorus. As a result, the channel region 619 has a concentration of the catalyst element of 1 × 10 6. ¹⁷ atoms / cm ^Three The following (preferably 1 × 10 ¹⁶ atoms / cm ^Three The following.
[0050]
In addition, in the region serving as a gettering site for the catalyst element (the n-type impurity region (C) 617 formed in the step of FIG. 7E), the catalyst element segregates at a high concentration, and 5 × 10 5. ¹⁸ atoms / cm ^Three Above (typically 1 × 10 ¹⁹ ~ 5x10 ²⁰ atoms / cm ^Three ) Concentration.
[0051]
Further, a step of hydrogenating the active layer is performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0052]
Thereafter, an opening 620 (FIG. 8B) reaching the source / drain region of the TFT and a source / drain wiring 621 are formed (FIG. 8C). Although not shown, in this embodiment, this wiring is formed of a laminated film having a three-layer structure in which a Ti film is formed to 100 nm, an aluminum film containing Ti is formed to 300 nm, and a Ti film is formed to 150 nm by sputtering. .
[0053]
Next, a passivation film 622 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm) (FIG. 8D). At this time, in this embodiment, H is formed prior to film formation. ₂ , NH _Three Plasma treatment is performed using a gas containing hydrogen, and heat treatment is performed after film formation. Hydrogen excited by this pretreatment is supplied into the fourth insulating film 618. By performing the heat treatment in this state, the film quality of the passivation film 622 is improved and hydrogen added to the fourth insulating film 618 diffuses downward, so that the active layer can be effectively hydrogenated. .
[0054]
Further, after forming the passivation film 622, a hydrogenation step may be further performed. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. Alternatively, the same effect can be obtained by using the plasma hydrogenation method. In this step, an opening may be formed in the passivation film 622 at a position where an opening for connecting the pixel electrode and the source / drain wiring is formed later.
[0055]
Thereafter, a fifth insulating film 623 made of an organic resin is formed to a thickness of about 1 μm (FIG. 8D). As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. In the present invention, any material other than those described above, such as an organic resin film or an organic SiO compound, can be used. In this embodiment, a polyimide which is thermally polymerized after being applied to a substrate is used and is baked at 300 ° C.
[0056]
Next, an opening 624 reaching the source / drain wiring 621 is formed in the fifth insulating film 623 and the passivation film 622, and a pixel electrode 625 is formed (FIGS. 8D and 8E). The pixel electrode 625 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 110 nm by sputtering.
[0057]
In this manner, a pixel TFT region 626 made of an n-channel TFT is formed in the pixel portion while securing the area of the display region 627, so that a sufficient storage capacitor can be obtained.
[0058]
Although not formed in this embodiment, an LDD region may be formed in the crystalline silicon film 606 using a known method. Note that in this specification, the LDD region refers to a low concentration impurity region (Light-Doped-Drain region). Further, an offset region may be formed in the crystalline silicon film 606 using a known method. Note that in this specification, an offset region refers to a region into which an impurity element is implanted by shifting from a gate electrode.
[0059]
[Example 2]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. As shown in FIG. 9, an alignment film 901 is formed on the substrate in the state of FIG. In this embodiment, a polyimide film is used as the alignment film. In addition, a counter electrode 904 and an alignment film 903 are formed using a transparent conductive film over the counter substrate 905. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.
[0060]
After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process. Thereafter, liquid crystal 902 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal. In this way, the active matrix liquid crystal display device shown in FIG. 9 is completed.
[0061]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. Note that FIG. 10 uses common reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. The active matrix substrate includes a pixel portion 1001 formed on a glass substrate 600, a gate signal driving circuit 1003, and a data (source) signal driving circuit 1002. The pixel TFT 1008 is an n-channel TFT, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The gate signal driving circuit 1003 and the data signal driving circuit 1002 are connected to the pixel portion 1001 by a gate wiring 614 and a source / drain wiring 621 (source signal line), respectively. In addition, connection wirings 1006 and 1007 from the input terminal 1005 to which the FPC 1004 is connected to the input / output terminal of the driver circuit are provided.
[0062]
Note that this embodiment can be freely combined with Embodiment 1.
[0063]
[Example 3]
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. 11 is a top view of the EL display device of the present invention, and FIG. 12 is a sectional view thereof.
[0064]
11 and 12, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source signal driving circuit, and 4004 denotes a gate signal driving circuit. Each driving circuit reaches an FPC (flexible printed circuit) 4006 through a connection wiring 4005. Connected to an external device.
[0065]
At this time, a first sealant 4101, a cover material 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source signal driver circuit 4003, and the gate signal driver circuit 4004.
[0066]
FIG. 12 corresponds to a cross-sectional view taken along line AA ′ of FIG. 11, and includes driving TFTs included in the source signal driving circuit 4003 on the substrate 4001 (here, an n-channel TFT and a p-channel TFT are included). 4201 and a pixel TFT included in the pixel portion 4002 (however, a TFT for controlling current to the EL element is shown here) 4202 are formed.
[0067]
In this embodiment, a pixel TFT 4202 is manufactured using the capacitor structure of the present invention. That is, a TFT having the same structure as that in FIG. 8E is used for the pixel TFT 4202.
[0068]
An interlayer insulating film (planarization film) 4301 made of a resin material is formed on the driving TFT 4201 and the pixel TFT 4202, and a pixel electrode 4302 electrically connected to one of the source / drain regions of the pixel TFT 4202 is formed thereon. The As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0069]
An insulating film 4303 is formed over the pixel electrode 4302, and an opening is formed in the insulating film 4303 over the pixel electrode 4302. In this opening, an EL layer 4304 is formed on the pixel electrode 4302. A known organic EL material or inorganic EL material can be used for the EL layer 4304. The organic EL material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0070]
A known technique may be used for forming the EL layer 4304. The EL layer may have a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0071]
Over the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper, or silver as its main component or a stacked film of these with another conductive film) is formed. . In addition, it is preferable to remove moisture and oxygen present at the interface between the cathode 4305 and the EL layer 4304 as much as possible. Therefore, it is necessary to devise such that the both are continuously formed in vacuum, or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0072]
The cathode 4305 is electrically connected to the connection wiring 4005 in the region indicated by 4306. The connection wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305 and is electrically connected to the FPC 4006 through the conductive material 4307.
[0073]
As described above, an EL element including the pixel electrode 4302, the EL layer 4304, and the cathode 4305 is formed. This EL element is surrounded by a cover material 4102 bonded to a substrate 4001 with a first sealant 4101 and enclosed with a filler 4103.
[0074]
Note that in this specification, an EL element (light-emitting element) has a structure in which an EL layer (organic compound layer) is sandwiched between a pair of electrodes (an anode and a cathode). The organic compound layer can be manufactured using a known light-emitting material. In addition, the organic compound layer has two structures, a single layer structure and a laminated structure, and either structure may be used in the present invention. Note that luminescence in the organic compound layer includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Can be applied to a light-emitting device using either light emission.
[0075]
As the cover material 4102, a glass plate, a metal plate (typically a stainless steel plate), a ceramic plate, a FRP (Fiberglass Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film is used. Can do. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0076]
However, when the emission direction of light from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0077]
As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) is used. Can be used. When a hygroscopic substance (preferably barium oxide) is provided inside the filler 4103, deterioration of the EL element can be suppressed.
[0078]
Further, the filler 4103 may contain a spacer. At this time, if the spacer is formed of barium oxide, the spacer itself can be hygroscopic. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer that relieves pressure from the spacer.
[0079]
Further, the connection wiring 4005 is electrically connected to the FPC 4006 through a conductive material 4307. The connection wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source signal driver circuit 4003, and the gate signal driver circuit 4004 to the FPC 4006 and is electrically connected to an external device by the FPC 4006.
[0080]
In this embodiment, the second sealing material 4104 is provided so as to cover the exposed portion of the first sealing material 4101 and a part of the FPC 4006, and the EL element is thoroughly shielded from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. 12 is obtained. Note that the EL display device of this embodiment may be manufactured in combination with the structure of Embodiment 1.
[0081]
Note that this embodiment can be freely combined with Embodiments 1 and 2.
[0082]
[Example 4]
In this embodiment, a cross-sectional structure of a display device provided with an upper light-shielding film in addition to a lower light-shielding film provided below a transistor will be described with reference to FIGS.
[0083]
In FIG. 14, reference numeral 1910 denotes a substrate having an insulating surface. As the substrate 1910, a glass substrate, a quartz substrate, or the like can be used. A light shielding film 1906 is provided over the substrate 1910. Note that the light-shielding film 1906 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or an alloy film in which the elements are combined. Is formed by a known method. The light-shielding film 1906 has a function of shielding the transistor from light.
[0084]
Next, a first insulating film 1911 is provided over the light-shielding film 1906, and a semiconductor film 1907 is provided over the first insulating film 1911. In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the first insulating film 1911. Further, the semiconductor film 1907 was formed by a known method using a known material.
[0085]
Next, a gate insulating film 1912 is provided over the semiconductor film 1907. A gate electrode 1908 and a capacitor wiring 1909 are provided over the gate insulating film 1912. Note that in this embodiment, a region where the light-blocking film 1906, the semiconductor film 1907, and the capacitor wiring 1909 overlap corresponds to a storage capacitor.
[0086]
Reference numeral 1913 denotes a second insulating film. In this embodiment, a silicon oxide film is formed as the second insulating film 1913. Then, contact holes are formed in the gate insulating film 1912 and the second insulating film 1913, and a source wiring 1917 and a drain wiring 1918 are provided.
[0087]
Reference numeral 1914 denotes a third insulating film. In this embodiment, a silicon oxide film is formed as the third insulating film 1913. On the third insulating film 1913, an upper light-shielding film 1916 formed using a known material is provided. The upper light-shielding film 1916 is formed using a known material and has a function of shielding the transistor from light.
[0088]
1920 is a fourth insulating film. Next, contact holes are formed in the third insulating film 1914 and the fourth insulating film 1920, and a pixel electrode 1919 is provided.
[0089]
As shown in FIG. 14, the pixel electrode 1919 is electrically connected to the drain wiring 1918. Note that although the pixel electrode 1919 is connected to the drain wiring 1918 in this embodiment, the present invention is not limited to this and may be connected to the source wiring 1917. Note that one of the source region and the drain region connected to the pixel electrode has a larger area than the other.
[0090]
Reference numeral 1901 denotes an alignment film. In this embodiment, a polyimide film is used as the alignment film 1901. In addition, a counter electrode 1904 and an alignment film 1903 are formed using a transparent conductive film over the counter substrate 1905. Note that a color filter or a shielding film may be formed on the counter substrate 1905 as needed.
[0091]
After the alignment film 1903 is formed, a rubbing process is performed so that liquid crystal molecules are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process. Thereafter, liquid crystal 1902 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal 1902. In this way, the active matrix liquid crystal display device shown in FIG. 14 is completed.
[0092]
Note that this embodiment can be freely combined with Embodiments 1 to 3.
[0093]
[Example 5]
The active matrix display device of the present invention can be used as a display portion of an electric appliance. Such electric appliances include video cameras, digital cameras, projectors, projection TVs, goggles type displays (head mounted displays), navigation systems, sound playback devices, notebook personal computers, game machines, portable information terminals (mobile computers, Mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media, and the like. Specific examples of these electric appliances are shown in FIG.
[0094]
FIG. 13A illustrates a mobile phone, which includes a main body 2001, an audio output portion 2002, an audio input portion 2003, a display portion 2004, operation switches 2005, and an antenna 2006. The active matrix display device of the present invention can be used for the display portion 2004.
[0095]
FIG. 13B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The active matrix display device of the present invention can be used for the display portion 2102.
[0096]
FIG. 13C illustrates a mobile computer (mobile computer), which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display unit 2205. The active matrix display device of the present invention can be used for the display portion 2205.
[0097]
FIG. 13D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The active matrix display device of the present invention can be used for the display portion 2302.
[0098]
FIG. 13E shows a rear projector (projection TV), which includes a main body 2401, a light source 2402, a liquid crystal display device 2403, a polarization beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be used for the liquid crystal display device 2403.
[0099]
FIG. 13F illustrates a front projector which includes a main body 2501, a light source 2502, a liquid crystal display device 2503, an optical system 2504, and a screen 2505.
The present invention can be used for the liquid crystal display device 2503.
[0100]
As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-4.
[0101]
【Effect of the invention】
If an active matrix display device having a storage capacitor using the present invention is manufactured, even if the area of one pixel is reduced, a sufficient storage capacitor can be secured using a light-shielding film, so that display quality can be improved. At the same time, the quality of the electric appliance using the active matrix display device using the present invention as a display portion can be improved.
[0102]
[Brief description of the drawings]
FIG. 1 is a diagram showing an equivalent circuit of one pixel of an active matrix liquid crystal display device.
FIG. 2 is a cross-sectional view showing a conventional storage capacitor structure.
FIG. 3 is a diagram in which a light shielding film is provided below a pixel TFT.
FIG. 4 is a diagram showing a structure of a storage capacitor in the present invention.
FIG. 5 shows a structure of a storage capacitor in the present invention.
6 is a diagram showing a manufacturing process of a pixel portion of Example 1. FIG.
7 is a diagram showing a manufacturing process of a pixel portion of Example 1. FIG.
8 is a diagram showing a manufacturing process of a pixel portion of Example 1. FIG.
FIG. 9 is a cross-sectional view of an active matrix liquid crystal display device.
FIG. 10 is a perspective view of an active matrix liquid crystal display device.
FIG. 11 illustrates a structure of an active matrix EL display device.
FIG. 12 is a cross-sectional view illustrating a structure of an active matrix EL display device.
FIG. 13 shows an example of an electric appliance.
FIG. 14 is a cross-sectional view of an active matrix display device.

Claims (5)

A first light-shielding film formed on the insulating surface;
A first insulating film formed on the first light shielding film;
A second light-shielding film formed on the first insulating film;
A second insulating film formed on the second light shielding film;
A semiconductor film formed on the second insulating film and having a source region, a drain region, and a channel formation region;
A third insulating film formed on the semiconductor film;
A gate electrode formed on the third insulating film,
The display device, wherein the second light shielding film is formed so as to overlap with one of the source region and the drain region and not overlap with the other of the source region and the drain region. A first light-shielding film formed on the insulating surface;
A first insulating film formed on the first light shielding film;
A second light-shielding film formed on the first insulating film;
A second insulating film formed on the second light shielding film;
A semiconductor film formed on the second insulating film and having a source region, a drain region, and a channel formation region;
A third insulating film formed on the semiconductor film;
A gate electrode formed on the third insulating film,
The second light-shielding film overlaps one of the source region and the drain region that is electrically connected to the pixel electrode, and is electrically connected to a source signal line in the source region and the drain region. It is formed so as not to overlap with the person who is
The display device, wherein the first light-shielding film is formed so as to overlap with one of the source region and the drain region that is electrically connected to the source signal line. A first light-shielding film formed on the insulating surface;
A first insulating film formed on the first light shielding film;
A second light-shielding film formed on the first insulating film;
A second insulating film formed on the second light shielding film;
A semiconductor film formed on the second insulating film and having a source region, a drain region, and a channel formation region;
A third insulating film formed on the semiconductor film;
A gate electrode and a capacitor wiring formed on the third insulating film,
The second light-shielding film is formed so as to overlap with one of the source region and the drain region and the capacitor wiring and not with the other of the source region and the drain region. apparatus. A first light-shielding film formed on the insulating surface;
A first insulating film formed on the first light shielding film;
A second light-shielding film formed on the first insulating film;
A second insulating film formed on the second light shielding film;
A semiconductor film formed on the second insulating film and having a source region, a drain region, and a channel formation region;
A third insulating film formed on the semiconductor film;
A gate electrode and a capacitor wiring formed on the third insulating film,
The second light-shielding film overlaps the one of the source region and the drain region that is electrically connected to the pixel electrode and the capacitor wiring, and the source signal line of the source region and the drain region. It is formed so as not to overlap with the one that is electrically connected,
The display device, wherein the first light-shielding film is formed so as to overlap with one of the source region and the drain region that is electrically connected to the source signal line. In any one of Claims 1 thru | or 4 ,
The display device, wherein the first light shielding film is a gate signal line.

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