JP2001057433A - Manufacture for thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a reliable thin film transistor. SOLUTION: In a multi-chamber type film formation system, a silicon nitride film, a silicon oxide film and a silicon film are formed sequentially without exposing a glass substrate to the atmosphere. In this way, an interfacial contamination is prevented at a channel forming region and a gate insulation film. At the same time, an impurity region is formed with a gate electrode in an overlapped way, so a deterioration in age can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit formed on an insulating substrate, which is excellent in reliability and mass productivity and has high yield, and a method of manufacturing the same. The present invention is applied to a driving circuit such as a liquid crystal display or a thin film image sensor, a three-dimensional integrated circuit, or the like as an application field thereof.

[0002]

2. Description of the Related Art In recent years, attempts have been made to form a semiconductor integrated circuit on an insulating substrate such as glass or sapphire.
The reason is that the operating speed is improved by reducing the parasitic capacitance between the substrate and the wiring, and that the glass material such as quartz is inexpensive because there is no size limitation like a silicon wafer, Easy separation between devices, especially CM
This is because a latch-up phenomenon that causes a problem in a monolithic integrated circuit of the OS does not occur. Apart from the above reasons, in a liquid crystal display or a contact type image sensor, it is necessary to integrate a semiconductor element and a liquid crystal element or a light detecting element, so that a thin film transistor (TFT) is disposed on a transparent substrate. Etc. must be formed.

[0003]

For these reasons, thin-film semiconductor elements have been formed on insulating substrates. However, a conventional semiconductor integrated circuit on an insulating substrate employs the same manufacturing process as that of a semiconductor integrated circuit (monolithic integrated circuit) on a semiconductor substrate, so that the number of masks required for manufacturing has become extremely large. In a conventional monolithic integrated circuit, a silicon single crystal, which is a substrate, has extremely high reliability and has almost no problems such as deformation due to heat treatment. Therefore, even in a mask alignment process, a mask is shifted for such a reason. It was not so much.

However, generally commercially available insulating substrates have lower reliability than silicon substrates, and in particular, substrates made of a glass-based material are deformed randomly by heat treatment. In some cases, mask alignment becomes extremely difficult, for example, the masks may not be aligned.

Further, when the integrated circuit is used for the purpose of a liquid crystal display or the like, it is required to form the integrated circuit in a much larger area than the conventional integrated circuit. Was. Therefore, it has been necessary to reduce the number of mask alignment steps. The present invention proposes a manufacturing method with a small number of mask alignment steps in manufacturing an integrated circuit on such an insulating substrate.

Another object of the present invention is to improve the reliability of the obtained integrated circuit and improve the yield. In the case of forming an integrated circuit on an insulating substrate, particularly, electrostatic breakdown of an element becomes a problem. This is because static electricity is easily generated due to the insulating substrate, and it is difficult to remove static electricity. In particular, electrostatic breakdown between multilayer wiring
For example, in the case of a liquid crystal display, one line in each of the vertical and horizontal directions becomes unusable due to the destruction of one place, and it cannot be supplemented with other parts as in the case of a semiconductor memory, for example. Is big.

[0007]

The present invention seeks to solve the above-mentioned problems by introducing a completely different process from the conventional one. That is, regarding the interlayer insulator used in the conventional integrated circuit, in the present invention,
The insulator formed by oxidizing the lower wiring layer is used as all or a part of the interlayer insulator, thereby reducing the number of times of mask alignment or improving the breakdown voltage between the multilayer wirings.

FIG. 1 shows an example of the present invention. First, a silicon oxide film 102 having a thickness of 100 to 1000 nm is formed as a passivation film on a substrate 101 having an insulating surface, and a semiconductor film is formed thereon. As a substrate having this insulating surface, a glass substrate, a substrate having an insulating film provided on a silicon wafer, a substrate having an insulating film provided on a monolithic semiconductor integrated circuit using a silicon semiconductor, or the like can be used. The passivation film has a function of suppressing mobile ions such as sodium from the substrate from penetrating into a semiconductor region thereover and deteriorating semiconductor characteristics. This passivation film may be a single-layer film or a multilayer film of, for example, silicon nitride, silicon oxide, aluminum oxide, or the like. Further, when the substrate is of sufficiently high purity and the number of mobile ions is sufficiently small, it is not necessary to provide the passivation film in this way. As the semiconductor film, for example, amorphous, polycrystalline, or microcrystalline silicon may be used. The semiconductor film is etched to form a semiconductor region 103.
To form

Further, an insulating film is formed thereon. Since this insulating film is used as a gate insulating film, use a film having excellent characteristics at the interface with the underlying semiconductor region and a film having few defects such as a carrier trap center and an interface state. It is desired. For example, EC
A silicon oxide film or the like formed by the R-CVD method is preferable. Further, a structure in which a plurality of insulating films are stacked in multiple layers may be employed.
The thickness of the insulating film is determined in consideration of use as a gate insulating film. Typically, 50-500n
m. Thus, the structure shown in FIG. 1A is obtained.

Thereafter, a metal film mainly composed of a metal, for example, aluminum is formed. That is, aluminum containing almost no impurities or pure aluminum has insufficient strength. For example, when the aluminum is weak to mechanical force such as electromigration, an alloy obtained by adding 1 to 10% of silicon to aluminum is used. To form a coating. Instead of aluminum, titanium or tantalum, or titanium silicide, tantalum silicide, an aluminum compound, a titanium compound, or a tantalum compound may be used. These metals can form an oxide film of the material by an anodization method (anodization method), and this oxide film has excellent pressure resistance. However, care must be taken in selecting this metal that titanium oxide and tantalum oxide have a much higher dielectric constant than aluminum oxide. Therefore, if these materials having a high dielectric constant are used as the interlayer insulator, the dielectric loss may increase. In addition, it must be considered in selecting a material that tantalum and titanium have a higher resistivity than aluminum. Therefore, for example, even if the first wiring is the same, high-speed response is required, and aluminum is used for the gate wiring which is required to have a small electrostatic loss with the upper wiring, so that high-speed response is required. Instead, it is also desirable to use tantalum or titanium separately for the storage capacitor wiring required to function as a capacitor. Of course, in this case, the number of extra masks is required. The metal film thus formed is selectively removed to function as, for example, a gate electrode 106, a wiring (gate wiring) 105 extending therefrom, or a storage capacitor electrode, and used separately from the gate wiring. The wiring (storage capacitor wiring) 107 to be formed is formed. The gate electrode may be a single layer of phosphorus-doped silicon or metal, or a multilayer of phosphorus-doped silicon film and metal film. In the case of a multilayer, the thickness of the phosphorus-doped silicon film is, for example, 20 to 500 °.

Next, an impurity is introduced into the semiconductor region by a known impurity diffusion method, for example, an ion implantation method or a plasma doping method, to form an impurity region 108. At this time, since the gate electrode 106 functions as a mask at the time of impurity implantation, an impurity region is formed in a self-aligned (self-aligned) manner. In this way, FIG.
Is obtained.

After the formation of the impurity region, the substrate is immersed in an appropriate electrolytic solution, and the gate wiring and the storage capacitor wiring are connected to a power supply, and anodic oxidation is performed through a DC or AC current. An oxide film 109 is formed on the surface of the capacitor electrode or the like. When aluminum is used as the material of the wiring or the like, a film of aluminum oxide is formed. When titanium is used, a film of titanium oxide is formed. When tantalum is used, a film of tantalum oxide is formed. These oxide films do not consist purely of metal and oxygen, but instead contain elements constituting the electrolyte or become hydrates, so that their physical properties change. For example, when an organic acid is used for the electrolyte, carbon is contained in the oxide film, and when sulfuric acid is used, sulfur is contained. The use of materials containing alkali metal ions for the electrolyte should be avoided. Alkali metal ions (sodium and potassium)
The reason is that when the semiconductor enters the semiconductor region, the conductive characteristics of the semiconductor are significantly damaged.

The thickness of the oxide film is determined according to the required breakdown voltage, and since the gate electrode recedes by this oxidation step, the thickness is determined in consideration of how the impurity region overlaps the gate electrode. Typically, the thickness of the oxide film is 1
0 to 1000 nm.

For example, when only the gate wiring is connected to the power supply and the storage capacitor wiring is not connected, an oxide film is formed only on the gate wiring, and the storage capacitor wiring is formed of a material other than the natural oxide film. Substantially no oxide film is formed. Alternatively, the time, the current, the voltage, etc., for supplying current to each may be changed. Thus, the thickness of the oxide film to be formed can be changed. For example, when used as an interlayer insulator, it is desirable that the film thickness be large in order to reduce the capacitance between wirings, while on the other hand, when it is used as an insulator of a capacitor such as a storage capacitor, it is desirable that the film thickness be thin. When there is a difference in such purpose, it is effective to use the above-described method.

After the wiring and the like are covered with the oxide film in this way, the substrate is taken out of the solution and dried well. If necessary, the oxide film may be modified by exposure to hot water or high-temperature steam. That is, in the anodic oxidation method, under the conditions for obtaining a particularly thick oxide film, the obtained film is a porous film. Although such a film is thick, there is a case where there is a problem in withstand voltage, and in a later step, a current may be short-circuited through a hole. In such a case, the oxide film may be reacted with high-temperature water to form a hydrate, and the volume may be expanded to close the roughness. Thus, a dense film having good insulating properties can be obtained. In any case, it is necessary to sufficiently wash and dry the electrolyte so that no electrolyte remains on the coating. Thus, FIG. 1C is obtained.

After that, a metal film is formed and is patterned to form, for example, a drain wiring / electrode 110 and a source electrode 11. In particular, in a multilayer wiring such as a matrix circuit, the wiring formed in this manner may need to intersect with the wiring formed first. Conventionally, after the first wiring is formed, an interlayer insulating material is formed with an insulating material, and then the upper wiring is formed. In the present invention, the upper wiring is formed directly without forming the interlayer insulating material. It is possible. That is, the lower wiring is already covered with the oxide film. Therefore, at this stage, the number of masks can be reduced by one as compared with the conventional method. Thus, FIG. 1 (D)
Get.

In the present invention, three masks required for obtaining FIG. 1D are used for forming a semiconductor region, forming a first metal wiring, and forming a second metal wiring. However, the conventional method requires four wafers for forming a semiconductor region, forming a first metal wiring, forming a source electrode of a transistor (drilling a hole in an interlayer insulator), and forming a second metal wiring. Was.

Thereafter, as shown in FIG. 1E, for example, a film of a transparent conductive material such as indium tin oxide or tin oxide is formed by, for example, a sputtering method, and is patterned to form a liquid crystal display. If a pixel electrode is formed, a pixel of a liquid crystal display is formed. The number of masks required for the above steps is four. In FIG.
A state in which the pixels of the liquid crystal display thus manufactured are viewed from above is shown. The chain line abcd in the figure is
Corresponding to abcd in FIG. 1E, FIG. 1 schematically shows a cross section at each point.

As apparent from FIG. 1E, the end of the impurity region 108 of the thin film transistor (TFT) does not coincide with the end of the gate electrode. In the figure, the gate electrode and the impurity region are drawn so as not to overlap. The opening L between the gate electrode and the impurity region (this is referred to as offset) is designed to be, for example, 0.2 to 0.5 μm. This feature is also a feature of the present invention. That is, in the example of FIG. 1, after the impurity is implanted in a self-aligned manner to form the impurity region, the surface of the gate electrode is oxidized, and the surface of the gate electrode recedes by this oxidation step. Therefore, an offset state is set. By setting such an offset state, the ON / OFF ratio of the drain current of the TFT is increased, and the effect of suppressing the increase of the leak current often observed when a gate voltage of the opposite polarity is applied is reduced. Obtainable.

FIG. 1 shows an example in which the relationship between the gate electrode and the impurity region is an offset. However, according to the present invention, the magnitude L of the offset can be set to an arbitrary value. The overlapped state in which the impurity regions overlap can also be freely set. That is, for example, if the ion implantation method is used as the impurity implantation method, the degree of secondary scattering of the implanted ions can be adjusted depending on the energy of the ions. Secondary scattering of ions causes impurity ions to go under the gate electrode. That is, if the secondary scattering is large, the overlap between the gate electrode and the impurity region is large, resulting in an overlap state. Also, if the secondary energy is suppressed by reducing the energy of the ions, the overlap is suppressed.

On the other hand, in the present invention, the gate electrode recedes thereafter by oxidizing the gate electrode. The degree of this regression is determined by the degree of oxidation. Therefore,
By controlling the ion implantation energy and the oxidation conditions, the offset state and the overlap state can be realized with an arbitrary size.

In the figure, the storage capacitor electrode / wiring 107
It is shown. This electrode / wiring faces the transparent pixel electrode 112 via the oxide film, and is kept at the same potential as the counter electrode formed with the liquid crystal interposed therebetween, thereby providing a capacitance parallel to the capacitance of the liquid crystal pixel. Configuration. This is because, for example, when the parasitic capacitance between the gate and the source of a thin film transistor (TFT) is large, the ON /
It is provided for the purpose of reducing the fluctuation of the potential of the liquid crystal pixel due to OFF. In the example of FIG. 1, oxides such as titanium, aluminum, and tantalum serve as dielectrics, and the relative dielectric constant of these materials is more than twice that of silicon oxide, which is a typical insulating / dielectric material. Can be reduced. That is, to increase the area of the liquid crystal pixel which transmits light (increase the aperture ratio).
Becomes possible. In addition, such storage capacitors are not necessary in liquid crystal displays.

FIG. 3 shows another example of the present invention. In the example of FIG. 1, the interlayer insulator is only the oxide film of the lower wiring. In this case, however, there is a problem in terms of thickness, and since such an oxide has a large dielectric constant, This causes an increase in the capacitance between wirings. Therefore, FIG. 3 shows an example in which the interlayer insulator is made of two layers, the thickness thereof is increased, and the average dielectric constant is reduced to reduce the capacitance between wirings.

As in the case of FIG. 1, a passivation film 302 is formed on an insulating substrate 301 and a semiconductor region 3 is formed.
03, a gate oxide film 304 is formed, and further, a gate wiring 305, a gate electrode 306, and a storage capacitor wiring 307 are formed. I do. Before the ion implantation, unlike the case of FIG. 1, it is preferable to leave all the gate oxide films. Thus, FIG. 3A is obtained.

After that, as shown in FIG. 3B, the surfaces of the gate wiring 305, the gate electrode 306, and the storage capacitor wiring 307 are oxidized as necessary as in the case of FIG. And
An interlayer insulator 313 is formed, and holes 314 and 315 for source and drain electrodes are formed therein. Further, a drain wiring 310 and a source electrode 311 are formed, and FIG.
(C) is obtained.

Finally, as shown in FIG. 3D, a transparent conductive electrode (pixel electrode) 312 is formed to form a pixel of the liquid crystal display. In this example, the number of masks used in all the steps is five, including formation of a semiconductor region, formation of a gate wiring, formation of an interlayer insulating film, formation of a drain wiring, and formation of a pixel electrode. Is the same as the conventional case.

However, in the present invention, for example, the intersection of the gate wiring and the drain wiring has a two-layer structure such as an oxide layer of the gate wiring and a layer of an interlayer insulator. Since the oxide thus obtained is a honey and has a high pressure resistance, it is suitable for insulating separation between layers. Conventionally, there was only one interlayer insulating layer,
There is a problem with its pressure resistance, especially since there is a step at the wiring intersection, the interlayer insulator cannot cover this step, and there is a defect such as a crack, which causes a short circuit with the upper wiring. There were many things. However, in the present invention, there is no need to consider such a defect due to a step at all, and this contributes to a great improvement in yield.

Although the above example has described an example using only one conductive type thin film transistor, it is needless to say that a complementary device combining two or more transistors, that is, a so-called CMOS is also used. Can be used. FIG. 4 shows an example of a pixel of a liquid crystal display using CMOS. In the case of CMOS, one or two more photolithography steps are required for one conductivity type transistor. FIG.
5 shows a process that requires five masks to form one pixel.

First, as in the previous examples, the insulating substrate 40
1, a passivation film 402 is formed, and further, semiconductor regions 403a and 403b are selectively formed. Thereafter, a gate insulating film is formed, and a metal wiring 409 and gate electrodes 406a and 406b are formed thereon using a material such as aluminum.

Then, the surfaces of the wirings and electrodes are oxidized to an appropriate thickness by an anodic oxidation method. For example, wiring
When aluminum is used as the electrode material, the surface is covered with a coating 409 of aluminum oxide. Next, if the gate insulating film is silicon oxide, for example, if the substrate is lightly etched with a 1/10 HF (hydrogen fluoride) solution, the gate insulating film is selectively etched. At this time, the silicon oxide under the gate wiring and the gate electrode covered with the aluminum oxide is not etched.
After that, an impurity is introduced into the semiconductor region by a known method. At this time, the conductivity type of the impurity is, for example, n-type.

Alternatively, after oxidizing the surface of the gate wiring / electrode, impurities are introduced while the gate insulating film remains, and thereafter the gate insulating film is etched using aluminum oxide as a mask. The structure is obtained. Thus, FIG. 4A is obtained.

For example, in the example of FIG. 1 or FIG. 3, the impurity is introduced prior to the oxidation of the surface of the wiring and the electrode, and in the example of FIG. 1, the removal of the gate insulating film is performed before the surface oxidation. As a result, as typically shown in FIG. 1C, aluminum oxide remained on the surface of the wiring / electrode like a mushroom umbrella. For example, if the thickness of the aluminum oxide is 500 nm, a protrusion of about 250 nm can be formed, so that in subsequent wiring formation, voids and voids are formed under the umbrella, which may cause disconnection. . However, in the example of FIG.
Since such voids and voids are rarely generated, there is no problem such as disconnection.

Next, the left semiconductor region 403a is covered with a material 407 such as a photomask, and p-type impurities are introduced in that state. Through the above steps, an n-type impurity region 408a and a p-type impurity region 408b are obtained. Thus, FIG. 4B is obtained.

Instead of the above steps, first, without adding impurities to any of the semiconductor regions,
03b is coated with a photoresist or the like to form a semiconductor region 40
A step of introducing an n-type impurity only into 3a and then introducing a p-type impurity into only the semiconductor region 403b while covering the semiconductor region 403a may be adopted. However, adopting such a method requires one more mask in addition to the method of FIG.

Thereafter, in the same manner as in the example of FIG. 1, metal wiring / electrodes 410a and 410b, 411 are formed, and
A structure as shown in FIG. 4C is obtained, and further, a pixel electrode 412 is formed to obtain a structure as shown in FIG.

FIG. 5 shows a top view of one pixel of the liquid crystal display device obtained by the above steps. In this example, a part of the gate wiring 405 (or the adjacent gate wiring 405 ') is inserted under the pixel electrode 412, thereby forming a capacitor therebetween, thereby performing the same function as the storage capacitor of FIG. I decided to have it.
A, b and c given by the chain lines in FIG.
FIG. 4 corresponds to a, b, and c in (D), and FIG. 4 shows a cross section along the chain line.

The above is an example in which a CMOS structure is used as an inverter structure. In addition, Japanese Patent Application Nos. 3-145842, 3-145463, 3-145566, 3-145 filed by the present inventors filed the present invention. 157502, 3-157
503, 3-157504, 3-157505, 3-157506, 3-157507, and the like, or a modified structure thereof.

The number of masks for obtaining this structure is five for forming a semiconductor region, forming a gate electrode and wiring, forming a p-type impurity region, forming a (second) metal wiring, and forming a pixel electrode. It is. Conventionally, there are a total of six sheets for forming a semiconductor region, forming a gate electrode and wiring, forming a p-type impurity region, forming an electrode hole for an interlayer insulator, forming a (second) metal wiring, and forming a pixel electrode. Was needed.

FIG. 6 shows another manufacturing method using the present invention for obtaining a CMOS structure. This is shown in FIG.
It will be more easily understood from the manufacturing method shown in FIG. In this example, the thickness of the intersection between the first wiring 605 and the second wiring 610a is equal to the thickness of the anodic oxide film 6 of the metal wiring.
09 alone is not sufficient, and when it is considered that the capacitance between wirings becomes too large, an interlayer insulator 613 is formed separately in addition to the anodic oxide film. In that case,
Formation of semiconductor regions (603a, 603b), gate wiring
Formation of electrodes (605, 606a, 606b), formation of resist (607), hole for electrodes (614a, 6
14b, 615), forming a second metal wiring / electrode (610)
a, 610b, 611) and the formation of the pixel electrode (612) are required. This is the same as the minimum number required by the conventional manufacturing method, but the effects obtained by using the present invention are the same as those obtained by the manufacturing method of FIG. And substantially the same, and a high yield could be achieved.

FIG. 7 shows another example using the present invention. In the example of FIG. 1 (and FIG. 4) or FIG. 3 (and FIG. 6), the thickness of the interlayer insulator between the lower wiring and the upper wiring, and the thickness of the insulator between the storage capacitor wiring and the pixel electrode are: Although substantially the same, the former prefers a thicker one, while the latter prefers a thinner one. A method for solving this inconsistency is the method shown in FIG.

As in the case of FIG. 1, a passivation film 702 is formed on an insulating substrate 701 and a semiconductor region 703 is formed.
Is formed, a gate oxide film 704 is formed, and
Gate wiring 705, gate electrode 706, storage capacitor wiring 7
After the formation of 07, the surfaces of these wirings and electrodes are anodized, and the gate insulating film is removed using the anodic oxide film 709 as a mask. Then, an impurity is implanted by ion implantation in a self-aligned manner using the gate as a mask to form an impurity region 708. The gate insulating film may be left without being removed. Thus, FIG. 7A is obtained.

Thereafter, a pixel electrode 712 is formed as shown in FIG. Further, as shown in FIG. 7C, an interlayer insulator 713 is formed, and holes 714 for source and drain electrodes are formed therein. Further, the drain wiring 71
0 is formed to obtain FIG.

In the pixel of the liquid crystal display having such a structure, the interlayer insulator at the intersection of the wiring is thick and the dielectric layer of the storage capacitor is thin. The masks required for the above steps include the formation of a semiconductor region, the formation of gate wiring and electrodes, the formation of pixel electrodes, the formation of electrode holes for interlayer insulators, and the formation of upper metal wiring.
It is a sheet.

However, in such a structure, the upper metal wiring (functioning as a drain wiring) is located above the pixel electrode, and as a result, when the opposing electrode is provided, the portion of the drain wiring A phenomenon occurs in which the electric field is large and the electric field in the pixel electrode portion is small. In normal operation, the drain wiring is in a state where signals can be constantly applied. Therefore, even if the area of the drain wiring is small, the voltage applied thereto is large, so that regardless of the image, It always presents a bright or dark state, giving serious problems to the image. Further, since the signal on the drain wiring includes information of another pixel, a phenomenon similar to crosstalk occurs as a result. Therefore, when adopting the structure as shown in FIG. 7, pay sufficient attention to this point. For example, the TFT panel is arranged on the near side (the drain wiring is always invisible because it is not seen in the shadow, so it is added to the drain wiring). (The effect of the signal does not appear visually.)

In the examples shown in FIGS. 1 and 3, the pixel electrode was not flat because the storage capacitor wiring and the like exist below the pixel electrode. For this reason, the magnitude of the electric field varies in the same pixel electrode, and the brightness of each pixel sometimes varies due to a slight difference in the width of the wiring. For this reason,
In order to obtain a pixel with little variation, it is desirable that the pixel electrode is flat and the height of each pixel is the same. FIG. 8 is an example of the present invention that solves such a problem.

As in the case of FIGS. 1 and 7, the insulating substrate 80
1, a passivation film 802 is formed, a semiconductor region 803 is formed, a gate oxide film 804 is formed, and further, a gate wiring 805, a gate electrode 806, and a storage capacitor wiring 807 are formed. The surface is anodized, and the gate insulating film is removed using the anodized film 809 as a mask. Then, impurities are implanted in a self-aligned manner by ion implantation using the gate as a mask to form an impurity region 808. The gate insulating film may be left without being removed. Thus, FIG.
Get.

Thereafter, as shown in FIG. 8B, a drain wiring 810 is formed. Further, as shown in FIG. 8C, for example, a flat film 81 made of an organic material such as polyimide is used.
3 and finally a source electrode hole 815 is formed to form a pixel electrode 812, and FIG. 3D is obtained.

The masks required for the above steps include formation of a semiconductor region, formation of a gate wiring / electrode, formation of an upper metal wiring,
There are five sheets, one for forming an electrode hole of an interlayer insulator and the other for forming a pixel electrode. As described above, by using the present invention, a semiconductor device which meets extremely various purposes can be manufactured.

In the present invention, an anodic oxidation method may be used as a method for oxidizing a metal wiring. In this anodic oxidation method, 50 to 200 V is applied between the anode and the cathode in the electrolytic solution.
Alternatively, a higher voltage may be applied, and a large potential gradient of 10 MV / cm or more may be generated around the metal wiring / electrode during anodization. Therefore, it is necessary to protect the gate insulating film from such a high voltage. For this purpose, it is desired that the semiconductor region has the same potential as the gate wiring / electrode.

FIG. 9 illustrates the method. First, a stripe-shaped semiconductor region 903 is formed over an insulating substrate 901. Then, after forming a gate insulating film on the semiconductor region, holes 9 are formed in the gate insulating film at the end of each semiconductor region.
Then, a gate wiring / electrode 905 is formed. That is, the semiconductor region 903 and the gate wiring / electrode 9
05 is maintained at the same potential through the hole 916. After that, if anodic oxidation is performed, the semiconductor region and the gate wiring
Since an electric field is not substantially generated between the electrodes, it is less likely that an excessive voltage is applied to the gate insulating film and the gate insulating film is broken. This state is shown in FIG.

After completion of the anodic oxidation, impurities are introduced, and the stripe-shaped semiconductor region is divided into appropriate lengths. Then, a hole 917 is provided in the gate wiring-shaped anodic oxide film, and then a drain wiring / electrode 910 is formed. In this state, the gate wiring 905 and the drain wiring 916 are kept at the same potential. As a result, at the intersection of the gate wiring and the drain wiring, dielectric breakdown caused by static electricity generated during the operation can be prevented. However, this step has nothing to do with the high voltage during anodization. afterwards,
The pixel electrode 912 may be formed, and then the peripheral metal wiring may be removed.

In the above steps, a lithography step is required in order to form a hole for connection between wirings in the periphery of the substrate. However, these precisions are so low that they do not pose a problem as compared with those of the pixel portion. Thus, there is almost no decrease in yield due to the addition of these steps. Further, for example, it is also possible to evaporate only the oxide film on the surface by using a laser, and if such a method is adopted, the process is greatly simplified.

The mask used in the method of FIG. 9 is (1)
Formation of a stripe-shaped semiconductor region, (2) formation of a hole in a gate insulating film, (3) formation of a gate wiring and an electrode, (4) cutting of a stripe-shaped semiconductor region, and (5) formation of an anodized film. As compared with the method of FIG. 1 for obtaining the same structure, such as (6) formation of a drain wiring / electrode and (7) formation of a pixel electrode, a larger number of masks are required. Of these, the masks required in the steps (2) and (5) do not need to have high accuracy, so that, in comparison with FIG.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION

[0055]

An embodiment using the present invention will be described with reference to FIG. In this embodiment, a CM formed on an AN glass substrate is used.
The present invention is applied to an OS type TFT. First,
As shown in FIG. 10A, a 100-nm-thick silicon nitride film 152a is formed over an AN glass substrate 151 by a low-pressure CVD method. Low pressure CVD uses dichlorosilane (SiH ₂ Cl ₂ ) and ammonia as raw material gases,
The reaction may be performed at a pressure of 10 to 1000 Pa and at a temperature of 500 to 800C, preferably 550 to 750C. of course,
Silane (SiH ₄ ) and trichlorosilane (SiHC
l ₃ ) may be used. Instead of the low pressure CVD method, a CVD technique such as a plasma CVD method, a photo CVD method, or a plasma enhanced CVD method may be used.

The silicon nitride film thus formed is
It has a function of preventing mobile ions (such as sodium ions) contained in a glass substrate from entering a semiconductor. Therefore, it is not necessary to provide a silicon nitride film if mobile ions are sufficiently small on the substrate. Further, the silicon nitride film may be an aluminum oxide film. In forming the aluminum oxide film, trimethylaluminum (Al (CH ₃ ) ₃ ) and an oxidizing gas such as oxygen or dinitrogen monoxide (N ₂ O) may be used in the aforementioned low pressure CVD method. . A similar material may be used even when another CVD method is adopted. Further, it can also be formed by a sputtering method.

In the figure, a state in which the silicon nitride film is provided only on the element formation surface on the glass substrate is shown. If possible, a film is formed so that the entire glass substrate is covered with the silicon nitride film. It is hopeful. Because, in the later anodic oxidation step, the substrate is immersed in the solution, so if there is an exposed portion of the glass, alkali ions will dissolve into the solution from that portion and adhere to the semiconductor region, This is because it is possible to invade.

Next, the silicon oxide film 152b is
Only nm is formed. This formation includes ECR plasma CV
Method D or sputtering was suitable. A semiconductor region is formed on the silicon oxide film.
If many interface states, trap centers, and the like occur at the interface between the silicon oxide film and the semiconductor region, the conductivity of the semiconductor region cannot be controlled, and the characteristics of the transistor deteriorate. Therefore, sufficient care must be taken in forming this silicon oxide film. In particular, silicon nitride cannot be used instead of silicon oxide. That is, in many cases, the silicon nitride film itself has a property of trapping carriers inside.

According to the study of the present inventors, a silicon oxide film formed by ECR plasma CVD or sputtering has a sufficiently low interface state density.
It is suitable for this purpose. In particular, when forming by sputtering, a silicon oxide bulk was used as a target, the atmosphere was a mixed atmosphere of oxygen and argon, and the oxygen concentration was 50 to 100%. In the case of forming by ECR plasma CVD, silane (SiH ₄ ) and oxygen may be used.
The density of the interface states between the silicon oxide film thus formed and the semiconductor film (silicon film) formed thereafter is:
It was 10 ¹¹ cm ^-2 , which was extremely excellent. Further, when forming a film by a sputtering method or an ECR plasma CVD method, 1 to 5% of hydrogen chloride or hydrogen fluoride is mixed in the atmosphere, or
When silane containing chlorine or fluorine (for example, dichlorsilane or silicon tetrafluoride SiF ₄ ) is mixed in an amount of 1 to 10%, chlorine or fluorine is taken into the silicon oxide film, and these are strongly bonded to silicon. However, the unpaired bond of the silicon-oxygen bond is terminated, so that the interface state can be further reduced. For example, it can be 5 to 9 × 10 ¹⁰ cm ⁻² .

Next, a silicon film is formed to a thickness of 30 nm by a low pressure CVD method. 6N or more silane (SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ ) is used as a silicon source,
No impurity doping was performed. However, especially when used as a CMOS, when it is required that the threshold voltages of the NMOS and the PMOS are substantially equal, the boron should be contained in an amount of 10 ¹⁵ to 10 ¹⁶ cm ⁻³ .
A small amount of diborane (B ₂ H ₆ ) may be mixed in the source gas. Alternatively, an equivalent treatment can be performed by implanting impurity ions (for example, BF ₂ ⁺ ) into the silicon film after film formation.

The above three layers are formed by a film forming apparatus capable of continuously forming a film without exposing the substrate to the atmosphere.
This was performed by a so-called multi-chamber type film forming apparatus. In particular, in a thin film transistor, the characteristics of the interface of the semiconductor are important, and therefore, a continuous film formation method capable of preventing the interface from being contaminated is indispensable.

Thereafter, the silicon film is patterned by a known photolithography method to form a P-channel TFT region 1.
53a and an N-channel TFT region 153b were formed. Then, annealing was performed at 600 ° C. for 24 to 72 hours in a hydrogen atmosphere to crystallize. Further, a silicon oxide film 154 to be a gate insulating film was formed by the sputtering method or the ECR plasma CVD method described above. As with the silicon oxide film 152b, the interface characteristics with the semiconductor region are important as in the case of the silicon oxide film 152b. This silicon oxide film was formed with a thickness of 100 nm.

Thereafter, an aluminum film was formed to a thickness of 0.8 to 1.0 μm by an electron beam evaporation method. In addition, a sputtering method or an organic metal CVD method can be used for forming the aluminum film. And
These aluminum films are patterned by a known photolithography method to form a gate electrode 156a.
And 156b, and further, a gate wiring 155 was formed. Thus, FIG. 10A is obtained. The width of the gate electrode was 10 μm.

Next, the surface of the gate electrode / wiring is oxidized by anodic oxidation to form a thickness of 0.3 to 0.5 μm.
m of aluminum oxide film was formed. Anodization was performed according to the following procedure. Here, it should be noted that the numerical values used in the following description are merely examples, and may vary depending on the size of the element to be manufactured.
That is, the optimal value is determined. That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid having a sufficiently low alkali ion concentration was prepared. The concentration of tartaric acid is 0.1 to 10%, for example, 3%.
20%, for example, 10% ammonia water is added, and the pH is 7
It was adjusted to be ± 0.5.

In this solution, a platinum electrode was provided as a cathode, and the substrate was immersed in the solution. Then, the gate wiring / electrode on the substrate was connected to the positive electrode of the DC power supply. At first, the current was passed so as to be constant at 2 mA. The voltage between the anode and cathode (platinum electrode), along with the concentration of the solution,
It changes with time depending on the thickness of the oxide film formed on the gate electrode / wiring. Generally, as the thickness of the oxide film increases, a higher voltage is required. When the current continues to flow and the voltage reaches 150 V,
The voltage was kept constant and the current continued to flow until the current reached 0.1 mA. The constant current state lasted about 50 minutes, and the constant voltage state lasted about 2 hours. Thus, the aluminum oxide film 15 having a thickness of 0.3 to 0.5 μm is formed on the surface of the gate electrode / wiring.
9 could be formed. The aluminum oxide film thus formed was sufficiently dense by itself, but was kept in hot water for 10 minutes in order to further increase the insulating property. By this step, a high withstand voltage film of 6 to 12 MV / cm was formed. This state is shown in FIG.

Thereafter, the substrate is immersed in a hydrofluoric acid solution, for example, 1/10 hydrofluoric acid, and the silicon oxide film 154 is etched to expose the surface of the semiconductor region. At this time, since the aluminum oxide is insoluble in hydrofluoric acid, the silicon oxide film under the gate electrode and wiring is not removed but remains as it is. However, care must be taken since the silicon oxide film under the gate electrode and wiring will be dissolved if left in hydrofluoric acid for a long time.

Thereafter, by a known ion implantation method, first, boron ions or boron compound ions (for example, BF
₂ ⁺⁾ is injected only 10 ¹⁸ cm ^-3. At that time, no ions enter the portion of the semiconductor region below the gate electrode except for secondary scattering of the implanted ions, that is, the impurity region may be formed in a self-aligned (self-aligned) manner. it can. Thus, P-type impurity region 158a
To form

Next, as shown in FIG. 10C, phosphorus ions are implanted with the photoresist 157 covering the semiconductor region 153a and only the semiconductor region 153b being exposed. At this time, the phosphorus concentration is 10 ²⁰ cm ⁻³ .
Then, although boron already exists in the semiconductor region 153b, the concentration of phosphorus is higher than that of phosphorus, so that the semiconductor region 153b shows N-type and the N-type impurity region 158b is obtained. As described above, the impurity element can be introduced into the semiconductor region. However, in the region into which such an impurity is introduced, the crystal is destroyed by the impact at the time of ion implantation, and an amorphous or microcrystalline state is obtained. Or, they are in a mixed state. Since there is no appropriate term to describe this state, it is described here as an amorphous state.

Next, the photoresist was removed, and laser annealing such as an excimer laser or an argon ion laser was applied from above to perform laser annealing. Laser annealing is performed, for example, using a KrF excimer laser (wavelength 248 nm, pulse width 10 ns).
In the case of c), the energy density is 150 to 250 m.
J / cm ² , for example, 210 mJ / cm ²
When 0 shots are added, crystallization can be performed almost certainly.
If the number of shots is less than this, the degree of crystallization is not uniform due to uncontrollable fluctuations and variations in laser output. Further, in this laser annealing, light does not enter below the gate electrode, so that it cannot be crystallized below the gate electrode. However, when the semiconductor region is thick, the laser beam is wrapped by the diffraction of the light beam and crystallization proceeds. The extent to which the laser light wraps around is approximately the wavelength of the laser when the thickness of the semiconductor region is larger than the wavelength of the laser, and is approximately the thickness of the semiconductor region when the thickness of the semiconductor region is smaller than the wavelength of the laser. is there. When the thickness of the semiconductor region is 30 nm, which is significantly smaller than the wavelength of the laser light (248 nm) as in this embodiment, the degree of the wraparound is sufficiently smaller than the width of the gate electrode (10 μm). . Therefore, there are portions where the crystallinity cannot be recovered even by this laser annealing, while being brought into an amorphous state by ion implantation. The significance of that part will be described later.

As described above, the structure of the CMOS type TFT was largely obtained. After that, a metal wiring may be formed on this TFT, but unlike a conventional TFT, it is very simple because the trouble of forming electrode holes for source and drain can be omitted. That is, since the semiconductor region is already exposed,
An ohmic junction can be obtained only by forming a metal film such as aluminum thereon. Therefore, for example, after forming a multilayer film of aluminum or aluminum and chrome 163 as shown in FIG. 10, unnecessary portions are etched by a known photolithography method to form second wirings 160a and 160b, 161 or the like may be formed.

Alternatively, if the element does not require much precision, these wirings may be formed directly by a vacuum evaporation method or the like using a metal mask. Then, FIG.
As shown in (D), the film 162 of the pixel electrode of the liquid crystal display was selectively formed to form a liquid crystal pixel.

The number of masks used in the above steps is
There are five sheets for forming the semiconductor region 153, forming the gate electrode and wiring, forming the photoresist 157, forming the second wiring, and forming the pixel electrode. Focusing on the TFT of this embodiment, in addition to the normal impurity region 164, there is an offset region due to a geometrical deviation between the gate electrode and the impurity region. A doped region 165 has been formed. The usefulness of providing such an amorphous portion is described in "Insulated Gate Type Semiconductor Device and its Fabrication" filed on Aug. 26, 1991 by the Semiconductor Energy Laboratory Co., Ltd. The method is described in detail in “Method” and will not be described here.

A polyimide film was formed as an alignment film of a liquid crystal material on a substrate (hereinafter referred to as a first substrate) manufactured by the above steps. The surface of this polyimide film is treated by a known rubbing method, and after forming a transparent electrode on the other second substrate, an alignment film is formed in the same manner as the first substrate,
Rubbing treatment was performed. These substrates were adhered so that the rubbing directions were parallel to each other to produce a liquid crystal cell.

Thereafter, a nematic liquid crystal material is injected into the liquid crystal cell, and two polarizing plates are arranged so that the polarization axes are crossed on both sides of the liquid crystal cell, and the rubbing direction of both substrates is 45 degrees. To complete the liquid crystal electro-optical device. This NON-TWISTED-NEMATIC
In the liquid crystal electro-optical device, when turned off, light (white) is displayed due to the birefringence of the liquid crystal material, and when turned on, dark (black) is displayed because the liquid crystal molecules stand in a direction perpendicular to the substrate. The application of the semiconductor device of the present invention can be applied not only to the above-described liquid crystal electro-optical device, but also to other types of liquid crystal electro-optical devices, for example, antiferroelectric liquid crystal electro-optical devices,
Further, the present invention can be applied to other electric and electronic devices.

[0075]

According to the present invention, a TFT can be manufactured with a smaller number of masks than in the prior art. Further, according to the present invention, a TFT having higher reliability can be manufactured although the number of masks is not different from the conventional one. In particular, an object of the present invention is to improve the yield of TFTs. In particular, the formation of the source and drain electrodes of a TFT
This is an advanced operation that requires an accuracy of 1 μm or less, and the number of defective panels generated by this process is significantly larger than those generated by other processes.

The number of defects is determined by T
It increased as the amount of FT increased and as the area of the panel increased. That is, both the formation of the holes in the electrodes and the formation of the electrode wiring required extremely advanced techniques. According to the present invention, for example, since it is not necessary to form a hole in an electrode, the yield is mainly only to form an electrode wiring. For example, assuming that the rate of occurrence of defects in forming holes and forming electrode wirings is 20%, if these two steps are performed, only 64% of non-defective products are obtained. Since no process is required, 80% is non-defective.

On the other hand, especially in a liquid crystal display,
The occurrence of a defect due to a short circuit between the gate wiring and the signal line (source / drain wiring) was a serious problem. This is directly a defect due to a problem in handling, but indirectly is considered to be a defect of the interlayer insulator. That is, the silicon oxide used as the interlayer insulator cannot completely cover the undulations of the wiring, and its thickness may be thick or thin. Particularly, the film is not formed on the side surface of the gate wiring as the lower wiring. It has become thin. On the other hand, a film having a sufficient thickness was formed on the upper surface of the lower wiring. When the upper wiring was formed in this state, a short circuit was likely to occur on the side surface of the lower wiring. However, according to the present invention, such a problem is solved because the anodic oxide insulating film having substantially the same thickness on both the side surface and the upper surface of the lower wiring can be formed. If an interlayer insulating film is formed after the formation of the anodic oxide insulating film, the insulating effect can be further enhanced.

[Brief description of the drawings]

FIG. 1 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 2 shows an example of a pixel of a liquid crystal display manufactured according to the present invention.

FIG. 3 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 4 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 5 shows a pixel example of a liquid crystal display manufactured according to the present invention.

FIG. 6 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 7 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 8 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 9 shows an example of manufacturing a liquid crystal display panel according to the present invention.

FIG. 10 shows a manufacturing process of the TFT according to the present embodiment.

[Explanation of symbols]

 Reference Signs List 101 Insulating substrate 102 Passivation film 103 Semiconductor region 104 Gate insulating film 105 First wiring (gate wiring) 106 Gate electrode 107 First wiring (storage capacitor wiring) 108 Impurity region 109 Anodized insulating film 110 Second wiring ( Drain electrode / wiring) 111 Second wiring (source electrode / wiring) 112 Pixel electrode / wiring

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideki Uojichi 398 Hase, Atsugi-shi, Kanagawa Inside Semiconductor Energy Research Institute Co., Ltd.

Claims (20)

[Claims] A first insulating film is formed in contact with a glass substrate, and a second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases. Forming a semiconductor film containing silicon in contact with the second insulating film by a CVD method using silane as a source gas without exposing the second insulating film to the atmosphere; A method for manufacturing a thin film transistor. 2. A first insulating film is formed in contact with a glass substrate, and a second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases. Forming a semiconductor film containing silicon in contact with the second insulating film by a CVD method using silane as a source gas without exposing the second insulating film to the atmosphere; A method for manufacturing a thin film transistor, comprising: adding a compound containing chlorine or fluorine to the source gas of the second insulating film. 3. A first insulating film is formed in contact with a glass substrate, and a second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases. Forming a semiconductor film containing silicon in contact with the second insulating film by a CVD method using silane as a source gas without exposing the second insulating film to the atmosphere; A method for manufacturing a thin film transistor, comprising: adding a compound containing chlorine or fluorine and silicon to the source gas of the second insulating film. 4. A first substrate made of silicon nitride in contact with a glass substrate.
And forming a second insulating film made of silicon oxide in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and exposing the second insulating film to the atmosphere. A method for manufacturing a thin film transistor, wherein a semiconductor film containing silicon is formed in contact with the second insulating film by a CVD method using silane as a source gas without contact, and the semiconductor film is crystallized. 5. A first substrate made of silicon nitride in contact with a glass substrate.
And forming a second insulating film made of silicon oxide in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and exposing the second insulating film to the atmosphere. Forming a semiconductor film containing silicon in contact with the second insulating film by CVD using silane as a source gas without contacting the semiconductor film, and crystallizing the semiconductor film; A method for manufacturing a thin film transistor, characterized in that a compound containing chlorine or fluorine is added to a source gas of the insulating film. 6. A first substrate made of silicon nitride in contact with a glass substrate.
And forming a second insulating film made of silicon oxide in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and exposing the second insulating film to the atmosphere. Forming a semiconductor film containing silicon in contact with the second insulating film by CVD using silane as a source gas without contacting the semiconductor film, and crystallizing the semiconductor film; A method for manufacturing a thin film transistor, wherein a compound containing chlorine or fluorine and silicon is added to a source gas of the insulating film. 7. A first substrate made of silicon nitride in contact with a glass substrate.
A second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and is formed in contact with the second insulating film. A method for manufacturing a thin film transistor in which a semiconductor film containing silicon is formed by a CVD method using silane as a source gas and the semiconductor film is crystallized. In a multi-chamber film formation apparatus, the glass substrate is exposed to air. Forming the second insulating film and the semiconductor film without forming the thin film transistor. 8. A first substrate made of silicon nitride in contact with a glass substrate.
A second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and is formed in contact with the second insulating film. A method for manufacturing a thin film transistor in which a semiconductor film containing silicon is formed by a CVD method using silane as a source gas and the semiconductor film is crystallized. In a multi-chamber film formation apparatus, the glass substrate is exposed to air. Wherein the second insulating film and the semiconductor film are formed without adding a compound containing chlorine or fluorine to a source gas of the second insulating film. 9. A first substrate made of silicon nitride in contact with a glass substrate.
A second insulating film made of silicon oxide is formed in contact with the first insulating film by a CVD method using silane and oxygen as source gases, and is formed in contact with the second insulating film. A method for manufacturing a thin film transistor in which a semiconductor film containing silicon is formed by a CVD method using silane as a source gas and the semiconductor film is crystallized. In a multi-chamber film formation apparatus, the glass substrate is exposed to air. Forming the second insulating film and the semiconductor film without adding a compound containing chlorine or fluorine and silicon to a source gas of the second insulating film. Production method. 10. The method according to claim 1, wherein the first insulating film is formed in the film forming apparatus, and the second insulating film is formed in the film forming apparatus without exposing the first insulating film to the atmosphere. The method for manufacturing a thin film transistor according to claim 7, wherein: 11. A silane having a purity of 6N or more is used as a source gas for the semiconductor film.
11. The method for manufacturing a thin film transistor according to any one of items 10 to 10. 12. The method for manufacturing a thin film transistor according to claim 1, wherein the second insulating film is formed without exposing the first insulating film to the air. 13. The method for manufacturing a thin film transistor according to claim 1, wherein the first insulating film is formed by a CVD method. 14. The method for manufacturing a thin film transistor according to claim 1, wherein the first insulating film is formed by a plasma CVD method. 15. The method for manufacturing a thin film transistor according to claim 1, wherein the second insulating film is formed by a plasma CVD method. 16. The method according to claim 1, wherein the semiconductor film is formed by a plasma CVD method. 17. The method according to claim 1, wherein the thin film transistor is a top-gate transistor. 18. A liquid crystal display, wherein a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1 is provided in a pixel. 19. A liquid crystal display using a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1 in a CMOS circuit. 20. A semiconductor integrated circuit comprising a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1.