JP3024387B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a material used for a gate electrode and a wiring of a thin film transistor (hereinafter referred to as a TFT) for forming an image display device in combination with a semiconductor device, especially a liquid crystal or the like.

[0002]

2. Description of the Related Art Liquid crystal display devices are promising among thin displays because of their characteristics such as low power consumption and easy full-color display. In recent years, the development of large display screens has been actively conducted.

The structure of a conventional TFT will be described with reference to FIG. A gate electrode 2 made of, for example, aluminum is formed on a glass substrate 1, a first gate insulating layer 3 of aluminum oxide is formed so as to cover the gate electrode 2, and an amorphous silicon semiconductor layer 5 is formed of silicon nitride. The source and drain electrodes 7a and 7b made of titanium and aluminum are formed through the gate insulating film 4 and the amorphous silicon semiconductor layer 6a containing phosphorus;
A transparent display electrode 8 formed through the gate electrode 6b and applying a voltage to the liquid crystal is connected to the drain electrode 7b.

Next, a brief description will be given of a manufacturing process of the TFT having the above-described structure. First, an Al film is formed on a glass substrate 1, and a gate electrode 2 is formed by photolithography. Next, a first gate insulating film 3 of aluminum oxide is formed by anodic oxidation of a necessary portion of the gate electrode 2 described above. Next, a second gate insulating film 4 made of silicon nitride (SiNx), which is a main material of the TFT, an amorphous silicon (a-Si) semiconductor layer 5, and n for obtaining ohmic contact between the source and drain electrodes and the semiconductor layer ^{A +} -a-Si layer is continuously formed by a plasma CVD method, and an a-Si layer and an n ⁺ -a-Si layer other than those where a TFT is formed are removed by etching.

Next, an iTO film is formed, and a transparent display electrode 8 is formed by photolithography. Next, in order to expose the surface of the gate electrode wiring and obtain electrical contact with the source wiring forming source and drain electrodes, an opening is provided in the silicon nitride gate insulating film.
The source and drain electrodes 7a and 7b are formed by photolithography, and the n ⁺ -a-Si layer on the channel portion of the TFT is removed to complete the TFT.

Here, pure aluminum is used because there is a thermal process in the manufacturing process, such as when the aluminum gate electrode 2 is formed by the photolithography technique or when the insulating film 4 and the semiconductor layer 5 are formed by the plasma CVD. Hillocks (protrusions) are formed on the gate electrode, and the aluminum oxide in the anodic oxidation step cannot cover the protrusions sufficiently, thereby lowering insulation properties and causing a short circuit between row wiring and column wiring. In addition, there is a high probability that a contact failure occurs due to roughening of the Al surface at a portion where the source electrode wiring contacts the gate electrode wiring.

Conventionally, in order to prevent such defects,
As invented in Japanese Patent Application No. 3-347182 filed by the present applicant, a gate electrode is formed using Al to which an anodic oxidizable refractory metal is added as an impurity, thereby suppressing hillocks of Al. The above defect was prevented by forming an anodic oxide film having an excellent insulating property.

[0008]

However, the above conventional structure has a problem that the wiring resistance is extremely increased due to the addition of the impurity of the high melting point metal to aluminum (see FIG. 2). . SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and prevents hillocks of Al without increasing the wiring resistance of the electrodes, and enables an anodic oxide film having a high interlayer insulating property to be formed as a gate insulating film, thereby achieving high performance. Accordingly, a semiconductor device having a high yield can be provided.

[0009]

According to the present invention, in order to solve the above-mentioned problems, a row wiring or a gate electrode can be made of aluminum or pure aluminum to which silicon and / or copper or both are added in a lower layer, and anodized in an upper layer. Made of aluminum doped with a high refractory metal as an impurity 2
It is formed using a layer structure. The refractory metals are tantalum, titanium, molybdenum, tungsten, hafnium,
It is characterized by being one of niobium, zirconium and vanadium.

[0010]

According to the above technical means of the present invention, a gate electrode is formed by a structure in which aluminum added with silicon and / or copper or both, or pure aluminum is disposed below aluminum added with a high melting point metal. The wiring resistance is reduced by the conventional aluminum with added high melting point metal.
It can be reduced as compared with the case where a layer is used. Moreover, hillocks due to the heat process during the manufacturing process are suppressed by aluminum to which an anodically oxidizable high melting point metal is added as an impurity in the upper layer, and the added impurity itself becomes an oxide by anodic oxidation, so that good insulation properties are obtained. Since an anodic oxide film can be formed, short circuit failure between the gate electrode and the source and drain electrodes can be prevented. Further, since the hillock does not occur, the contact failure of the source electrode wiring with the gate electrode wiring can be prevented.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor device T of this embodiment.
FIG. 2 shows a cross-sectional view of a main part configuration of the FT. 1a on glass substrate 11
A gate electrode made of aluminum 12a containing t% Si and aluminum 12b containing 2 at% Ta is formed, and an aluminum oxide gate insulating layer 13 is formed by anodic oxidation to cover the gate electrode. A semiconductor layer 15 is formed via a silicon nitride gate insulating film 14, a transparent display electrode 18 for applying a voltage to a liquid crystal is formed, and source and drain electrodes 17a and 17b made of titanium and aluminum are made of amorphous silicon containing phosphorus. The drain electrode 17b is formed via the semiconductor layers 16a and 16b, and is connected to the transparent display electrode 18.

A method of manufacturing a TFT having this configuration will be briefly described. 1 at% Si on glass substrate 11
-Added aluminum film (100 nm thick), and 2 at% of tantalum, a high melting point metal, is further superposed thereon.
An added aluminum film (thickness: 200 nm) is formed by DC sputtering, and processed by photolithography to form a gate electrode as shown in the figure.

Next, the surface of the gate electrode is anodized to form an aluminum oxide gate insulating film (150 nm thick).
13 is formed. Here, the anodic oxidation solution was prepared by mixing an aqueous solution obtained by dissolving 3% of ammonium borate in water and ethylene glycol at a ratio of 1: 9, and adjusting the pH to 6 to 10.
A neutral one adjusted to 7 was used. Further, the temperature of the anodizing solution was kept at 30 ° C., the anodizing voltage was 105 V, and the anodizing current was 5 mA / cm ^2, and the anodizing was performed.

Next, a second gate insulating film made of silicon nitride (SiNx), which is a main material of the TFT, an amorphous silicon (a-Si) semiconductor layer, and an amorphous silicon semiconductor layer containing phosphorus are formed at a frequency of 13.56 MHz. Are successively formed by the plasma CVD method. Subsequently, the amorphous silicon semiconductor layer and the amorphous silicon semiconductor layer containing phosphorus are formed into an island shape using a mixed solution of hydrofluoric acid and nitric acid.

Next, a film of iTO is formed, and a transparent display electrode is formed by photolithography. Next, a film is formed in the order of Ti and Al, source and drain electrodes are formed by photolithography technology, and finally, an amorphous silicon semiconductor containing phosphorus remaining on the amorphous silicon semiconductor layer in the TFT channel portion. After removing the layer, the T
FT is completed.

According to this embodiment, as shown in FIG. 2, the wiring resistance can be reduced to half or less of the wiring resistance of the aluminum single layer to which tantalum is added.

Further, since the gate electrode is formed using aluminum containing 2 at% of Ta as the upper layer, generation of hillocks can be suppressed even after the heat treatment in the photolithography step, and the formation using the subsequent anodic oxidation method is performed. Of aluminum oxide is improved. The leakage current of the aluminum oxide formed by the anodic oxidation method of this embodiment is as follows.
The leakage current is equivalent to the leakage current of aluminum oxide formed by anodizing Al having a purity of 99.99%, a short circuit between the gate electrode and the source and drain electrodes can be prevented, and the yield can be improved. Furthermore, even after forming SiNx at 300 ° C., almost no hillocks are generated, and the surface of Al at the contact portion between the gate electrode wiring and the source electrode wiring is not roughened.
Good electrical contact was obtained.

Next, another embodiment will be described. In this embodiment, pure aluminum is used instead of the aluminum 12a to which 1 at% of Si is added in the above-described embodiment (FIG. 1). Other configurations and manufacturing methods are the same as those of the above-described embodiment.

According to this embodiment, as shown in FIG. 2, the resistance can be further reduced as compared with the previous embodiment, and is about １ ／ of the wiring resistance of the aluminum single layer to which tantalum is added. Can be reduced to

Further, by adopting the manufacturing method as in this embodiment, even if the high-melting-point metal remains on the surface without being etched when etching the upper-layer Al to which the high-melting-point metal is added, the lower-layer pure aluminum Has the effect of automatically removing the remaining high-melting-point metal at the same time that the metal is etched.

Next, another embodiment of the present invention will be described. FIG. 3 is a cross-sectional view of a main part configuration of the TFT of this embodiment. As shown in FIG. 3, the TFT of this embodiment has a passivation silicon nitride film 39 formed on an amorphous silicon semiconductor layer forming a channel portion, and the other structure is the same as that of the first or second embodiment described above. The configuration is similar to that of the example.

According to this embodiment, as in the previous embodiment, hillocks of the gate electrode can be prevented without increasing the wiring resistance, and an anodic oxide film having a low leakage current can be formed. This has an effect that a short-circuit defect is prevented and a TFT in which a passivation film is formed in a channel portion can be manufactured.

In the embodiments of the present invention, the description has been made mainly on the use of Ta as the refractory metal to be added to aluminum. However, Ti, Mo, W, Hf, Nb, Zr, V
Has the same effect.

Also, the case where aluminum to which Si is added is used as the lower aluminum has been described.
Similar effects can be obtained by using aluminum to which copper is added or aluminum to which both Si and copper are added.

[0026]

As described above, the wiring resistance is increased by forming the gate electrode using aluminum or pure aluminum to which Si is added in the lower layer and aluminum containing an anodic oxidizable high melting point metal in the upper layer. A hillock can be prevented without causing anodic oxide film with a low leakage current, so that a short circuit between the gate electrode and the source electrode can be prevented, and a contact failure between the gate electrode wiring and the source electrode wiring can be prevented. Therefore, there is an effect that a semiconductor device with a high production yield can be provided. Further, by disposing pure aluminum in the lower layer, there is also an effect that the gate electrode can be formed by etching without leaving the high melting point metal which cannot be etched on the substrate surface. Further, since the yield of semiconductor devices can be improved, there is also an effect that the manufacturing cost of a liquid crystal display device using the same can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing the specific resistance of an aluminum single layer to which Ta is added and various two-layer structures with respect to the amount of Ta added.

FIG. 3 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a sectional view of a main part of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Glass substrate 12a Pure aluminum or aluminum which added Si 12b High melting point metal addition aluminum 13 Aluminum oxide insulating layer 14 Silicon nitride insulating layer 15 Amorphous silicon semiconductor layer 17a, 7b Source and drain electrode 18 Transparent display electrode 39 Passivation film

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Mamoru Takeda 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-1-120068 (JP, A) JP-A-64-35421 (JP, A) JP-A-3-35524 (JP, A) JP-A-4-116524 (JP, A) JP-A-4-299865 (JP, A) JP-A-4-329675 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 29/786 G02F 1/1368

Claims (4)

(57) [Claims] 1. A method according to claim 1 , wherein the lower layer comprises at least silicon and copper.
Aluminum or pure aluminum
The upper layer is made of an anodically oxidizable refractory metal as an impurity.
-Layer structure made of aluminum added at 6 at% or less
A conductive layer having a structure, and anodizing the surface of the conductive layer
And an oxide film formed by the method described above . 2. The method according to claim 1, wherein the lower layer is made of silicon and copper on one main surface of the substrate .
A first conductor layer having a two-layer structure is selectively formed of aluminum to which at least one is added, or pure aluminum, and an upper layer made of aluminum to which an anodically oxidizable refractory metal is added as an impurity, An oxide film is formed on the surface of the first conductor layer by anodic oxidation, and a first non-single-crystal semiconductor layer containing silicon as a main component is in contact with the first conductor layer via an insulating thin film layer. A second conductive layer which is selectively formed so as to partially overlap with the first non-single-crystal semiconductor layer through a second non-single-crystal semiconductor layer mainly containing silicon containing phosphorus. A semiconductor device which is formed so as to partially overlap. 3. The high melting point metal is Ta, Ti, Mo, W, H.
f, Nb, Zr, or V
The semiconductor device according to claim 1 . 4. The semiconductor device according to claim 2, wherein the second insulating thin film layer is selectively formed so as to partially overlap the first non-single-crystal semiconductor layer containing silicon as a main component. Semiconductor device.