JPH02159730A - Formation of thin film transistor - Google Patents
Formation of thin film transistorInfo
- Publication number
- JPH02159730A JPH02159730A JP31565488A JP31565488A JPH02159730A JP H02159730 A JPH02159730 A JP H02159730A JP 31565488 A JP31565488 A JP 31565488A JP 31565488 A JP31565488 A JP 31565488A JP H02159730 A JPH02159730 A JP H02159730A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- concentration impurity
- mask
- layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 19
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 78
- 239000012535 impurity Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 51
- 238000005468 ion implantation Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000007943 implant Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタの形成方法に関し、特にソー
ス・ドレイン領域が高濃度不純物領域のチャンネル側に
低濃度不純物領域が形成された構造とされる所謂ＬＤＤ
（ライトリイ・ドープト・ドレイン）構造の薄膜トラ
ンジスタの形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a thin film transistor, and particularly to a method for forming a thin film transistor, in particular a so-called thin film transistor in which the source/drain region has a structure in which a low concentration impurity region is formed on the channel side of a high concentration impurity region. LDD
The present invention relates to a method for forming a thin film transistor having a (lightly doped drain) structure.
本発明は、所謂ＬＤＤ構造の薄膜トランジスタの形成方
法において、ゲート電極層のパターニングの後、ゲート
絶縁膜を残したまま低濃度不純物領域を形成するための
イオン注入を行い、続いてゲート電極層の隣接領域を覆
うマスク層をマスクとして高濃度不純物領域を形成する
イオン注入を行うことにより、層間絶縁膜から低濃度不
純物領域への不純物の拡散を防止するものである。The present invention relates to a method for forming a thin film transistor with a so-called LDD structure, in which after patterning a gate electrode layer, ion implantation is performed to form a low concentration impurity region while leaving the gate insulating film, and then adjacent to the gate electrode layer is implanted to form a low concentration impurity region. By performing ion implantation to form a high concentration impurity region using a mask layer covering the region as a mask, diffusion of impurities from the interlayer insulating film to the low concentration impurity region is prevented.
〔従来の技術］
薄膜トランジスタのリークを小さくし、その耐圧を高く
するためには、ソース・ドレイン領域が高濃度不純物領
域のチャンネル側に低濃度不純物領域が形成された構造
とされる所謂ＬＤＤ構造とすることが最適である。[Prior Art] In order to reduce leakage and increase the withstand voltage of a thin film transistor, a so-called LDD structure is used in which the source/drain regions have a structure in which a low concentration impurity region is formed on the channel side of a high concentration impurity region. It is best to do so.
第２図ａ及び第２図すは、このような薄膜トランジスタ
の形成方法を示す断面図である。まず、絶縁基板２１上
に所要のサイズで半導体層２２が形成され、その上部の
ゲート絶縁膜２３を介してケート電極層２４が形成され
る。ゲート電極層２４とゲート絶縁膜２３は、セルファ
ラインでパタニングされ、そのゲート電極層２４に隣接
した領域をマスクするようにレジスト層２５が形成され
る。このレジスト層２５をマスクとしながら、高濃度不
純物領域を形成するためのイオン注入が行われる（第２
図ａ）。FIGS. 2A and 2S are cross-sectional views showing a method for forming such a thin film transistor. First, a semiconductor layer 22 of a required size is formed on an insulating substrate 21, and a gate electrode layer 24 is formed thereon with a gate insulating film 23 interposed therebetween. The gate electrode layer 24 and the gate insulating film 23 are patterned with self-aligned lines, and a resist layer 25 is formed so as to mask a region adjacent to the gate electrode layer 24. Using this resist layer 25 as a mask, ion implantation is performed to form a high concentration impurity region (second
Diagram a).
次に、マスクとされたレジスト層２５を除去し、全面に
低濃度不純物領域２７を形成する濃度でイオン注入を行
う。イオン注入後、層間絶縁膜として応力が小さくＮａ
イオンストッパーになるＰＳＧ膜２６を全面に形成し、
アニールを行って、薄膜トランジスタを完成する（第２
図ｂ）。Next, the resist layer 25 used as a mask is removed, and ions are implanted at a concentration to form a low concentration impurity region 27 over the entire surface. After ion implantation, Na is used as an interlayer insulating film with low stress.
A PSG film 26 that serves as an ion stopper is formed on the entire surface,
Perform annealing to complete the thin film transistor (second
Figure b).
ＬＤＤ構造の薄膜トランジスタにおいては、ソス・ドレ
イン領域の低濃度不純物領域２７の不純物の濃度が低い
方が、特性に優れることが確かめられている。In a thin film transistor having an LDD structure, it has been confirmed that the lower the impurity concentration in the low concentration impurity region 27 in the sos/drain region, the better the characteristics.
ところが、層間絶縁膜をＰＳＧ膜２６で構成した場合に
は、その低濃度不純物領域２７にリンが拡散してしまい
、その不純物濃度が高くなることになる。However, if the interlayer insulating film is formed of the PSG film 26, phosphorus will diffuse into the low concentration impurity region 27, resulting in an increase in the impurity concentration.
また、層間絶縁膜をＣＶＤ５ ｉ Ｏ□膜とＰ’Ｓ Ｇ
膜からなるように同−ＣＶＤ装置を以て構成すると、Ｃ
ＶＤ５ ｉ○２膜に少量のリンが含まれてしまい、同様
に低濃度不純物領域２７の不純物濃度が高くなる。In addition, the interlayer insulating film is made of CVD5 i O□ film and P'S G.
When the same CVD apparatus is configured to consist of a film, C
A small amount of phosphorus is contained in the VD5 i○2 film, and the impurity concentration of the low concentration impurity region 27 similarly increases.
そこで、本発明は上述の技術的な課題に鑑み、層間絶縁
膜から低濃度不純物領域への不純物の拡散を防止するよ
うな薄膜トランジスタの形成方法の提供を目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a method for forming a thin film transistor that prevents diffusion of impurities from an interlayer insulating film to a low concentration impurity region.
行う。その後、マスク層の除去や、ＰＳＧ膜等の層間絶
縁膜の全面への形成、不純物拡散領域のアニール等が行
われる。conduct. Thereafter, the mask layer is removed, an interlayer insulating film such as a PSG film is formed on the entire surface, and the impurity diffusion region is annealed.
〔課題を解決するための手段］
上述の目的を達成するために、本発明の薄膜トランジス
タの形成方法は、絶縁基板上に半導体層を形成し、その
半導体層上に該半導体層を被覆するゲート絶縁膜を形成
する。半導体層としては、例えばポリシリコン層を形成
できる。そのゲート絶縁膜上にはゲート電極層が形成さ
れ、そのゲート電極層がパターニングされる。次に、低
濃度不純物領域を上記半導体層に形成するためのイオン
注入を上記ゲート電極層をマスクとしながら行う。[Means for Solving the Problems] In order to achieve the above object, the method for forming a thin film transistor of the present invention includes forming a semiconductor layer on an insulating substrate, and forming a gate insulator covering the semiconductor layer on the semiconductor layer. Forms a film. For example, a polysilicon layer can be formed as the semiconductor layer. A gate electrode layer is formed on the gate insulating film, and the gate electrode layer is patterned. Next, ion implantation for forming a low concentration impurity region in the semiconductor layer is performed using the gate electrode layer as a mask.
次に、上記ゲート電極層の隣接領域を覆うマスク層を形
成する。このマスク層は、例えばレジスト層によって構
成され、このマスク層のパターンを反映させて、上記ゲ
ート絶縁膜をパターニングすることが好ましい。そのマ
スク層をマスクとして高濃度不純物領域を形成するため
のイオン注入を（作用〕
本発明の薄膜トランジスタの形成方法では、ゲト絶縁膜
は、ゲート電極層のパターニング時にパターニングされ
ず、少なくともゲート電極層の隣接領域で最後まで残存
する。このため最終的に層間絶縁膜と低濃度不純物領域
の間には、ゲート絶縁膜が残ることになり、不純物の拡
散の問題が解決されることになる。Next, a mask layer is formed to cover a region adjacent to the gate electrode layer. This mask layer is formed of, for example, a resist layer, and the gate insulating film is preferably patterned to reflect the pattern of this mask layer. Ion implantation for forming a high concentration impurity region using the mask layer as a mask (function) In the method for forming a thin film transistor of the present invention, the gate insulating film is not patterned during patterning of the gate electrode layer; The gate insulating film remains until the end in the adjacent region.Therefore, the gate insulating film ultimately remains between the interlayer insulating film and the low concentration impurity region, which solves the problem of impurity diffusion.
［実施例］ 本発明の好適な実施例を図面を参照しながら説明する。[Example] Preferred embodiments of the present invention will be described with reference to the drawings.
本実施例は、ＬＤＤ構造のｎチャンネル薄膜トランジス
タを形成する例である。以下、本実施例をその工程に従
って第１図ａ〜第１図ｅを参照しながら説明する。This example is an example of forming an n-channel thin film transistor with an LDD structure. Hereinafter, this embodiment will be explained according to its steps with reference to FIGS. 1a to 1e.
まず、絶縁基板１上に薄膜のポリシリコン層２を形成し
、これを所定のサイズにパターニングして素子領域とす
る。次に、そのポリシリコン層２を被覆するように、ゲ
ート絶縁膜３を形成する。First, a thin polysilicon layer 2 is formed on an insulating substrate 1 and patterned to a predetermined size to form an element region. Next, a gate insulating film 3 is formed to cover the polysilicon layer 2.
ここで、ポリシリコン層２の膜厚はおよそ４００人であ
り、ゲート絶縁膜３の膜厚はおよそ５００人程皮表ある
。Here, the thickness of the polysilicon layer 2 is about 400 layers, and the thickness of the gate insulating film 3 is about 500 layers.
次に、第１図ａに示すように、全面にポリシリコン層か
らなるゲート電極層４を形成し、所要のゲート長、ゲー
ト幅となるサイズにパターニングする。このパターニン
グには、絶縁膜とシリコンとで選択性の有る異方性エツ
チングが用いられる。Next, as shown in FIG. 1a, a gate electrode layer 4 made of a polysilicon layer is formed on the entire surface and patterned to a size that provides the required gate length and gate width. This patterning uses anisotropic etching that is selective between the insulating film and silicon.
従って、ゲート電極層４の下部のゲート絶縁膜３はパタ
ーニングされない。Therefore, the gate insulating film 3 below the gate electrode layer 4 is not patterned.
このようなゲート電極層４のパターニングの後、パター
ニングされたゲート電極層４をマスクとして、全面に低
濃度不純物領域５を形成するためのイオン注入を行う。After patterning the gate electrode layer 4 in this manner, ion implantation is performed to form a low concentration impurity region 5 over the entire surface using the patterned gate electrode layer 4 as a mask.
このイオン注入で、パターニングされたゲート電極層４
の下部以外のポリシリコン層２の領域に、低濃度に不純
物が打ち込まれる。このイオン注入の条件は、７０ｋｅ
Ｖ、１ｘ１０＋ｆｆｃｍ−２程度のものとされ、最終的
に低濃度不純物領域５の不純物濃度は１×１０１ｂ〜１
×１０Ｉ７１０ｌ７程度に設定される。Through this ion implantation, the patterned gate electrode layer 4
Impurities are implanted at a low concentration into regions of the polysilicon layer 2 other than the lower part of the polysilicon layer 2 . The conditions for this ion implantation are 70ke
V, approximately 1x10+ffcm-2, and the final impurity concentration of the low concentration impurity region 5 is 1x101b~1
It is set to approximately ×10I710l7.
次に、第１図すに示すように、上記ゲート電極層４の隣
接領域７を覆うマスク層６を形成する。Next, as shown in FIG. 1, a mask layer 6 covering the adjacent region 7 of the gate electrode layer 4 is formed.
マスク層６ば例えばフォトレジストを材料とする。The mask layer 6 is made of, for example, photoresist.
ここで隣接領域とは、ソース・ドレイン領域の高濃度不
純物領域がチャンネル形成領域からオフセットされる領
域であり、ポリシリコン層２が低濃度不純物領域５のま
まにされる領域である。Here, the adjacent region is a region where the high concentration impurity region of the source/drain region is offset from the channel forming region, and is a region where the polysilicon layer 2 is left as the low concentration impurity region 5.
次に、第１図Ｃに示すように、そのマスク層５を用いて
ゲート絶縁膜３を異方性エツチングによりエツチングす
る。すると、ゲート絶縁膜３はゲート電極層４の直下及
びマスク層６の下部の隣接領域７以外で除去され、ポリ
シリコン層２が露出する。このように高濃度不純物領域
となる領域のゲート絶縁膜３を除去した方が、高濃度に
イオン注入する場合には好ましい。Next, as shown in FIG. 1C, the gate insulating film 3 is etched using the mask layer 5 by anisotropic etching. Then, the gate insulating film 3 is removed except for the adjacent region 7 immediately below the gate electrode layer 4 and below the mask layer 6, and the polysilicon layer 2 is exposed. It is preferable to remove the gate insulating film 3 in a region that will become a high concentration impurity region in this way when performing ion implantation at a high concentration.
次に、第１図ｄに示すように、上記マスク層６をマスク
として高濃度不純物領域８を形成するためのイオン注入
を行う。このイオン注入の条件は、例えば４０ｋｅＶ、
２Ｘ１０１５ｃ＋ｎ−２とされる。このイオン注入によ
り、ゲート電極層４の直下及び隣接領域７以外のポリシ
リコン層２に、ソース・ドレイン領域となる高濃度不純
物領域８が形成されることになる。Next, as shown in FIG. 1d, ion implantation is performed to form high concentration impurity regions 8 using the mask layer 6 as a mask. The conditions for this ion implantation are, for example, 40 keV,
2X1015c+n-2. By this ion implantation, high-concentration impurity regions 8 that will become source/drain regions are formed in the polysilicon layer 2 other than directly under the gate electrode layer 4 and in the adjacent region 7 .
次に、第１図ｅに示すように、上記マスク層６が除去さ
れ、全面に眉間絶縁膜であるＰＳＧ膜９が形成される。Next, as shown in FIG. 1e, the mask layer 6 is removed and a PSG film 9, which is an insulating film between the eyebrows, is formed on the entire surface.
隣接領域７の低濃度不純物領域５上にはゲート絶縁膜３
が形成されているため、そのＰＳＧ膜９は低濃度不純物
領域５には、直接に接続しない。従って、リン等の拡散
は防止されることになる。以下、ソース・ドレイン領域
のアニルや、コンタクトボールの形成、配線層の形成等
を行って薄膜トランジスタを形成する。A gate insulating film 3 is formed on the low concentration impurity region 5 of the adjacent region 7.
is formed, the PSG film 9 is not directly connected to the low concentration impurity region 5. Therefore, diffusion of phosphorus and the like is prevented. Thereafter, annealing of the source/drain regions, formation of contact balls, formation of wiring layers, etc. are performed to form a thin film transistor.
このように本実施例の薄膜トランジスタの形成方法では
、ゲート電極層とセルファラインでゲート絶縁膜をパタ
ーニングするのではなく、マスク層６によりゲート電極
層の隣接領域７まで、ゲート絶縁膜３を延在させている
。このため、層間絶縁膜（ＰＳＧ膜９）から低濃度不純
物領域５へのリン等の不純物の拡散を防止することがで
き、素子の特性の変動を未然に防止することができる。In this way, in the method for forming a thin film transistor of this embodiment, the gate insulating film 3 is extended to the adjacent region 7 of the gate electrode layer using the mask layer 6, instead of patterning the gate insulating film with the gate electrode layer and the self-alignment line. I'm letting you do it. Therefore, it is possible to prevent impurities such as phosphorus from diffusing from the interlayer insulating film (PSG film 9) to the low concentration impurity region 5, and it is possible to prevent variations in device characteristics.
また、低濃度不純物領域５の表面は、ゲート絶縁膜３に
覆われるため、その界面特性は良好となる。Further, since the surface of the low concentration impurity region 5 is covered with the gate insulating film 3, its interface characteristics are good.
また、眉間絶縁膜をＣＶＤ５ｉ０２膜とｐｓｃ膜の組合
せとする場合でも、ゲート絶縁膜３が低濃度不純物領域
５まで延在されているため、多少リンがＣＶＤ５ ｉ
Ｏ□膜が含まれていても良くなり、同一のＣＶＤ装置で
の処理が可能となる。Furthermore, even when the glabellar insulating film is a combination of the CVD5i02 film and the psc film, since the gate insulating film 3 extends to the low concentration impurity region 5, some amount of phosphorus is absorbed by the CVD5i02 film.
It becomes possible to include an O□ film, and processing can be performed using the same CVD apparatus.
本発明の薄膜トランジスタの形成方法は、ゲート絶縁膜
は、ゲート電極層のパターニング時にパターニングされ
ず、少なくともゲート電極層の隣接領域で最後まで残存
する。従って、層間絶縁膜からソース・ドレインの低濃
度不純物領域への不純物の拡散を防止することができ、
界面特性を良好にさせることが可能となる。In the method for forming a thin film transistor according to the present invention, the gate insulating film is not patterned during patterning of the gate electrode layer, and remains until the end at least in a region adjacent to the gate electrode layer. Therefore, diffusion of impurities from the interlayer insulating film to the low concentration impurity regions of the source and drain can be prevented.
It becomes possible to improve the interfacial properties.
第１図ａ〜第１図ｅは本発明の薄膜トランジスタの形成
方法の一例を説明するためのそれぞれ工程断面図、第２
図ａ及び第２図すは従来の薄膜トランジスタの形成方法
の一例を説明するためのそれぞれ工程断面図である。
１・・・絶縁基板
２・・・ポリシリコン層
３・・・ゲート絶縁膜
４・・・ゲート電極層
５・・・低濃度不純物領域
６・・・マスク層
７・・・隣接領域
８・・・高濃度不純物領域
９・・・ＰＳＧ膜FIGS. 1a to 1e are process cross-sectional views and FIG.
Figures a and 2 are process cross-sectional views for explaining an example of a conventional method for forming a thin film transistor. 1... Insulating substrate 2... Polysilicon layer 3... Gate insulating film 4... Gate electrode layer 5... Low concentration impurity region 6... Mask layer 7... Adjacent region 8...・High concentration impurity region 9...PSG film
Claims (1)
形成する工程と、 ゲート絶縁膜上にゲート電極層を形成する工程と、 そのゲート電極層をパターニングする工程と、低濃度不
純物領域を上記半導体層に形成するためのイオン注入を
上記ゲート電極層をマスクとしながら行う工程と、 上記ゲート電極層の隣接領域を覆うマスク層を形成する
工程と、 そのマスク層をマスクとして高濃度不純物領域を形成す
るためのイオン注入を行う工程と、全面に層間絶縁膜を
形成する工程とからなることを特徴とする薄膜トランジ
スタの形成方法。[Claims] A step of forming a semiconductor layer on an insulating substrate, a step of forming a gate insulating film covering the semiconductor layer on the semiconductor layer, and a step of forming a gate electrode layer on the gate insulating film. a step of patterning the gate electrode layer; a step of performing ion implantation to form a low concentration impurity region in the semiconductor layer while using the gate electrode layer as a mask; and a mask covering an area adjacent to the gate electrode layer. A method for forming a thin film transistor comprising the steps of forming a layer, using the mask layer as a mask to perform ion implantation to form a high concentration impurity region, and forming an interlayer insulating film over the entire surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63315654A JP2934445B2 (en) | 1988-12-14 | 1988-12-14 | Method for forming thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63315654A JP2934445B2 (en) | 1988-12-14 | 1988-12-14 | Method for forming thin film transistor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9280685A Division JPH1084118A (en) | 1997-10-14 | 1997-10-14 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02159730A true JPH02159730A (en) | 1990-06-19 |
| JP2934445B2 JP2934445B2 (en) | 1999-08-16 |
Family
ID=18067973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63315654A Expired - Lifetime JP2934445B2 (en) | 1988-12-14 | 1988-12-14 | Method for forming thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2934445B2 (en) |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555573A (en) * | 1991-08-26 | 1993-03-05 | Sharp Corp | Thin film transistor and manufacture thereof |
| JPH05343430A (en) * | 1991-08-23 | 1993-12-24 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacutre of the same |
| JPH07106594A (en) * | 1993-10-01 | 1995-04-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its forming method |
| JPH07153971A (en) * | 1993-10-01 | 1995-06-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07169975A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07169974A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07202213A (en) * | 1994-01-08 | 1995-08-04 | Semiconductor Energy Lab Co Ltd | Manufacture for semiconductor integrated circuit |
| US5879969A (en) * | 1991-03-06 | 1999-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5917225A (en) * | 1992-03-05 | 1999-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor having specific dielectric structures |
| US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6335555B1 (en) | 1993-10-01 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a manufacturing method for the same |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| US6475839B2 (en) | 1993-11-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing of TFT device by backside laser irradiation |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6635900B1 (en) | 1995-06-01 | 2003-10-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor film having a single-crystal like region with no grain boundary |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2005093874A (en) * | 2003-09-19 | 2005-04-07 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| US7087962B1 (en) | 1991-12-24 | 2006-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a MOS transistor having lightly dopped drain regions and structure thereof |
| US7227229B2 (en) | 1994-02-08 | 2007-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device comprising an inverter circuit |
| JP2010098321A (en) * | 1993-09-20 | 2010-04-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US8946717B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
| CN110223990A (en) * | 2019-06-18 | 2019-09-10 | 京东方科技集团股份有限公司 | Top gate structure and preparation method thereof, array substrate, display equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0298143A (en) * | 1988-10-04 | 1990-04-10 | Fuji Xerox Co Ltd | Manufacture of ldd structure polysilicon thin film transistor |
-
1988
- 1988-12-14 JP JP63315654A patent/JP2934445B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0298143A (en) * | 1988-10-04 | 1990-04-10 | Fuji Xerox Co Ltd | Manufacture of ldd structure polysilicon thin film transistor |
Cited By (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5879969A (en) * | 1991-03-06 | 1999-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JPH05343430A (en) * | 1991-08-23 | 1993-12-24 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacutre of the same |
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
| JPH0555573A (en) * | 1991-08-26 | 1993-03-05 | Sharp Corp | Thin film transistor and manufacture thereof |
| US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
| US7087962B1 (en) | 1991-12-24 | 2006-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a MOS transistor having lightly dopped drain regions and structure thereof |
| US6476447B1 (en) | 1992-02-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device including a transistor |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US5917225A (en) * | 1992-03-05 | 1999-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor having specific dielectric structures |
| US6995432B2 (en) | 1993-01-18 | 2006-02-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions |
| US7408233B2 (en) | 1993-01-18 | 2008-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having N-channel thin film transistor with LDD regions and P-channel thin film transistor with LDD region |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| JP2010098321A (en) * | 1993-09-20 | 2010-04-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2011035430A (en) * | 1993-09-20 | 2011-02-17 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JPH07169974A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07169975A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JP4657361B2 (en) * | 1993-09-20 | 2011-03-23 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP4675433B2 (en) * | 1993-09-20 | 2011-04-20 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US6835607B2 (en) | 1993-10-01 | 2004-12-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a method for manufacturing the same |
| JPH07106594A (en) * | 1993-10-01 | 1995-04-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its forming method |
| JPH07153971A (en) * | 1993-10-01 | 1995-06-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6335555B1 (en) | 1993-10-01 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a manufacturing method for the same |
| US5962872A (en) * | 1993-10-01 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US7301209B2 (en) | 1993-10-01 | 2007-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| KR100305004B1 (en) * | 1993-10-01 | 2001-11-07 | 야마자끼 순페이 | A semiconductor device |
| US7170138B2 (en) | 1993-10-01 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR100305005B1 (en) * | 1993-10-01 | 2001-11-07 | 야마자끼 순페이 | A semiconductor device |
| US6259120B1 (en) | 1993-10-01 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US7166503B2 (en) | 1993-10-01 | 2007-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with laser irradiation |
| US6617612B2 (en) * | 1993-11-05 | 2003-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a semiconductor integrated circuit |
| US6475839B2 (en) | 1993-11-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing of TFT device by backside laser irradiation |
| US6391694B1 (en) * | 1994-01-08 | 2002-05-21 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor integrated circuit |
| US5904509A (en) * | 1994-01-08 | 1999-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using anodic oxidation |
| JPH07202213A (en) * | 1994-01-08 | 1995-08-04 | Semiconductor Energy Lab Co Ltd | Manufacture for semiconductor integrated circuit |
| US7227229B2 (en) | 1994-02-08 | 2007-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device comprising an inverter circuit |
| US6635900B1 (en) | 1995-06-01 | 2003-10-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor film having a single-crystal like region with no grain boundary |
| US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10700106B2 (en) | 2002-04-09 | 2020-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US8946717B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US8946718B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9105727B2 (en) | 2002-04-09 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US11101299B2 (en) | 2002-04-09 | 2021-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US9406806B2 (en) | 2002-04-09 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9666614B2 (en) | 2002-04-09 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10050065B2 (en) | 2002-04-09 | 2018-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US10083995B2 (en) | 2002-04-09 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10854642B2 (en) | 2002-04-09 | 2020-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
| US10527903B2 (en) | 2002-05-17 | 2020-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US10133139B2 (en) | 2002-05-17 | 2018-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US11422423B2 (en) | 2002-05-17 | 2022-08-23 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| JP2005093874A (en) * | 2003-09-19 | 2005-04-07 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| CN110223990A (en) * | 2019-06-18 | 2019-09-10 | 京东方科技集团股份有限公司 | Top gate structure and preparation method thereof, array substrate, display equipment |
| CN110223990B (en) * | 2019-06-18 | 2022-03-08 | 京东方科技集团股份有限公司 | Top gate structure, preparation method thereof, array substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2934445B2 (en) | 1999-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02159730A (en) | Formation of thin film transistor | |
| US5426062A (en) | Method for forming a silicon on insulator device | |
| JP3170610B2 (en) | Manufacturing method of vertical field effect transistor | |
| JPH0228939A (en) | Mos type transistor | |
| JPH07321212A (en) | Forming method for channel stop diffusion layer | |
| JPH08181223A (en) | Manufacture of semiconductor device | |
| US5869372A (en) | Method of manufacturing a power semiconductor device | |
| JP2727590B2 (en) | MIS type semiconductor device | |
| JPH02153538A (en) | Manufacture of semiconductor device | |
| JPH07153953A (en) | Method for forming gate electrode having polyside structure | |
| JP2892415B2 (en) | Method for manufacturing semiconductor device | |
| JP3061892B2 (en) | Method for manufacturing semiconductor device | |
| KR960019768A (en) | Transistor Manufacturing Method | |
| JPH07326753A (en) | Manufacture of semiconductor element | |
| JP2658163B2 (en) | Method of manufacturing MIS type semiconductor device | |
| JPH07193235A (en) | Semiconductor device and its manufacture | |
| JP2000307105A (en) | Semiconductor device and manufacture thereof | |
| JPH11354793A (en) | Manufacture of semiconductor device | |
| KR0144246B1 (en) | Transistor Manufacturing Method | |
| KR0135670B1 (en) | Method of manufacturing semiconductor device | |
| JPH05283680A (en) | Mos-type semiconductor device and its production | |
| KR100235622B1 (en) | Method of manufacturing shallow junction os semiconductor device | |
| KR100325444B1 (en) | Method for fabricating metal oxide semiconductor transistor of low doping drain structure | |
| KR100365750B1 (en) | Method for forming self aligned contact in semiconductor device | |
| JP2727557B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090528 Year of fee payment: 10 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090528 Year of fee payment: 10 |