JPH03203322A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form favorably silicide films on regions to be reduced their resistances add to contrive the speedup of the operation of a MIS semiconductor device by a method wherein a metal film is formed on the necessary regions of the MIS semiconductor device and a short-wavelength arc lamplight is irradiated to silicity the metal film. CONSTITUTION:A polysilicon layer 3 is laminated on a quartz substrate 1, a gate electrode 5 consisting of a polysilicon layer is formed on the layer 3 via a gate oxide film 4 and when impurities, such as phosphorus or the like, are implanted in the layer 3 using the electrode 5 as a mask, impurity regions 6, i.e., source and drain regions, are formed and when a silicon oxide film 7 is deposited on the whole surface and an entire surface etching is performed, the film 7 is left on the sidewalls of the electrode 5. When a titanium film 8 is deposited on at least the regions 6 of this MIS semiconductor device and an arc lamplight of a short wavelength is irradiated in an argon-containing atmosphere, an annealing is performed at a low temperature for a comparatively short time, a polysilicon layer of the regions 6 and the polysilicon of the electrode 5 show a silicide reaction, silicide nitride films 9 are formed, the films 9 are turned into low-resistance regions and the MIS semiconductor device becomes a semiconductor device, whose operating speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device 1, and particularly to a technique for silicidation of a metal film.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device I in which a metal film formed on at least a source/drain region of a MIS type semiconductor device on a substrate is silicided, in which the metal film is silicided using short wavelength arc lamp light. A low-resistance silicide film is formed by irradiating the anti-reflection film on the metal film with a laser beam and converting it into a silicide.
The present invention provides a semiconductor device capable of high-speed operation, and also provides a method for forming a silicide film suitable for use in a semiconductor device having a three-dimensional structure.

[Prior Art] In recent years, thin film transistors have been widely used in semiconductor devices such as liquid crystal display devices, monolithic line sensors, driving matrices for printers, and the like. As the size of the semiconductor device increases, it becomes necessary to drive the thin film transistor at high speed. In order to increase the speed of this thin film transistor, a method is known in which the source/drain regions and gate electrodes of the thin film transistor are silicided to reduce contact resistance and sheet resistance.

In the conventional silicidation method, for example,
As described in Japanese Patent No. 952, a high melting point metal film is deposited on a polysilicon layer, ions are implanted into the high melting point metal film and the polysilicon layer, and then a silicide film is formed by lamp annealing. Methods are known. For example, a titanium film or the like is used as the high melting point metal film, and its silicide film is promising as a gate electrode material in submicron LSI. However, titanium film is very active against oxygen, and oxidation occurs when furnace annealing is performed, making it difficult to form a titanium silicide film. Therefore, lamp annealing is considered effective for silicidation of titanium films, usually at 600°C or 800°C.
Rapid heating and short-time annealing is performed at a temperature of approximately C.

[Problem to be solved by the invention]

However, when a semiconductor device provided on a quartz substrate is subjected to lamp annealing as described above, the quartz substrate absorbs less energy, so the temperature of the substrate does not easily rise. Therefore, in order to cause the silicide reaction, sufficient energy must be stored in the silicide film, so it is very difficult to form a thin titanium silicide film with a thickness of about 100 OA or less.

There is also a method of siliciding the titanium film by annealing using excimer laser light, but the titanium film has a high reflectance of the laser light and the titanium film is unlikely to absorb energy. Therefore, since the energy necessary for the silicide reaction is not supplied to the titanium film, a titanium silicide film is not formed.

On the other hand, in thin film transistors, in order to reduce lateral leakage current, it is necessary to reduce the thickness of a polysilicon layer in which source/drain regions are formed to, for example, about 300 Å or less.

The source of the thinned polysilicon layer
When a titanium film is deposited on the drain region and annealed to silicide, the silicidation extends to the quartz substrate underlying the fHII transistor because the polysilicon layer is a thin film. Therefore, there is a problem in that oxygen contained in the quartz substrate mixes into the titanium silicide film, increasing the resistance value of the titanium silicide film. As described above, thin film transistors cannot achieve high-speed operation because their resistance cannot be reduced satisfactorily.

SUMMARY OF THE INVENTION The present invention has been proposed in view of the conventional situation, and an object of the present invention is to provide a method for manufacturing a semiconductor device that forms a good silicide film in a region where resistance should be reduced and enables high-speed operation. With the goal.

[! ! Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention has been proposed to achieve the above-mentioned object.

That is, the first invention of the present application forms an MIS type semiconductor device on a substrate, forms a metal film on at least the source/drain region of the MIS type semiconductor device, and irradiates the metal with short wavelength arc lamp light. It is characterized by siliciding the film. Here, the above MIS type semiconductor device is a thin film)
- It may be a transistor. Furthermore, a quartz substrate or the like is used as the base.

Furthermore, another invention of the present application forms an MIS type semiconductor device on a substrate, and at least the source and source of the MIS type semiconductor device.
sequentially forming gold IS and an antireflection film on the drain region;
The method is characterized in that the metal film is silicided by irradiation with laser light.

Here, the MIS type semiconductor device can also be a thin film transistor, and a quartz substrate or the like is used as the base.

[Function] In the first invention of the present application, arc lamp light is used as a heating source in the annealing treatment for siliciding the metal film. Arc lamp light has a large absorption band for polysilicon layers in the ultraviolet region. Therefore, the energy necessary for the silicide reaction can be accumulated in the source/drain regions made of the polysilicon layer of the MIS type semiconductor device or the above-mentioned thin film transistor. Therefore, the temperature of the polysilicon layer, which is the source/drain region, rises sufficiently, so that a low-resistance silicide film is formed on the source/drain region even if the base is a quartz substrate.

Further, in another invention of the present application, annealing is performed using laser light to silicide the metal film.

At this time, since an anti-reflection film is formed on the metal film,
Even when laser light is irradiated, reflection of the laser light on the metal film is prevented, and energy is absorbed by the metal film via the antireflection film. As a result, the metal film is silicided, and a low resistance silicide film is formed. By patterning this silicide film into a predetermined pattern, the silicide film is formed only in the region where resistance should be reduced.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Example This example is an example in which a titanium silicide film is formed on the source/drain region and gate electrode of an IJO3) transistor provided on a quartz substrate by a two-step lamp annealing method using short wavelength arc lamp light. be.

As shown in FIG. 1(a), a polysilicon layer 3 is laminated on a quartz substrate 1. As shown in FIG. A gate electrode 5 of a predetermined shape made of a polysilicon layer is formed on this polysilicon layer 3 with a gate oxide film 4 interposed therebetween.

Using this gate electrode 5 as a mask, impurities such as phosphorus or boron are ion-implanted into the polysilicon layer 3,
Impurity region 6 is formed. This impurity region 6 is a source
Functions as a drain region.

After forming a silicon oxide film 7 on the entire surface by CVD or the like, etching back is performed on the entire surface. As a result, the polysilicon layer is exposed on the upper surfaces of impurity region 6 and gate electrode 5, and the silicon oxide 1II7 remains on the sidewalls of gate electrode 5.

Next, by sputtering or the like, the entire surface is coated with l! of about 300λ!
A titanium film 8 having Iff is deposited. Then, rapid heating and short-time annealing is performed by irradiating short-wavelength arc lamp light in an argon atmosphere. The conditions for this annealing treatment may be selected as appropriate; for example, it is preferable that the annealing temperature be a relatively low temperature of about 600'C and the treatment time be about 30 seconds. Furthermore, the wavelength of short wavelength arc lamp light is approximately 0.
It is preferable that it is 6 μm or less. Through this annealing treatment, the polysilicon layer 3 in the source/drain region and the polysilicon layer exposed on the upper surface of the gate electrode 5 undergoes a silicide reaction with the titanium film 8, and titanium silicide M9 is formed on the impurity region 6 and the gate electrode 5. It is formed. Since this titanium silicide 1119 is annealed at a relatively low temperature, it becomes a monosilicide state.

FIG. 2 is a diagram showing the relationship between absorption intensity (vertical axis) and wavelength [μm] (horizontal axis) of arc lamp light and halogen lamp light for a silicon layer. As shown in FIG. 2, the absorption intensity of halogen lamp light becomes slightly strong when the wavelength is about 0.9 μm, but it is hardly absorbed by the silicon layer. On the other hand, arc lamp light has a peak at about 0.5 μm, and large absorption occurs. In addition, when the absorption coefficient α (C1l-') (vertical pongee) of this arc lamp light is also shown in Figure 2, the absorption coefficient α of arc lamp light is extremely high in the range of 0.2 to 0.6 μm. I understand that.

That is, since the polysilicon layer 3 and the gate electrode 5 made of the polysilicon layer have a large absorption coefficient α of arc lamp light in the ultraviolet region, sufficient energy is supplied to these polysilicon layers 3 and the like. Therefore, even if the base of the polysilicon layer 3 and the like is a quartz substrate l, the temperature of only the polysilicon layer 3 and the gate electrode 5 can be effectively increased.
Good silicidation can be performed.

Next, unreacted titanium w148 from the above-mentioned silicidation
In order to remove the titanium film 8, only the titanium film 8 is selectively dissolved, and the titanium silicide 119 is removed. The unreacted titanium film 8 is selectively etched using an etching solution that does not disturb the etching process. As a result, as shown in FIG. 1(b), the titanium film 8 remaining on the quartz substrate 1, etc. is removed, and titanium is applied only to the regions where resistance should be reduced, such as the impurity region 6 and the gate electrode 5. A silicide film 9 is formed.

Then, the titanium silicide film 9 is annealed in a nitrogen gas atmosphere. The conditions for this annealing treatment may be selected as appropriate. For example, it is preferable to set the annealing temperature to a relatively high temperature of about 800"C and the treatment time to about 30 seconds. Through this annealing treatment, the titanium silicide film 9 is The resistance value of the source/drain region made of a normal polysilicon layer, which becomes a disilicide after the silicide reaction is completed, is about several hundred Ω/hole, whereas the resistance value of the titanium silicide film 9 is about 30 Ω. Since the titanium silicide film 9 is formed on the impurity region 6 and the gate electrode, the sheet resistance and contact resistance are significantly reduced. Therefore, high-speed operation of the MOS transistor is possible. Become.

MO3) A glabellar insulation 11101 made of a silicon oxide film, a PSG film, or the like is formed on the entire surface including the transistor according to a normal manufacturing process. As shown in FIG. 1(c), this interlayer insulating film 101 has connection holes above impurity region 6 and gate electrode 5. As shown in FIG.

Then, fill in this connection hole and insulate between the eyebrows! II
An aluminum wiring layer 102 is formed to cover 6. This aluminum wiring layer 102 is connected to impurity region 6 and gate electrode 5 via titanium silicide film 9 within the connection hole. At this time, since the titanium silicide film 9 functions as a barrier metal, the aluminum wiring layer 102
The alloying reaction between the polysilicon layer and these polysilicon layers is prevented,
Provides highly reliable contact.

Finally, a hydrogenation annealing process is performed.

In this example, aluminum is used as the material for the wiring layer, but in the connection hole with a high aspect ratio, aluminum is used as the material for the wiring layer.
A technique for embedding a high melting point metal such as tungsten using a selective CVD method is effective. Selection of tungsten In CVD, a tungsten film is usually formed by reacting a mixed gas of sxH,i gas and WFh gas, but in this method, a fluorine compound of titanium is generated in the early stage of the reaction, and the tungsten film in the contact hole is
Since the fluorine compound is precipitated on the tan silicide 1l19, a problem arises in that the contact resistance increases. In order to prevent this problem, it is preferable to embed tungsten by the method described below.

That is, first, selective CVD is performed at a temperature of about 400°C or higher using a hydrogen reduction method to remove titanium silicide 11 in the connection hole.
A tungsten film is placed on the 19 to a certain length.

Here, by setting the temperature to about 400° C. or higher, which is higher than the sublimation temperature of titanium fluoride, precipitation of the titanium fluorine compound as described above is prevented. Furthermore, since the atmosphere is hydrogen reducing, there is no risk that the ashes will deteriorate even at high temperatures of about 400° C. or higher.

Next, when the titanium silicide film 9 is sufficiently covered with the tungsten film, the temperature is lowered to about 20Q° C. and the reducing gas is switched to SiH4 gas. This increases the growth rate of the tungsten film and improves productivity.

FIG. 7 shows a conventional selection C on a tungsten silicide film.
(a) when a tungsten film is deposited by the VD method;
FIG. 7B is a diagram showing the contact resistance in the case (b) in which a tungsten film is deposited by the selective CVD method of this example. In addition, in FIG. 7, the vertical axis shows the current, and the horizontal axis shows the voltage. As shown in FIG. 7, the conventional selective CVD method has poor linearity and cannot obtain ohmic contact. It can be seen that the selective CVD method of this example has excellent linearity and low resistance. Therefore, according to the selective CVD method of this embodiment, a fluorine compound of titanium is not formed at the contact interface, the titanium silicide film 9 and the tungsten film are directly connected, and a good contact is obtained. As a method of forming a tungsten film with excellent ohmic properties on the silicide film 9, a thin silicon film may be selectively formed on the titanium silicide film 9 in advance.

That is, first, selective CVD is performed on the titanium silicide film 9 in the contact hole opened in the interlayer insulating film 101 using SiHgCfx gas as a reaction gas, to form a silicon film with a thickness of about 100 nm. The conditions for this selective CVD are 5i
The HzC1,x gas flow rate is 11005 CC, the reaction temperature is, for example, about 850°C, and the pressure is 760 Torr. At this time, by maintaining the high temperature as described above, the impurity diffused into the titanium silicide film 9 in the silicidation process is diffused into the polysilicon layer 3 again. Therefore, junction leakage current can be reduced at the same time.

Next, a tungsten film is grown by reacting a mixed gas of WF, gas, and Hz gas using the Si reduction method. after that,
Further, SiH4 gas is added to create a SiH4 gas reducing atmosphere to increase the growth rate of tungsten. At this time, for example, WF, gas flow rate is 065~IO3CCM, SiH4
The gas flow rate is 0 to 98 cCM, and the reaction temperature is, for example, 25
About 0'C, pressure is o.

It is preferable to set it to 15 Torr.

Finally, perform IR annealing and titanium silicide 1I
The silicon film previously formed on II9 is silicided.

By filling the contact hole by the selective CVD method as described above, ohmic properties are improved and a highly reliable contact can be obtained.

Second Embodiment In this embodiment, a thin film transistor is formed on a quartz substrate via a silicon nitride film, which is a reaction prevention film, and its Til1l
I! ) This is an example in which a low-resistance titanium silicide film is formed on the source/drain region and gate electrode of a transistor.

As shown in FIG. 3(a), a silicon nitride film 12 is formed on a quartz substrate 11. As shown in FIG. This silicon nitride 11111
The film thickness of No. 2 is 1000 Å or less, preferably about 500 Å or less.
It is considered to be less than Å. This silicon nitride 1112 functions as a reaction prevention film that prevents silicidation from reaching the quartz substrate 11 underlying the thin film transistor during annealing treatment for silicidation, which will be described later. This silicon nitride film 12
A thin polysilicon layer 13 is laminated thereon. A gate electrode 15 of a predetermined shape made of a polysilicon layer is formed on this polysilicon layer 13 with a gate oxide film 14 interposed therebetween. Using this gate electrode 15 as a mask, ion implantation is performed to form an impurity region 16 in the polysilicon layer 13 with an impurity such as phosphorus.

This impurity region 16 functions as a source/drain region.

After silicon oxide w117 is formed on the entire surface by CVD or the like, an etch bank is performed on the entire surface, and as a result, the silicon oxide film 17 is formed only on the side walls of the gate electrode 15.

Subsequently, a titanium film 18 is formed on the entire surface by sputtering or the like. Then, as in the first embodiment, rapid heating short-time annealing is performed using short wavelength arc lamp light in an argon atmosphere. Through this annealing process-1, a titanium silicide film 19 is formed on the impurity region 16 and the gate electrode 15. At this time, since the silicon nitride film 12 is formed on the quartz substrate 11, even if the polysilicon layer 13 is a thin film, the silicidation is based on quartz! There is no risk that it will reach 11. Therefore, oxygen is not mixed into the titanium silicide 11119 due to thermal diffusion of oxygen contained in the quartz substrate 11, and a good titanium silicide film 19 having a resistance value of about 15 μΩ or less is formed.

Next, titanium! Etching is performed using an etching solution that selectively dissolves only titanium silicide 118 and does not dissolve titanium silicide 11119. As a result, as shown in FIG. 3(b)
As shown in FIG. 2, unreacted titanium 111118 remaining on the quartz base @1111 is removed, and a titanium silicide film 19 is formed in regions where resistance should be reduced, such as on the impurity region 16 and the gate electrode 15.

This lowers the resistance on impurity region 16 and gate electrode 15, thereby increasing the speed of operation of the thin film transistor.

Third Embodiment In this embodiment, It! is provided on a quartz substrate. I! ) In this example, a titanium film and an amorphous silicon film as an antireflection film are sequentially deposited on the source/drain regions of a transistor, and then annealing is performed using excimer laser light to form a titanium silicide film.

First, as shown in FIG. 4(a), a thin polysilicon layer 23 is laminated on a quartz substrate 21. As shown in FIG. A gate electrode 25 having a predetermined shape is formed on this polysilicon layer 23 via a gate oxide II24.

Since this gate electrode 25 is made of a tungsten silicide layer and has a low resistance value, rIIll! This is advantageous in increasing the speed of transistors. Using such gate electrode 25 as a mask, impurity such as phosphorus is ion-implanted into polysilicon layer 23 to form impurity regions 26 functioning as source/drain regions.

Subsequently, as shown in FIG. 4(b), a silicon oxide film 27 is formed on the entire surface by a CVD method or the like, and then the entire surface is etched back to form the silicon oxide film 27 only on the side walls of the gate electrode 25. do.

Next, as shown in FIG. 4(c), a titanium film 28 having a thickness of about 300 Å is deposited over the entire surface by the Svanta method or the like. An amorphous silicon film 29 functioning as an antireflection film is formed on this titanium film 28. The thickness of this amorphous silicon film 29 is, for example, about 300, and other materials such as polysilicon film can also be used. Then, the entire surface is irradiated with excimer laser light to perform rapid heating and short-time annealing to turn titanium 1112B into silicide. The conditions for this annealing treatment may be selected as appropriate.

At this time, an amorphous silicon film 29 is formed on the titanium film 28.
is formed, even if excimer laser light is used, reflection of the laser light on the titanium film 28 is prevented, and energy is absorbed through the amorphous silicon film 29. As a result, as shown in FIG. 4(d), the titanium film 28 and the amorphous silicon l! A silicide reaction occurs between I29 and the impurity region 26, and a titanium silicide film 30 is formed over the entire surface.

Subsequently, as shown in FIG. 4(e), a silicon oxide film 2 is formed.
The titanium silicide M30 is etched using a mask having a pattern covering the gate electrode 25 including the etching pattern. As a result, the titanium silicide film 30 is replaced by the silicon oxide film 27.
is patterned in a self-consistent manner.

Fourth Example In this example, a titanium film and a Ti0NIIl as an antireflection film were sequentially deposited on the source/drain regions of a fill transistor provided on a quartz substrate, and annealing treatment was performed using excimer laser light. This is an example of forming a titanium silicide film.

First, a silicon oxide film 2 is formed on the side wall of the gate electrode 25 according to the steps shown in FIGS. 4(a) and 4(b) described above.
After forming the MOS transistor with 7, as shown in FIG.
As shown in a), titanium 112B and a Ti0N film 31 functioning as an antireflection film are sequentially laminated. Note that the same reference numerals are given to the same parts as in FIGS. 4(a) to 4(b) above.

Next, excimer laser treatment is performed in the same way as the annealing treatment described above.
Silicidation is performed by irradiating the entire surface with light.

Since the Ti0N film 31 is formed on the titanium film 28, titanium 1M! The laser beam is prevented from being reflected on the TiON film 31, and the energy is absorbed through the TiON film 31. As a result, a silicide reaction occurs between the titanium 1128 and the polysilicon layer 23 in which the impurities M6 are formed.
Impurity 8H! ! A titanium silicide film 30 is formed on the surface of 26.

Selective etching is performed to remove unreacted titanium 112B and TfONWI 131.

As a result, as shown in FIG. 5(b), the impurity region 26
A titanium silicide film 28 is formed on the surface of the wafer, making it possible to selectively silicide only the wI region whose resistance is desired to be reduced.

Fifth Embodiment This embodiment is an example in which a wiring layer made of a titanium silicide film is formed over a MOS transistor provided on a substrate via TiN1ll.

First, as shown in FIG. 6(a), a P-type silicon substrate 41 is selectively oxidized by LOCO3 method etc. to form an element component M.
A td area 42 is formed. A p type impurity is introduced into the lower part of the element isolation f11 region 42 to form a p type impurity region 43 which functions as a channel stopper. Then, a tungsten silicide layer 45 and a tungsten silicide layer 52, which are used as gate bridges, are formed on the silicon substrate 41 via a gate oxide film 44 by patterning. Tungsten silicide layer 52
has a pattern in which one end is on the silicon substrate 41 and the other end extends on the element isolation region 42 via the gate oxide film 44.

Then, using the gate electrode 45 as a mask, ion implantation is performed to form an n-type impurity region 46a on the surface of the silicon substrate 41.

Silicon oxide on the entire surface! After forming 147, the entire surface is etched back to expose impurity region 46a. As a result, silicon oxide film 47 remains on the sidewalls of tungsten silicide layer 45. Using the tungsten silicide layer 45 as a mask, n'' type impurity ions are implanted into the surface of the silicon substrate 41, including this silicon oxide film 47, to form n'' type impurity regions 46b that function as source/drain regions.Silicon Since an n-type impurity is introduced into the surface m of the substrate 41 in advance, an n-type impurity region 46a is formed in the vicinity of the tungsten silicide layer 45 in self-alignment with the silicon oxide film 47. That is, , an LDD type MO3I-transistor with excellent reliability is formed.A sufficient film of silicon oxide 1llI51 is formed over the entire surface of such a MOS) transistor.

This silicon oxide film 51 functions as an interlayer insulating film.

A resist layer having an opening above one of the source and drain regions of the MOs transistor is formed on the silicon oxide film 51, and etching is performed using this resist layer as a mask to form an opening 54 in the silicon oxide film 51.

As a result of this etching, the end portion of the tungsten silicide layer 52 is exposed within the opening 54. Then, a thin TiN film 53 is formed on the entire surface including this opening 54 along the shape of the opening 54. This TiN1153 functions as a reaction prevention film in the annealing treatment for silicidation, which will be described later. Furthermore, the exposed end portions of the tungsten silicide layer 52 are covered with this TiN film 53.

Subsequently, as shown in FIG. 6(b), a layer 3 on the TiN film 5 is
A titanium film 48 is formed along the shape of the upper opening 54, and an amorphous silicon film 49 is laminated on this titanium film 48.

Next, in the same manner as in the third embodiment, the entire surface was irradiated with excimer laser light to perform annealing, and as shown in FIG. 6(C), titanium 1! I48 and amorphous silicon film 49
is silicided to form a titanium silicide film 50. At this time, a silicon oxide film 51 is formed under the amorphous silicon film 49 that is irradiated with excimer laser light, but a TiN film 53 is interposed therebetween.
Since the iNllll53 functions as a barrier, there is no possibility that oxygen contained in the silicon oxide H51 will mix into the titanium silicide film 50 due to ripening. Therefore, a good titanium silicide [50] can be obtained. Also, amorphous silicon is placed on the titanium film 48! Since I49 is formed, even if the titanium film 48 is irradiated with excimer laser light, the titanium film 48 is prevented from reflecting the excimer laser light. Therefore, the titanium film 48 is formed through the amorphous silicon 1149.
energy is absorbed and a silicide reaction occurs.

The titanium silicide film 50 has an opening 54 in which the TiN film 5
3, and functions as a low resistance wiring layer.

As described above, the amorphous silicon film 49 is formed on the titanium film 48, and the amorphous silicon film 49 is irradiated with excimer laser light to be silicided, thereby forming a low resistance wiring layer. Furthermore, since annealing is performed using excimer laser light, there is no risk of thermal damage to the underlying layer.

[Effects of the Invention] As described above, in the present invention, a good silicide film is formed in a region where resistance should be reduced by siliciding a metal film using short wavelength arc lamp light. Also,
In the present invention, by providing an antireflection film on the metal film,
It is believed that silicide formation using laser light is possible. This reduces the contact resistance and sheet resistance in the source/drain regions, gate electrodes, etc., thereby realizing high-speed operation of the MIS type semiconductor device or the above-mentioned thin film transistor, and is convenient for higher integration and larger size. .

Furthermore, since the present invention enables silicidation using laser light, it is possible to perform silicidation without causing thermal damage to the underlying layer, and provides silicidation suitable for three-dimensional structuring of semiconductor devices. be done.

[Brief explanation of drawings]

1(a) to 1(c) are schematic cross-sectional views for explaining the manufacturing method of the first embodiment of the semiconductor device I of the present invention according to the manufacturing process order, and FIG. Relationship between absorption intensity and wavelength of arc lamp light and halogen lamp light, and absorption coefficient α of arc lamp light
3(a) to 3(b) are schematic cross-sectional views for explaining the manufacturing method of the second embodiment of the semiconductor device, and FIG. 4(a) to FIG. FIG. 5(e) is a schematic sectional view for explaining the manufacturing method of the third embodiment of the semiconductor device, and FIGS. 5(a) to 5(b)
6(a) to 6(a) are schematic cross-sectional views for explaining the manufacturing method of the fourth embodiment of the semiconductor device, respectively.
c) is a schematic sectional view for explaining the manufacturing method of the fifth embodiment of the semiconductor device I, and FIG.
FIG. 4 is a characteristic diagram showing the contact resistance in the case where the tungsten film is deposited by the VD method and the case where the tungsten film is deposited by the selective CVD method of the first embodiment. 1...Quartz substrate 3...Polysilicon layer Gate oxide film Gate electrode impurity region Silicon oxide film Titanium film Titanium silicide film

Claims (4)

[Claims] (1) Forming an MIS type semiconductor device on a substrate, forming a metal film on at least the source/drain region of the MIS type semiconductor device, and siliciding the metal film by irradiating short wavelength arc lamp light. A method for manufacturing a semiconductor device, characterized by: (2) The method of manufacturing a semiconductor device according to claim 1, wherein the MIS type semiconductor device is a thin film transistor. (3) Forming an MIS type semiconductor device on a substrate, sequentially forming a metal film and an antireflection film on at least the source/drain regions of the MIS type semiconductor device, and siliciding the metal film by irradiating laser light. A method of manufacturing a semiconductor device, characterized by: (4) The method of manufacturing a semiconductor device according to claim 3, wherein the MIS type semiconductor device is a thin film transistor.