CN100397217C - Series connection structure of thin film transistor and producing method thereof - Google Patents
Series connection structure of thin film transistor and producing method thereof Download PDFInfo
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- CN100397217C CN100397217C CNB2004100571790A CN200410057179A CN100397217C CN 100397217 C CN100397217 C CN 100397217C CN B2004100571790 A CNB2004100571790 A CN B2004100571790A CN 200410057179 A CN200410057179 A CN 200410057179A CN 100397217 C CN100397217 C CN 100397217C
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Abstract
The present invention relates to a series connection structure of thin film transistors. An N-type film transistor region shares one effective layer with a P-type film transistor region, and a contact hole is manufactured on the N/P connection surface between the N-type film transistors and the P-type film transistors; thereby, electric conductive loading electrons in an N-type doped region on one end is electrically connected to a P-type doped region on the other end via the bridge joint of a conductive layer in the contact hole without going through an empty region formed by the N/P connection surface. In addition, mask areas of a grid insulation layer, which are exposed on both sides of a grid layer, are used as the masks of the N-type film transistor region or the P-type film transistor region in the manufacture process of ion implantation, and thereby, a lightly doped drain region, a source region and a drain region can be manufactured simultaneously.
Description
Technical field
The present invention is relevant for a kind of thin film transistor (TFT) (thin film transistor, TFT) technology, especially about cascaded structure and lightly doped drain (lightly doped drain, LDD) Qu Yu the technology of a kind of N type thin film transistor (TFT) and P type thin film transistor (TFT).
Background technology
Active matrix liquid crystal display (active matrix liquid crystal display, hereinafter to be referred as AMLCD) pixel region and drive circuit area be utilization one thin film transistor (TFT) (thin filmtransistor, TFT), generally can be distinguished into two kinds of patterns of non-crystalline silicon tft and multi-crystal TFT as switch module.Because the carrier transport factor integration higher, driving circuit of multi-crystal TFT is preferable, leakage current is less, so multi-crystal TFT more often is applied in the circuit of high operating speed.But leakage current (leakage current) phenomenon easily takes place down in multi-crystal TFT in off position, and regular meeting causes the loss of charge or the problem of power consumption.In order to address this problem, (lightlydoped drain, LDD) structure are used for reducing the electric field of drain junction place (drain junction), can effectively improve the phenomenon of leakage current to adopt a kind of lightly doped drain at present.But along with the integration of circuit design increases, TFT cascaded structure how to improve peripheral circuit area has become the important topic that improves AMLCD resolution to dwindle the circuit area.In addition, along with the dimension reduction of TFT assembly, utilize the position in gold-tinted program defining LDD zone and the rigor test that size can face alignment error (photo misalignment) and critical dimension skew.
See also Figure 1A～Fig. 1 H, it shows the method for making of the cascaded structure of existing N type thin film transistor (TFT) and P type thin film transistor (TFT).
Shown in Figure 1A, a substrate 10 includes a N type TFT regions I and a P type TFT regions II.Be manufactured with one first polysilicon layer 12I, a first grid insulation course 14I and a first grid layer 16I in the N type TFT regions I, be manufactured with one second polysilicon layer 12II, a second grid insulation course 14II and a second grid layer 16II in the P type TFT regions II.Shown in Figure 1B, form one first photoresist layer 18 to cover P type TFT regions II, utilize again first grid layer 16I as mask N type TFT regions I is carried out a N type light dope processing procedure 20, then can in the first polysilicon layer 12I of first grid layer 16I both sides, form a N
-Type doped region 12I
1Follow-up with 18 removals of first photoresist layer.Then, shown in Fig. 1 C, form one second photoresist layer 22 to cover N type TFT regions I, utilize again second grid layer 16II as mask P type TFT regions II is carried out a P type light dope processing procedure 24, then can in the second polysilicon layer 12II of second grid layer 16II both sides, form a P
-Type doped region 12II
1Follow-up with 22 removals of second photoresist layer.
Shown in Fig. 1 D, carry out the deposition of insulation course, little shadow and dry ecthing procedure, can be respectively at forming sub-26I of one first insulative sidewall and the sub-26II of one second insulative sidewall on the two side of first grid layer 16I, second grid layer 16II, in order to cover the N of below
-Type doped region 12I
a, P
-Type doped region 12II
aA part of zone.Then, shown in Fig. 1 E, form one the 3rd photoresist layer 28 to cover P type TFT regions II, utilize first grid layer 16I and the sub-26I of first insulative sidewall as mask again, N type TFT regions I is carried out a N type heavy doping processing procedure 30, then can be in the N of the sub-26I of first insulative sidewall both sides
-Type doped region 12I
aThe interior N that forms
+Type doped region 12I
b, 12I
cFollow-up with 28 removals of the 3rd photoresist layer.Just roughly finish the making of N type thin film transistor (TFT), wherein N in this
+Type doped region 12I
bBe as one source pole diffusion zone, N
+Type doped region 12I
cBe as a drain diffusion region, N
-Type doped region 12I
aBe as a LDD zone.
Then, shown in Fig. 1 F, form one the 4th photoresist layer 32 to cover N type TFT regions I, utilize second grid layer 16II and the sub-26II of second insulative sidewall as mask again, P type TFT regions II is carried out a P type heavy doping processing procedure 34, then can be in the P of the sub-26II of second insulative sidewall both sides
-Type doped region 12II
aThe interior P that forms
+Type doped region 12II
b, 12II
cFollow-up with 32 removals of the 4th photoresist layer.Just roughly finish the making of P type thin film transistor (TFT), wherein P in this
+Type doped region 12II
bBe as one source pole diffusion zone, P
+Type doped region 12II
cBe as a drain diffusion region, P
-Type doped region 12II
aBe as a LDD zone.
Shown in Fig. 1 G, form an interlayer dielectric layer 36 on N type thin film transistor (TFT) and P type thin film transistor (TFT), utilize again little shadow and etching mode in interlayer dielectric layer 36, make one first contact hole 38A, one second the contact hole 38B, one the 3rd the contact hole 38C contact hole 38D with one the 4th.The first contact hole 38A exposes N
+Type doped region 12I
b, the second contact hole 38B exposes N
+Type doped region 12I
c, the 3rd contact hole 38C exposes P
+Type doped region 12II
b, the 4th contact hole 38D exposes P
+Type doped region 12II
cAt last, shown in Fig. 1 H, carry out the deposition of a conductive layer, little shadow and dry ecthing procedure, to form a plurality of contact plunger 40A, 40B, 40C, 40D, one first source electrode conductive layer 40S
1, one second source electrode conductive layer 40S
2An and drain electrode conductive layer 40D.Wherein, conductive layer is to fill up the first contact hole 38A to become the first contact plunger 40A, then can make the first source electrode conductive layer 40S
1Be electrically connected to N
+Type doped region 12I
bConductive layer is to fill up the 3rd contact hole 38C to become the 3rd contact plunger 40C, then can make the second source electrode conductive layer 40S
2Be electrically connected to P
+Type doped region 12II
bConductive layer is to fill up the second contact hole 38B, the 4th contact hole 38D to become the second contact plunger 40B and the 4th contact plunger 40D, then can make drain electrode conductive layer 40D be electrically connected to N simultaneously
+Type doped region 12I
cWith P
+Type doped region 12II
c
The cascaded structure and the method for making of above-mentioned N type thin film transistor (TFT) and P type thin film transistor (TFT) have following shortcoming:
The first, for fear of N
+Type doped region 12I
cWith P
+Type doped region 12II
cThe formed exhaustion region in composition surface (below be referred to as N/P connect face) influence the carrier transmission, therefore need the first polysilicon layer 12I and the second polysilicon layer 12II are made into the island structure of two separations, the follow-up second contact plunger 40B and the 4th contact plunger 40D of more must making is to be electrically connected to the conductive layer 40D that drains.Therefore the needed area of integrated circuit is bigger, and in the circuit design of using high integration, for example: (digital analog converter, DAC), this kind cascaded structure can limit the pixel resolution of AMLCD to digital analog converter.
The second, said method must accurately be controlled the pattern of the sub-26I of insulative sidewall, 26II just can guarantee the position and the size in LDD zone.And, being subject to the alignment error (photo misalignment) of exposure technique, twice ion disposing process can make the offset problem in LDD zone can be more serious.Very and, processing procedure complexity, the production speed of said method are low, the length in also wayward LDD zone.
Summary of the invention
In view of this, purpose of the present invention just is to provide a kind of N type thin film transistor (TFT) and the cascaded structure of P type thin film transistor (TFT) and the technology of ldd structure thereof, can reach and dwindle circuit area and the advantage that increases resolution, and can utilize the mask of the shaded areas that is exposed to the grid layer both sides of gate insulator as ion disposing process, to reach the making of lightly doped drain zone and source/drain region simultaneously.
For reaching above-mentioned purpose, the invention provides a kind of cascaded structure of thin film transistor (TFT).One substrate includes one first conductivity type thin-film transistor zone and one second conductivity type thin-film transistor zone.One effective layer includes: one first channel region is to be formed in this first conductivity type thin-film transistor zone; The lightly doped region of one first conductivity type is to be formed in this first conductivity type thin-film transistor zone, and is formed at the both sides of this first channel region; The heavily doped region of one first conductivity type is to be formed in this first conductivity type thin-film transistor zone, and is formed at the both sides of the lightly doped region of this first conductivity type; One second channel region is to be formed in this second conductivity type thin-film transistor zone; The lightly doped region of one second conductivity type is to be formed in this second conductivity type thin-film transistor zone, and is formed at the both sides of this second channel region; And the heavily doped region of one second conductivity type, be to be formed in this second conductivity type thin-film transistor zone, and be formed at the both sides of the lightly doped region of this second conductivity type, wherein the face that the connects place of the heavily doped region of the heavily doped region of two adjacent these first conductivity types and this second conductivity type forms an exhaustion region.One first grid insulation course is on the effectively layer that is formed in this first conductivity type thin-film transistor zone, and includes: a middle section is to cover this effectively first channel region of layer; And a shaded areas, be to cover this effectively lightly doped region of this first conductivity type of layer.One second grid insulation course is on the effectively layer that is formed in this second conductivity type thin-film transistor zone, and includes: a middle section is to cover this effectively second channel region of layer; And a shaded areas, be to cover this effectively lightly doped region of this second conductivity type of layer.One first grid layer is to be formed on this first grid insulation course, and covers the middle section of this first grid insulation course.One second grid layer is to be formed on this second grid insulation course, and covers the middle section of this second grid insulation course.One interlayer dielectric layer is to be formed on this first, second grid layer, this first, second gate insulator and this effective layer, and including a contact hole, is that this of heavily doped region that exposes the heavily doped region of this first conductivity type and this second conductivity type meets the face place.One conductive layer is to be formed in this contact hole, so that the heavily doped region of this first conductivity type is electrically connected to the heavily doped region of this second conductivity type.
For reaching above-mentioned purpose, the invention provides a kind of method for making of cascaded structure of thin film transistor (TFT).One substrate is provided, and it includes one first conductivity type thin-film transistor zone and one second conductivity type thin-film transistor zone, forms an effective layer, an insulation course and one first conductive layer more in regular turn in this substrate.Carry out an etch process, this first conductive layer is defined as a first grid layer and a second grid layer, and this insulation course is defined as a first grid insulation course and a second grid insulation course.This first grid insulation course is to be formed in this first conductivity type thin-film transistor zone, and includes the both sides that a middle section and a shaded areas are formed at this middle section.This first grid layer is to be formed in this first conductivity type thin-film transistor zone, and covers the middle section of this first grid insulation course.This second grid insulation course is to be formed in this second conductivity type thin-film transistor zone, and includes the both sides that a middle section and a shaded areas are formed at this middle section.This second grid layer is to be formed in this second conductivity type thin-film transistor zone, and covers the middle section of this second grid insulation course.Carry out one first ion disposing process, form one first channel region, the lightly doped region of one first conductivity type and the heavily doped region of one first conductivity type in the effectively layer in this first conductivity type thin-film transistor zone.This first channel region is the below that is positioned at this first grid layer, and the lightly doped region of this first conductivity type is the both sides that are positioned at this first channel region, and the heavily doped region of this first conductivity type is the both sides that are positioned at the lightly doped region of this first conductivity type.Carry out one second ion disposing process, form one second channel region, the lightly doped region of one second conductivity type and the heavily doped region of one second conductivity type in the effectively layer in this second conductivity type thin-film transistor zone.This second channel region is the below that is positioned at this second grid layer, the lightly doped region of this second conductivity type is the both sides that are positioned at this second channel region, the heavily doped region of this second conductivity type is the both sides that are positioned at the lightly doped region of this second conductivity type, and the face that the connects place of the heavily doped region of two adjacent these first conductivity types and the heavily doped region of this second conductivity type forms an exhaustion region.Form an interlayer dielectric layer with the TFT regions that covers this first conductivity type and the TFT regions of this second conductivity type, and in this interlayer dielectric layer, form a contact hole, be the face that the connects place that exposes the heavily doped region of the heavily doped region of this first conductivity type and this second conductivity type.Form one second conductive layer in this second contact hole, so that the heavily doped region of this first conductivity type is electrically connected to the heavily doped region of this second conductivity type.
Description of drawings
Figure 1A～Fig. 1 H shows the method for making of the cascaded structure of existing N type thin film transistor (TFT) and P type thin film transistor (TFT).
The diagrammatic cross-section of the method for making of the cascaded structure of the multi-crystal TFT of Fig. 2 A～Fig. 2 F demonstration first embodiment of the invention.
Fig. 3 shows the schematic layout pattern of cascaded structure of the multi-crystal TFT of first embodiment of the invention.
Fig. 4 shows the diagrammatic cross-section of cascaded structure of the multi-crystal TFT of second embodiment of the invention.
The diagrammatic cross-section of the cascaded structure of the multi-crystal TFT of Fig. 5 A～Fig. 5 B demonstration third embodiment of the invention.
Symbol description:
Substrate～10;
N type TFT regions～I;
P type TFT regions～II;
First polysilicon layer～12I;
N
-Type doped region～12I
1N
+Type doped region～12I
b, 12I
c
Second polysilicon layer～12II;
P
-Type doped region～12II
1P
+Type doped region～12II
b, 12II
c
First grid insulation course～14I; Second grid insulation course～14II;
First grid layer～16I; Second grid layer～16II;
Photoresist layer～18,22,28,32;
N type light dope processing procedure～20; N type heavy doping processing procedure～30;
P type light dope processing procedure～24; P type heavy doping processing procedure～34;
First insulative sidewall～26I; Second insulative sidewall～26II;
Interlayer dielectric layer～36;
Contact hole～38A, 38B, 38C, 38D;
Contact plunger～40A, 40B, 40C, 40D;
First source electrode conductive layer～40S
1
Second source electrode conductive layer～40S
2
Drain electrode conductive layer～40D.
Substrate～50;
N type TFT regions～I;
P type TFT regions～II;
Cushion～52;
Effective layer～54;
Not doped region～54a, 54d;
N
-Doped region～54b
1, 54b
2
N
+Doped region～54c
1, 54c
2
P
-Doped region～54e
1, 54e
2
P
+Doped region～54f
1, 54f
2
Insulation course～56;
First grid insulation course～561;
Middle section～561a;
Shaded areas～561b
1, 561b
2
Elongated area～561c
1, 561c
2
Second grid insulation course～562;
Middle section～562a;
Shaded areas～562b
1, 562b
2
Elongated area～562c
1, 562c
2
First conductive layer～58;
First grid layer～581; Second grid layer～582;
Photoresist layer～60,64;
N type dopping process～62;
P type dopping process～66;
Interlayer dielectric layer～68;
Contact hole～70A, 70B, 70C;
Contact plunger～72A, 72B, 72C;
First source electrode conductive layer～72S
1
Second source electrode conductive layer～72S
2
Drain electrode conductive layer～72D.
Embodiment
The invention provides the cascaded structure and lightly doped drain (the lightly doped drain thereof of a kind of N type thin film transistor (TFT) and P type thin film transistor (TFT), LDD) technology of structure, it can be applicable in the circuit design of the drives zone of high resolution display or pixel region, for example: the cascaded structure that is applied to the multi-crystal TFT of active matrix liquid crystal display (AM-LCD) or active-matrix display of organic electroluminescence (AM-OLED).One of its technical characterictic is, needn't make two effective layers (polysilicon layer) that independently separate for N type thin film transistor (TFT) and P type thin film transistor (TFT), one of making contacts the hole on the face but directly connect with the N/P of P type thin film transistor (TFT) in N type thin film transistor (TFT), can make an end N type doped region conducting currier can via contact in the hole conductive layer and be electrically connected to the P type doped region of the other end, and can not connect the formed exhaustion region of face, so can reach and dwindle circuit area and the advantage that increases resolution by this N/P.Two of its technical characterictic is, utilize the mask of the shaded areas that is exposed to the grid layer both sides of gate insulator as ion disposing process, then can reach the making of LDD zone and source/drain region simultaneously, so that multi-crystal TFT has extremely low leakage current, and can remove the problem that gold-tinted is aimed at from, and reach the length symmetry in LDD zone.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
First embodiment
See also Fig. 2 A～Fig. 2 F, the diagrammatic cross-section of the method for making of the cascaded structure of the multi-crystal TFT of its demonstration first embodiment of the invention.
At first, shown in Fig. 2 A, provide a substrate 50, its definition has a N type TFT regions I and a P type TFT regions II.In substrate 50, make effective layer 54 of a cushion 52 and an island structure in regular turn.The preferably of substrate 50 is a transparent insulation substrate, for example: substrate of glass.The preferably of cushion 52 is a dielectric materials layer, and for example: silicon oxide layer, layer 54 is formed in the substrate 50 its purpose in order to help effectively.Effectively the preferably of layer 54 is the semiconductor silicon layer, and for example: polysilicon layer, it is to cover N type TFT regions I and P type TFT regions II simultaneously.The present invention does not limit thickness of effective layer 54 and preparation method thereof, for instance, can adopt low temperature polycrystalline silicon (lowtemperature polycrystalline silicon, LTPS) processing procedure, prior to forming a noncrystalline silicon layer on the glass substrate, (excimer laserannealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize the annealing of thermal treatment or excimer laser then.Then, on effective layer 54, deposit an insulation course 56 and one first conductive layer 58 in regular turn.The preferably of insulation course 56 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.The preferably of first conductive layer 58 is a metal level or a polysilicon layer.
Shown in Fig. 2 B, the photoresistance that utilizes patterning as mask to carry out dry ecthing procedure, tentatively with the pattern of conductive layer 58 definition becoming a first grid layer 581 and a second grid layer 582, it is to lay respectively at N type TFT regions I and P type TFT regions II.Continue, carry out electric paste etching (plasma etching) or reactive ion etching, can use a mixed gas with oxygen-containing gas and chlorine-containing gas, flow with chlorine-containing gas in the etching process of conductive layer 58 is adjusted to greatly (or even only using chlorine-containing gas as etching reaction gas) gradually, aerating oxygen or strengthen oxygen flow simultaneously again when waiting to be etched to insulation course 56, but etching simultaneously expose once again first, second grid layer 581,582 profile, then can be with first, second grid layer 581,582 make and to become one up-narrow and down-wide trapezoidally, and can make first, second grid layer 581, the insulation course 56 of 582 belows becomes first of two separations, second grid insulation course 561,562.Follow-up photoresistance with patterning removes.In addition, this step can utilize a decrescendo phase transfer light shield (attenuated phase shifting mask) and collocation to carry out micro-photographing process one time, then the grid layer 581,582 that can define N type TFT regions I and P type TFT regions II simultaneously by convex character shape optical pattern resistances layer and etch process with the pattern of gate pole insulation course 561,562.
For the first grid insulation course 561 in the N type TFT regions I, it includes a middle section 561a, one first shaded areas 561b
1And one second shaded areas 561b
2 Middle section 561a is covered by the bottom of first grid layer 581, first, second shaded areas 561b
1, 561b
2Be the two bottom sides that is exposed to first grid layer 581 respectively, and first grid insulation course 561 is to expose the effectively predetermined origin/drain region of a N type thin film transistor (TFT) of layer 54.The preferably is the first shaded areas 561b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 561b
2Lateral length W
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W
1, W
2Length and symmetry thereof.For example, W
1=W
2W
1≠ W
2W
1, W
2One of them equals 0.
For the second grid insulation course 562 in the P type TFT regions I, it includes a middle section 562a, one first shaded areas 562b
1And one second shaded areas 562b
2, middle section 562a is covered by the bottom of second grid layer 582, first, second shaded areas 562b
1, 562b
2Be the two bottom sides that is exposed to second grid layer 582 respectively, and second grid insulation course 562 is to expose the effectively predetermined origin/drain region of a P type thin film transistor (TFT) of layer 54.The preferably is the first shaded areas 562b
1Lateral length D
1Be 0.1 μ m～2.0 μ m, the second shaded areas 562b
2Lateral length D
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust D
1, D
2Length and symmetry thereof.For example, D
1=D
2D
1≠ D
2D
1, D
2One of them equals 0.
Then, shown in Fig. 2 C, form one first photoresist layer 60, again N type TFT regions I is carried out a N type ion disposing process 62, utilize the shaded areas 561b of first grid layer 581, first grid insulation course 561 to cover P type TFT regions II
1, 561b
2As mask, then can in the effective layer 54 of N type TFT regions I, form not doped region 54a, two N
-Doped region 54b
1, 54b
2And two N
+Doped region 54c
1, 54c
2Wherein, doped region 54a is not the corresponding below that is formed at middle section 561a, is to be used as a channel region; First, second N
-Doped region 54b
1, 54b
2Be corresponding first, second shaded areas 561b that is formed at
1, 561b
2The below, be to be used as a LDD zone; First, second N
+Doped region 54c
1, 54c
2Being the two bottom sides that is exposed to first grid insulation course 561, is to be used as one source/drain diffusion region.Because the shaded areas 561b of first grid insulation course 561
1, 561b
2Be the mask that is used as the LDD zone, so a N
-Doped region 54b
1Width be to correspond to the first shaded areas 561b
1Width W
1, and the 2nd N
-Doped region 54b
2Width be to correspond to the second shaded areas 561b
2Width W
2The preferably is first, second N
-Doped region 54b
1, 54b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, first, second N
+Doped region 54c
1, 54c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2So just roughly finish the making of N type thin film transistor (TFT), follow-up with 60 removals of first photoresist layer.
Then, shown in Fig. 2 D, form one second photoresist layer 64, again P type TFT regions II is carried out a P type ion disposing process 66, utilize the shaded areas 562b of second grid layer 582, second grid insulation course 562 to cover N type TFT regions I
1, 562b
2As mask, then can in the effective layer 54 of P type TFT regions II, form not doped region 54d, two P
-Doped region 54e
1, 54e
2And two P
+Doped region 54f
1, 54f
2Wherein, doped region 54d is not the corresponding below that is formed at middle section 562a, is to be used as a channel region; First, second P
-Doped region 54e
1, 54e
2Be corresponding first, second shaded areas 562b that is formed at
1, 562b
2The below, be to be used as a LDD zone; First, second P
+Doped region 54f
1, 54f
2Being the two bottom sides that is exposed to second grid insulation course 562, is to be used as one source/drain diffusion region.Because the shaded areas 562b of first grid insulation course 562
1, 562b
2Be the mask that is used as the LDD zone, so a P
-Doped region 54e
1Width be to correspond to the first shaded areas 562b
1Width D
1, and the 2nd P
-Doped region 54e
2Width be to correspond to the second shaded areas 562b
2Width D
2The preferably is first, second P
-Doped region 54e
1, 54e
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, first, second P
+Doped region 54f
1, 54f
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2So just roughly finish the making of P type thin film transistor (TFT), follow-up with 64 removals of second photoresist layer.
Shown in Fig. 2 E, form an interlayer dielectric layer 68 on N type thin film transistor (TFT) and P type thin film transistor (TFT), utilize little shadow and etching mode in interlayer dielectric layer 68, to make one first again and contact hole 70A, one second contact hole 70B and one the 3rd contact hole 70C.The first contact hole 70A exposes N
+Type doped region 54c
1, the second contact hole 70B exposes P
+Type doped region 54f
2, the 3rd contact hole 70C exposes N
+Type doped region 54c
2With P
+Type doped region 54f
1N/P meet the face place.It should be noted that the present invention does not limit quantity and the profile of the 3rd contact hole 70C, connect the formed vague and general zone of face but the size of the 3rd contact hole 70C must surmount N/P, the preferably is: the path length of the 3rd contact hole 70C is about 3～5 μ m.
At last, shown in Fig. 2 F, carry out the deposition of one second conductive layer, little shadow and dry ecthing procedure, to form a plurality of contact plunger 72A, 72B, 72C, one first source electrode conductive layer 72S
1, one second source electrode conductive layer 72S
2An and drain electrode conductive layer 72D.Wherein, second conductive layer is to fill up the first contact hole 70A to become the first contact plunger 72A, then can make the first source electrode conductive layer 72S
1Be electrically connected to N
+Type doped region 54c
1Second conductive layer is to fill up the second contact hole 70B to become the second contact plunger 72B, then can make the second source electrode conductive layer 72S
2Be electrically connected to P
+Type doped region 54f
2Second conductive layer is to fill up the 3rd contact hole 70C to become the 3rd contact plunger 72C, then can make N
+Type doped region 54c
2And P
+Type doped region 54f
1The conducting currier at two ends can be reached the effect of conducting with drain electrode conductive layer 72D via the 3rd contact plunger 72C.
See also Fig. 3, the schematic layout pattern of the cascaded structure of the multi-crystal TFT of its demonstration first embodiment of the invention.The present invention needn't make effective layer of two separations, and can be directly in N
+Type doped region 54c
2With P
+Type doped region 54f
1N/P connect on the face and to make at least one the 3rd contact hole 70C, then, can make an end N by the bridge joint of the 3rd contact plunger 72C with drain electrode conductive layer 72D
+Type doped region 54c
2Conducting currier be electrically connected to the P of the other end
+Type doped region 54f
1Very and, the size of the 3rd contact hole 70C connects the formed exhaustion region of face greater than this N/P, is same as the electrical performance that traditional circuit designs so can reach.In addition, this kind topological design can be dwindled the circuit area, increases resolution and be simplified fabrication steps.
Compared to prior art, the cascaded structure and the method for making of N type thin film transistor (TFT) of the present invention and P type thin film transistor (TFT) have following advantage:
The first, only need to make an independently effective layer 54, and can connect with the N/P of P type thin film transistor (TFT) in N type thin film transistor (TFT) directly that one the 3rd of making contacts hole 70C on the face, can make an end N
+Type doped region 54c
2Conducting currier be electrically connected to the P of the other end with drain electrode conductive layer 72D via the 3rd contact plunger 72C
+Type doped region 54f
1, and can not connect the formed exhaustion region of face by this N/P, so can reach the same electrical sex expression.
The second, the present invention can save effective layer 54 and area that contacts hole 70C and quantity, so can reach the advantage of dwindling the circuit area, increasing resolution and simplifying fabrication steps.Especially in the circuit design of using high integration, for example: (digital analog converter, DAC), this kind cascaded structure can obtain the pixel resolution of preferable AMLCD to digital analog converter.
The 3rd, by the shaded areas 561b that adjusts first, second gate insulator 561,562 of etching condition may command
1, 561b
2, 562b
1, 562b
2Lateral length W
1, W
2, D
1, D
2Therefore, can accurately control the position in LDD zone, to meet the electrical demand of N type thin film transistor (TFT) and P type thin film transistor (TFT).
The 4th, do not need additionally to provide light shield or make sidewall to define the pattern in LDD zone, so can avoid the problem of alignment error (photo misalignment) offset that causes of exposure technique, then can further accurately control the position in LDD zone.
The 5th, reduce primary ions cloth and plant processing procedure, thus have advantages such as the fabrication steps of simplification, reduction processing procedure cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.
Second embodiment
See also Fig. 4, the diagrammatic cross-section of the cascaded structure of the multi-crystal TFT of its demonstration second embodiment of the invention.
The cascaded structure feature of the multi-crystal TFT of second embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.
In N type thin film transistor (TFT) I, first grid insulation course 561 includes one first elongated area 561c in addition
1And one second elongated area 561c
2The first elongated area 561c
1Be to be positioned at the first shaded areas 561b
1The left side, and cover a N
+Doped region 54c
1The second elongated area 561c
2Be to be positioned at the second shaded areas 561b
2The right side, and cover the 2nd N
+Doped region 54c
2Particularly, the first elongated area 561c
1Thickness T
1Less than the first shaded areas 561b
1Thickness T
2, the second elongated area 561c
2Thickness T
1Less than the second shaded areas 561b
2Thickness T
2The feature of second embodiment is by elongated area 561c
1, 561c
2With the polysilicon material of protection below, and can not influence the ion concentration of heavily doped region.Thus, then can utilize the bigger shaded areas 561b of thickness
1, 561b
2As the mask of the ion disposing process in LDD zone, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD zone and source/drain region simultaneously via ion disposing process once.
In the same manner, in P type TFT regions II, second grid insulation course 562 includes one first elongated area 562c in addition
1And one second elongated area 562c
2The first elongated area 562c
1Be to be positioned at the first shaded areas 562b
1The left side, and cover a P
+Doped region 54f
1The second elongated area 562c
2Be to be positioned at the second shaded areas 562b
2The right side, and cover the 2nd P
+Doped region 54f
2Particularly, the first elongated area 562c
1Thickness t
1Less than the first shaded areas 562b
1Thickness t
2, the second elongated area 562c
2Thickness t
1Less than the second shaded areas 562b
2Thickness t
2Thus, utilize the bigger shaded areas 562b of thickness
1, 562b
2As the mask of the ion disposing process in LDD zone, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD zone and source/drain region simultaneously via ion disposing process once.
The method for making of second embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is etching isolation layer 56 with in the process of finishing first grid insulation course 561 and second grid insulation course 562, needs suitably control etch depth, so that elongated area 561c
1, 561c
2Thickness T
1And elongated area 562c
1, 562c
2Thickness t
1Reach a preferred values.The elongated area 561c of first grid insulation course 561
1, 561c
2With shaded areas 561b
1, 561b
2Be by being constituted with one deck material.Or, shaded areas 561b
1, 561b
2Be to form elongated area 561c by one first insulation course and one second insulation course institute storehouse
1, 561c
2Constituted by this first insulation course.Wherein, the preferably of first insulation course is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of second insulation course is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.In addition, can also adopt the insulation course storehouse effect more than three layers or three layers, to reach shaded areas 561b
1, 561b
2With elongated area 561c
1, 561c
2The effect of difference in thickness.The elongated area 562c of second grid insulation course 562
1, 562c
2With shaded areas 562b
1, 562b
2Be by being constituted with one deck material.Or, shaded areas 562b
1, 562b
2Be to form elongated area 562c by one first insulation course and one second insulation course institute storehouse
1, 562c
2Constituted by this first insulation course.Wherein, the preferably of first insulation course is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of second insulation course is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.In addition, can also adopt the insulation course storehouse effect more than three layers or three layers, to reach shaded areas 562b
1, 562b
2With elongated area 562c
1, 562c
2The effect of difference in thickness.
The 3rd embodiment
See also Fig. 5 A～Fig. 5 B, the diagrammatic cross-section of the cascaded structure of the multi-crystal TFT of its demonstration third embodiment of the invention.
The cascaded structure feature of the multi-crystal TFT of the 3rd embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is that the structural design of the shaded areas of gate insulator can only be applied to N type TFT regions I or P type TFT regions II.
Shown in Fig. 5 A, the first grid insulation course 561 in the N type TFT regions I includes first, second shaded areas 561b
1, 561b
2, can be in order to size, position and the symmetry in definition LDD zone; 562 of second grid insulation courses in the P type TFT regions II are not made shaded areas, so can't form the LDD zone in effective layer 54.Shown in Fig. 5 B, the second grid insulation course 562 in the P type TFT regions II includes first, second shaded areas 562b
1, 562b
2, can be in order to size, position and the symmetry in definition LDD zone; 561 of first grid insulation courses in the N type TFT regions I are not made shaded areas, so can't form the LDD zone in effective layer 54.The method for making of the 3rd embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (13)
1. tandem arrangement with thin film transistor (TFT) includes:
One substrate, it includes one first conductivity type thin-film transistor zone and one second conductivity type thin-film transistor zone;
One effective layer is to be formed in this substrate, and includes:
One first channel region is to be formed in this first conductivity type thin-film transistor zone;
The lightly doped region of one first conductivity type is to be formed in this first conductivity type thin-film transistor zone, and is formed at the both sides of this first channel region;
The heavily doped region of one first conductivity type is to be formed in this first conductivity type thin-film transistor zone, and is formed at the both sides of the lightly doped region of this first conductivity type;
One second channel region is to be formed in this second conductivity type thin-film transistor zone; And
The heavily doped region of one second conductivity type is to be formed in this second conductivity type thin-film transistor zone, and is formed at the both sides of this second channel region; And
Wherein, the face that the connects place of the heavily doped region of the heavily doped region of two adjacent these first conductivity types and this second conductivity type forms an exhaustion region;
One first grid insulation course is that this first grid insulation course includes in addition on the effectively layer that is formed in this first conductivity type thin-film transistor zone:
One middle section is to cover this effectively first channel region of layer;
One shaded areas is to cover this effectively lightly doped region of this first conductivity type of layer; And
One elongated area be to extend the heavily doped region that covers to this first conductivity type that is somebody's turn to do effective layer from this shaded areas of this first grid insulation course, and the thickness of this elongated area is less than the thickness of this shaded areas;
One second grid insulation course is on the effectively layer that is formed in this second conductivity type thin-film transistor zone;
One first grid layer is to be formed on this first grid insulation course, and covers the middle section of this first grid insulation course;
One second grid layer is to be formed on this second grid insulation course, and covers this second grid insulation course;
One interlayer dielectric layer is to be formed on this first, second grid layer, this first, second gate insulator and this effective layer, and includes:
One contact hole is that this of heavily doped region that exposes the heavily doped region of this first conductivity type and this second conductivity type meets the face place; And
One conductive layer is to be formed in this contact hole, so that the heavily doped region of this first conductivity type is electrically connected to the heavily doped region of this second conductivity type.
2. the tandem arrangement with thin film transistor (TFT) according to claim 1, wherein the size in this contact hole connects this exhaustion region that the face place forms greater than this.
3. the tandem arrangement with thin film transistor (TFT) according to claim 1, wherein this contact hole is of a size of 3～5 μ m.
4. the tandem arrangement with thin film transistor (TFT) according to claim 1, wherein:
The doping content of the lightly doped region of this first conductivity type is 1 * 10
12～1 * 10
14Atom/cm
2
The doping content of the heavily doped region of this first conductivity type is 1 * 10
14～1 * 10
16Atom/cm
2And
The doping content of the heavily doped region of this second conductivity type is 1 * 10
14～1 * 10
16Atom/cm
2
5. the tandem arrangement with thin film transistor (TFT) according to claim 1, the lightly doped region that wherein more includes one second conductivity type, be to be formed in this second conductivity type thin-film transistor zone, and be formed at the both sides of this second channel region, wherein the lightly doped region of this second conductivity type is between the heavily doped region of this second channel region and this second conductivity type.
6. the tandem arrangement with thin film transistor (TFT) according to claim 5, wherein the doping content of the lightly doped region of this second conductivity type is 1 * 10
12～1 * 10
14Atom/cm
2
7. the tandem arrangement with thin film transistor (TFT) according to claim 1, wherein:
This substrate is a transparent insulation substrate or a substrate of glass;
Effectively layer is a semiconductor silicon layer or a polysilicon layer;
This first grid insulation course is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination; And
This second grid insulation course is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
8. the method for making with tandem arrangement of thin film transistor (TFT) comprises the following steps:
One substrate is provided, and it includes one first conductivity type thin-film transistor zone and one second conductivity type thin-film transistor zone;
Form an effective layer in this substrate;
Form an insulation course in this substrate, to cover effectively layer;
Form one first conductive layer on this insulation course;
Carry out an etch process, this first conductive layer is defined as a first grid layer and a second grid layer, and this insulation course is defined as a first grid insulation course and a second grid insulation course;
Wherein, this first grid insulation course is to be formed in this first conductivity type thin-film transistor zone, and includes the both sides that a middle section and a shaded areas are formed at this middle section;
Wherein, this first grid layer is to be formed in this first conductivity type thin-film transistor zone, and covers the middle section of this first grid insulation course;
Wherein, this second grid insulation course is to be formed in this second conductivity type thin-film transistor zone;
Wherein, this second grid layer is to be formed in this second conductivity type thin-film transistor zone, and covers this second grid insulation course;
Carry out one first ion disposing process, form one first channel region, the lightly doped region of one first conductivity type and the heavily doped region of one first conductivity type in the effectively layer in this first conductivity type thin-film transistor zone;
Wherein, this first channel region is the below that is positioned at this first grid layer;
Wherein, the lightly doped region of this first conductivity type is the both sides that are positioned at this first channel region;
Wherein, the heavily doped region of this first conductivity type is the both sides that are positioned at the lightly doped region of this first conductivity type;
Carry out one second ion disposing process, form the heavily doped region of one second channel region and one second conductivity type in the effectively layer in this second conductivity type thin-film transistor zone;
Wherein, this second channel region is the below that is positioned at this second grid layer;
Wherein, the heavily doped region of this second conductivity type is the both sides that are positioned at this second channel region;
Wherein, the face that the connects place of the heavily doped region of the heavily doped region of two adjacent these first conductivity types and this second conductivity type forms an exhaustion region;
Form an interlayer dielectric layer with the TFT regions that covers this first conductivity type and the TFT regions of this second conductivity type;
Forming a contact hole in this interlayer dielectric layer, is the face that the connects place that exposes the heavily doped region of the heavily doped region of this first conductivity type and this second conductivity type; And
Form one second conductive layer in this second contact hole, so that the heavily doped region of this first conductivity type is electrically connected to the heavily doped region of this second conductivity type.
9. the method for making with tandem arrangement of thin film transistor (TFT) according to claim 8, wherein the size in this contact hole connects this exhaustion region that the face place forms greater than this.
10. the method for making with tandem arrangement of thin film transistor (TFT) according to claim 8, wherein this contact hole is of a size of 3～5 μ m.
11. the method for making with tandem arrangement of thin film transistor (TFT) according to claim 8, wherein:
The doping content of the lightly doped region of this first conductivity type is 1 * 10
12～1 * 10
14Atom/cm
2
The doping content of the heavily doped region of this first conductivity type is 1 * 10
14～1 * 10
16Atom/cm
2And
The doping content of the heavily doped region of this second conductivity type is 1 * 10
14～1 * 10
16Atom/cm
2
12. the method for making with tandem arrangement of thin film transistor (TFT) according to claim 8, wherein this first grid insulation course includes an elongated area in addition, be to extend the heavily doped region that covers to this first conductivity type that is somebody's turn to do effective layer, and the thickness of this elongated area is less than the thickness of this shaded areas from this shaded areas of this first grid insulation course.
13. the method for making with tandem arrangement of thin film transistor (TFT) according to claim 8, wherein:
This substrate is a transparent insulation substrate or a substrate of glass;
Effectively layer is a semiconductor silicon layer or a polysilicon layer;
This first grid insulation course is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination; And
This second grid insulation course is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
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| CN104600082A (en) * | 2015-01-14 | 2015-05-06 | 京东方科技集团股份有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN109860107B (en) * | 2019-01-31 | 2021-03-16 | 武汉华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150907A (en) * | 1993-09-20 | 2000-05-30 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JP2000267139A (en) * | 1999-03-16 | 2000-09-29 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and method for formation thereof |
| JP2002076361A (en) * | 2000-09-05 | 2002-03-15 | Sharp Corp | Semiconductor device, its manufacturing method and image display device |
| JP2002221936A (en) * | 2000-10-24 | 2002-08-09 | Semiconductor Energy Lab Co Ltd | Light emission device and its driving method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150907A (en) * | 1993-09-20 | 2000-05-30 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JP2000267139A (en) * | 1999-03-16 | 2000-09-29 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and method for formation thereof |
| JP2002076361A (en) * | 2000-09-05 | 2002-03-15 | Sharp Corp | Semiconductor device, its manufacturing method and image display device |
| JP2002221936A (en) * | 2000-10-24 | 2002-08-09 | Semiconductor Energy Lab Co Ltd | Light emission device and its driving method |
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