CN100358157C - Thin film transistor and its manufacturing method - Google Patents

Thin film transistor and its manufacturing method Download PDF

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Publication number
CN100358157C
CN100358157C CNB2003101033254A CN200310103325A CN100358157C CN 100358157 C CN100358157 C CN 100358157C CN B2003101033254 A CNB2003101033254 A CN B2003101033254A CN 200310103325 A CN200310103325 A CN 200310103325A CN 100358157 C CN100358157 C CN 100358157C
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layer
doped region
insulating barrier
active layer
shaded areas
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CN1612358A (en
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张世昌
方俊雄
蔡耀铭
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TPO Displays Corp
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Toppoly Optoelectronics Corp
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Abstract

The present invention relates to a thin film transistor and a manufacture method thereof. The thin film transistor comprises a first effective layer which is formed on a first thin film transistor district, wherein the first effective layer comprises a trench district, a lightly doped district and a heavily doped district. A first grid electrode insulation layer is formed on the first effective layer, and comprises a center district and a shielding district. The shielding district covers the lightly doped district of the first effective layer. A second effective layer is formed on a second thin film transistor district, and comprises a trench district, a lightly doped district and a heavily doped district. The second grid electrode insulation layer is formed on second effective layer, and comprises a center district and a shielding district. The shielding district covers the lightly doped district of the second effective layer. The transversal length of the shielding district of the first grid electrode insulation layer is not equal to the transversal length of the shielding district of the second grid electrode insulation layer. The transversal length of the lightly doped district of the first effective layer is not equal to the transversal length of the lightly doped district of the second effective layer.

Description

Thin-film transistor and preparation method thereof
Technical field
The present invention is relevant for a kind of thin-film transistor (thin film transistor, TFT) technology, lightly doped drain (the light1y doped drain of relevant especially a kind of thin-film transistor, LDD) technology of structure, can be at the LDD structure of the TFT establishment of component different length of different operating voltage, also can be at the LDD structure of the asymmetric length of TFT establishment of component.
Background technology
Active matrix liquid crystal display (active matrix liquid crystal display, hereinafter to be referred as AMLCD) the pixel switch assembly be utilization one thin-film transistor (thin filmtransistor, TFT), generally can be divided into non-crystalline silicon tft and two kinds of patterns of multi-crystal TFT in the zone.Because the carrier transport factor integration higher, drive circuit of multi-crystal TFT is preferable, leakage current is less, so multi-crystal TFT more often is applied in the circuit of high service speed, as: static random access memory (static random access memory, SRAM).But the problem of leakage current (leakage current) easily takes place down in multi-crystal TFT in off position, and regular meeting causes LCD loss electric charge or makes the non-firm power consumption of SRAM.In order to address this problem, (lightly doped drain, LDD) structure are used for reducing the electric field of drain junction place (drainjunction), can actively improve the phenomenon of leakage current to adopt a kind of lightly doped drain at present.Prior art is utilized the position and the size of gold-tinted technology definition LDD structure mostly, but along with the reduction of TFT size of components, alignment error of gold-tinted technology (photo misalignment) and considering of critical dimension skew can be more harsh.
Known a kind of method of making the LDD structure is to utilize a photoresist layer as covering curtain to carry out a heavy doping ion injection technology, to form a heavily doped region in a polysilicon layer earlier.Make a grid layer then as covering curtain to carry out a light dope ion implantation technology, so that the not doped region of the exposure of polysilicon layer becomes a lightly doped region.Thus, lightly doped region is to be used as a LDD structure, and heavily doped region is to be used as one source/drain region, and the not doped region of polysilicon layer then is to be used as a channel region.Yet said method must accurately be controlled the position that the pattern of grid layer just can be guaranteed the LDD structure.And, be subject to the alignment error (photomisalignment) of exposure technique, be not easy to control the side-play amount of grid layer, then twice ion implantation technology can make the problem of the offset of LDD structure can be more serious.Very and, the complex process of said method, production speed are low, the lateral length of also wayward LDD structure.In addition, with regard to considering of circuit design, known techniques can't be at the LDD structure of different establishment of component different lengths, so can't meet the requirement on reliability and the service speed.
Summary of the invention
Automatic aligning (self-aligned) LDD structure that provides by a kind of TFT assembly and preparation method thereof just is provided purpose of the present invention, can be at the LDD structure of the TFT establishment of component different length of different operating voltage, can also be at the LDD structure of the asymmetric length of TFT establishment of component, with the requirement on Achieved Reliability and the service speed.
For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor, include a first film transistor area and one second TFT regions.One first active layer is to be formed on this first film transistor area, and includes a channel region, a lightly doped region and a heavily doped region.One first grid insulating barrier is to be formed on this first active layer, and includes a middle section and a shaded areas, and this middle section is the channel region that covers this first active layer, and this shaded areas is the lightly doped region that covers this first active layer.One second active layer is to be formed on this second TFT regions of this substrate, and includes a channel region, a lightly doped region and a heavily doped region.One second grid insulating barrier is to be formed on this second active layer, and includes a middle section and a shaded areas, and this middle section is the channel region that covers this second active layer, and this shaded areas is the lightly doped region that covers this second active layer.The lateral length of the shaded areas of this first grid insulating barrier is not equal to the lateral length of the shaded areas of this second grid insulating barrier.The lateral length of the lightly doped region of this first active layer is not equal to the lateral length of the lightly doped region of this second active layer.
For reaching above-mentioned purpose, the invention provides another kind of thin-film transistor, including an active layer is to be formed in the substrate, and includes a channel region, a lightly doped region, one first heavily doped region and one second heavily doped region.This channel region and this lightly doped region are to be formed between this first heavily doped region and this second heavily doped region, and this lightly doped region is to be formed between this channel region and this second heavily doped region.One gate insulator is to be formed on this active layer, and includes a middle section and a shaded areas.This middle section is the channel region that covers this active layer, and this shaded areas is the lightly doped region that covers this active layer.One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
For reaching above-mentioned purpose, the invention provides another kind of thin-film transistor, including an active layer is to be formed in the substrate, and includes a channel region, one first lightly doped region, one second lightly doped region, one first heavily doped region and one second heavily doped region.This channel region is to be formed between this first lightly doped region and this second lightly doped region, this first lightly doped region is to be formed between this channel region and this first heavily doped region, this second lightly doped region is to be formed between this channel region and this second heavily doped region, and the lateral length of this first lightly doped region is the lateral length that is not equal to this second lightly doped region.One gate insulator is to be formed on this active layer, and includes a middle section, one first shaded areas and one second shaded areas.This middle section is the channel region that covers this active layer, this first shaded areas is first lightly doped region that covers this active layer, this second shaded areas is second lightly doped region that covers this active layer, and the lateral length of this first shaded areas is the lateral length that is not equal to this second shaded areas.One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
Description of drawings
Fig. 1 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of first embodiment of the invention;
The generalized section of the manufacture method of aiming at the LDD structure voluntarily of the TFT assembly of Fig. 2 A to Fig. 2 H demonstration first embodiment of the invention;
Fig. 3 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of second embodiment of the invention;
Fig. 4 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of third embodiment of the invention;
Fig. 5 shows the generalized section of asymmetric LDD structure of the TFT assembly of fourth embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Fig. 6 A to Fig. 6 C demonstration fourth embodiment of the invention;
Fig. 7 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of fifth embodiment of the invention;
Fig. 8 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of sixth embodiment of the invention;
Fig. 9 shows the generalized section of asymmetric LDD structure of the TFT assembly of seventh embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Figure 10 A to Figure 10 C demonstration seventh embodiment of the invention;
Figure 11 shows the generalized section of asymmetric LDD structure of the TFT assembly of eighth embodiment of the invention;
Figure 12 shows the generalized section of asymmetric LDD structure of the TFT assembly of ninth embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Figure 13 A to Figure 13 E demonstration tenth embodiment of the invention.
Symbol description:
Substrate～10,30,50,70
The one TFT zone～I
The 2nd TFT zone～II
Resilient coating～12,32,52,72
Active layer～14,16,34,54,74
Insulating barrier～18,36,56,76
Conductive layer～24,40,60,80
Photoresist layer～26,28,44,64,84
Grid layer～25,27,42,62,82
Gate insulator～20,22,38,58,78
Middle section～20a, 22a, 38a, 58a, 78a
Shaded areas～20b 1, 20b 2, 22b 1, 22b 2, 38b 1, 38b 2, 58b 1, 58b 2, 78b 1, 78b 2
Ion implantation technology～29,46,66,86
Not doped region～14a, 16a, 34a, 54a, 74a
Lightly doped region～14b 1, 14b 2, 16b 1, 16b 2, 34b 1, 34b 2, 54b 1, 54b 2, 74b 1, 74b 2
Heavily doped region～14c 1, 14c 2, 16c 1, 16c 2, 34c 1, 34c 2, 54c 1, 54c 2, 74c 1, 74c 2
Mask～6,87
Zone of opacity～2a, 4a, 87a
Phase transfer zone～2b, 4b, 87b 1, 87b 2
Transparent region～2c, 4c, 87c 1, 87c 2
Photoresist pattern～26I, 26II, 85
First area～26I a, 26II a, 85a
Second area～26I b, 26II b, 85b
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
First embodiment:
First embodiment of the invention is the LDD structure at the TFT establishment of component different length of different operating voltage, as the cover curtain and the primary ions injection technology of arranging in pairs or groups, can reach a making of aiming at LDD structure and one source/drain region voluntarily by the lateral length that is exposed to the grid layer both sides of gate insulator simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a pixel array region and a peripheral drive circuit zone, below is to describe in detail to aim at LDD structure and preparation method thereof voluntarily.
See also Fig. 1, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of first embodiment of the invention.
One substrate 10 includes one the one TFT area I and one the 2nd TFT area I I, and deposits a resilient coating 12 on the surface.In a TFT area I, be manufactured with one first active layer 14, a first grid insulating barrier 20 and a first grid layer 25 on the resilient coating 12 in regular turn.In the 2nd TFT area I I, be manufactured with one second active layer 16, a second grid insulating barrier 22 and a second grid layer 27 on the resilient coating 12 in regular turn.
The preferably of substrate 10 is a transparent insulation substrate, for example: substrate of glass.The one TFT area I or the 2nd TFT area I I are a peripheral drive circuit zone or a pixel array region.The preferably of resilient coating 12 is a dielectric materials layer, and for example: silicon oxide layer, its purpose is formed in the substrate 10 for helping first, second active layer 14,16.The preferably of first, second active layer 14,16 is the semiconductor silicon layer, for example: polysilicon layer.The preferably of first, second gate insulator 20,22 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.The preferably of first, second grid layer 25,27 is a metal level or a polysilicon layer.
It below is the architectural feature of explanation the one TFT area I.First active layer 14 includes not doped region 14a, two lightly doped region 14b 1, 14b 2And two heavily doped region 14c 1, 14c 2Wherein, doped region 14a is not used as a channel region; First, second lightly doped region 14b 1, 14b 2Being to be formed at the not both sides of doped region 14a respectively, is to be used as a LDD structure; First, second heavily doped region 14c 1, 14c 2Be to be formed at first, second lightly doped region 14b respectively 1, 14b 2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 14b 1, 14b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, first, second heavily doped region 14c 1, 14c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2
First grid insulating barrier 20 includes a middle section 20a and two shaded areas 20b 1, 20b 2Wherein, middle section 20a covers not doped region 14a; The first shaded areas 20b 1Be to be positioned at middle section 20a left side, and cover the first lightly doped region 14b 1The second shaded areas 20b 2Be to be positioned at middle section 20a right side, and cover the second lightly doped region 14b 2The bottom of first grid layer 25 is to cover middle section 20a.Thus, then can utilize shaded areas 20b 1, 20b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Shaded areas 20b 1, 20b 2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 14b 1Width be to correspond to the first shaded areas 20b 1Width W 1, and the second lightly doped region 14b 2Width be to correspond to the second shaded areas 20b 2Width W 2The preferably is the first shaded areas 20b 1Lateral length W 1Be 0.1 μ m～2.0 μ m, the second shaded areas 20b 2Lateral length W 2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W 1, W 2Length and symmetry thereof, the preferably is: W 1=W 2
It below is the architectural feature of explanation the 2nd TFT area I I.Second active layer 16 includes not doped region 16a, two lightly doped region 16b 1, 16b 2And two heavily doped region 16c 1, 16c 2Wherein, doped region 16a is not used as a channel region; First, second lightly doped region 16b 1, 16b 2Being to be formed at the not both sides of doped region 16a respectively, is to be used as a LDD structure; First, second heavily doped region 16c 1, 16c 2Be to be formed at first, second lightly doped region 16b respectively 1, 16b 2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 16b 1, 16b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, first, second heavily doped region 16c 1, 16c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2
Second grid insulating barrier 22 includes a middle section 22a and two shaded areas 22b 1, 22b 2Wherein, middle section 22a covers not doped region 16a; The first shaded areas 22b 1Be to be positioned at middle section 22a left side, and cover the first lightly doped region 16b 1The second shaded areas 22b 2Be to be positioned at middle section 22a right side, and cover the second lightly doped region 16b 2The bottom of second grid layer 27 is to cover middle section 22a.Shaded areas 22b 1, 22b 2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 16b 1Width be to correspond to the first shaded areas 22b 1Width D 1, and the second lightly doped region 16b 2Width be to correspond to the second shaded areas 22b 2Width D 2The preferably is the first shaded areas 22b 1Lateral length D 1Be 0.1 μ m～2.0 μ m, the second shaded areas 22b 2Lateral length D 2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust D 1, D 2Length and symmetry thereof, also can be: D 1=D 2In addition, can adjust W according to the reliability of circuit design, the demand of electric current 1, W 2, D 1, D 2Between relation so that W 1(or W 2) be not equal to D 1(or D 2), the preferably shown in the 1st figure is: a TFT area I is as a pixel array region, the 2nd TFT area I I is as a peripheral drive circuit zone, and W 1(or W 2)＞D 1(or D 2).
See also Fig. 2 A to Fig. 2 G, the generalized section of the manufacture method of aiming at the LDD structure voluntarily of the TFT assembly of its demonstration first embodiment of the invention.
At first, shown in Fig. 2 A, provide a substrate 10, it includes one the one TFT area I and one the 2nd TFT area I I.Then, deposition one resilient coating 12 in substrate 10 is again respectively at making first, second active layer 14,16 on the resilient coating 12 of first, second TFT area I, II.The present invention does not limit thickness of first, second active layer 14,16 and preparation method thereof, for instance, can adopt low temperature polycrystalline silicon (low temperature polycrystalline silicon, LTPS) technology, prior to forming a noncrystalline silicon layer on the glass substrate, (excimer laser annealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize the annealing of heat treatment or excimer laser then.
Then, shown in Fig. 2 B, on first, second active layer 14,16, deposit an insulating barrier 18 and a conductive layer 24 in regular turn.The preferably of insulating barrier 18 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.The preferably of conductive layer 24 is a metal level or a polysilicon layer.
Thereafter, shown in Fig. 2 C, on conductive layer 24, form first photoresist layer 26 of a patterning,, and make first photoresist layer 26 cover whole the 2nd TFT area I I so that first photoresist layer 26 covers the zone of the pre-defined gate pattern of a TFT area I.Follow-up, shown in Fig. 2 D, first photoresist layer 26 that utilizes patterning is as covering curtain to carry out an etch process, pattern with 24 definition becoming of the conductive layer in a TFT area I first grid layer 25, and, follow-up first photoresist layer 26 is removed the pattern of the insulating barrier in the TFT area I 18 definition becoming a first grid insulating barrier 20.
The profile preferably of first grid layer 25 is one up-narrow and down-wide trapezoidal.First grid insulating barrier 20 includes a middle section 20a, one first shaded areas 20b 1And one second shaded areas 20b 2, middle section 20a is covered by the bottom of first grid layer 25, and first, second shaded areas 20b 1, 20b 2Be the two bottom sides that is exposed to first grid layer 25, and first grid insulating barrier 20 expose the predetermined origin/drain diffusion region of first active layer 14.The preferably is the first shaded areas 20b 1Lateral length W 1Be 0.1 μ m～2.0 μ m, the second shaded areas 20b 2Lateral length W 2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W 1, W 2Length and symmetry thereof, also can be: W 1=W 2
The etch process preferably of this step is plasma etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.For example: in the etching process of conductive layer 24, the flow of chlorine-containing gas can be adjusted to gradually greatly, or even only use chlorine-containing gas as etching reaction gas, aerating oxygen or strengthen oxygen flow simultaneously again when waiting to be etched to insulating barrier 18, simultaneously part first photoresist layer 26 and the grid layer 25 that exposes are once again carried out etching, the profile of first grid layer 25 can be made become one up-narrow and down-wide trapezoidally, and produces first, second shaded areas 20b of first grid insulating barrier 20 1, 20b 2
Then, shown in Fig. 2 E, provide second photoresist layer 28 of a patterning,, and make second photoresist layer 28 cover the zone of the pre-defined gate pattern of the 2nd TFT area I I so that second photoresist layer 28 covers a whole TFT area I.Follow-up, shown in Fig. 2 F, second photoresist layer 28 that utilizes patterning is as covering curtain to carry out an etch process, pattern with 24 definition becoming of the conductive layer in the 2nd a TFT area I I second grid layer 27, and, follow-up second photoresist layer 28 is removed the pattern of the insulating barrier in the 2nd TFT area I I 18 definition becoming a second grid insulating barrier 22.
The profile preferably of second grid layer 27 is one up-narrow and down-wide trapezoidal.Second grid insulating barrier 22 includes a middle section 22a, one first shaded areas 22b 1And one second shaded areas 22b 2, middle section 22a is covered by the bottom of second grid layer 27, and first, second shaded areas 22b 1, 22b 2Be the two bottom sides that is exposed to second grid layer 27, and second grid insulating barrier 22 expose the predetermined origin/drain diffusion region of second active layer 16.The preferably is the first shaded areas 22b 1Lateral length D 1Be 0.1 μ m～2.0 μ m, the second shaded areas 22b 2Lateral length D 2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust D 1, D 2Length and symmetry thereof, also can be: D 1=D 2In addition, relatively the structure of first grid insulating barrier 20 and second grid insulating barrier 22 can be adjusted W according to the reliability of circuit design, the demand of electric current 1, W 2, D 1, D 2Between relation so that W 1(or W 2) be not equal to D 1(or D 2), the preferably is: the LDD lateral length of the TFT in LDD lateral length＞peripheral drive circuit zone of the TFT of pixel array region.
The engraving method of this step is described similar in appearance to Fig. 2 D, can use plasma etching (plasmaetching) or reactive ion etching method, maybe can use a mist with oxygen-containing gas and chlorine-containing gas as etching gas, and according to the flow or the etching period that need to adjust individual gases in good time.
At last, shown in Fig. 2 G, carry out an ion implantation technology 29, utilize the shaded areas 20b of first grid layer 25, first grid insulating barrier 20 1, 20b 2As cover curtain, then can in first active layer 14, form not doped region 14a, two lightly doped region 14b 1, 14b 2And two heavily doped region 14c 1, 14c 2Wherein, doped region 14a is not the corresponding below that is formed at middle section 20a, is to be used as a channel region; First, second lightly doped region 14b 1, 14b 2Be corresponding first, second shaded areas 20b that is formed at 1, 20b 2The below, be to be used as a LDD structure; First, second heavily doped region 14c 1, 14c 2Being the two bottom sides that is exposed to first grid insulating barrier 20, is to be used as one source/drain diffusion region.Because the shaded areas 20b of first grid insulating barrier 20 1, 20b 2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 14b 1Width be to correspond to the first shaded areas 20b 1Width W 1, and the second lightly doped region 14b 2Width be to correspond to the second shaded areas 20b 2Width W 2
When carrying out ion implantation technology 29, can utilize the shaded areas 22b of second grid layer 27 and second grid insulating barrier 22 1, 22b 2As cover curtain, then can in second active layer 16, form not doped region 16a, two lightly doped region 16b 1, 16b 2And two heavily doped region 16c 1, 16c 2Wherein, doped region 16a is not the corresponding below that is formed at middle section 22a, is to be used as a channel region; First, second lightly doped region 16b 1, 16b 2Be corresponding first, second shaded areas 22b that is formed at 1, 22b 2The below, be to be used as a LDD structure; First, second heavily doped region 16c 1, 16c 2Being the two bottom sides that is exposed to second grid insulating barrier 22, is to be used as one source/drain diffusion region.Because the shaded areas 22b of second grid insulating barrier 22 1, 22b 2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 16b 1Width be to correspond to the first shaded areas 22b 1Width D 1, and the second lightly doped region 16b 2Width be to correspond to the second shaded areas 22b 2Width D 2
For a TFT area I, the preferably is first, second lightly doped region 14b 1, 14b 2Transverse width W 1, W 2Be 0.1～2.0 μ m, the injection energy is 10～100keV, first, second lightly doped region 14b 1, 14b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of heavily doped region 14c is 1 * 10 14～1 * 10 16Atom/cm 2
For the 2nd TFT area I I, the preferably is first, second lightly doped region 16b 1, 16b 2Transverse width D 1, D 2Be 0.1～2.0 μ m, the injection energy is 10～100keV, first, second lightly doped region 16b 1, 16b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of heavily doped region 16c is 1 * 10 14～1 * 10 16Atom/cm 2
The inventive method can be applicable to a P type silicon base, and then the LDD structure is a N -Doped region, and source/drain diffusion region is a N +Doped region.The inventive method also can be applicable to a N type silicon base, and then the LDD structure is a P -Doped region, and source/drain region is a P +Doped region.
Follow-uply carry out interconnected technology, include inter-dielectric layer, contact hole and interconnected making, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.
From the above, TFT assembly of first embodiment of the invention and preparation method thereof has the following advantages:
The first, by the shaded areas 20b that adjusts first, second gate insulator 20,22 of etching condition may command 1, 20b 2, 22b 1, 22b 2Lateral length W 1, W 2, D 1, D 2Therefore, can accurately control the position of LDD structure, to meet the electrical demand of TFT assembly.
The second, do not need additionally to provide mask or make sidewall to define the pattern of LDD structure, so can avoid the problem of alignment error (photo misalignment) offset that causes of exposure technique, then can further accurately control the position of LDD structure.
The 3rd, reduce one time the light dope injection technology, thus have advantages such as the processing step of simplification, reduction technology cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.
The 4th, the inventive method can be simultaneously carried out doping process adjusting its component characteristic to a TFT area I and the 2nd TFT area I I, and the shaded areas 20b of first, second gate insulator 20,22 of may command 1, 20b 2, 22b 1, 22b 2Lateral length W 1, W 2, D 1, D 2So, can be at the LDD structure of the establishment of component different length of different operating voltage, with the requirement on Achieved Reliability and the service speed.
In addition, see also Fig. 2 H, the manufacture method of first embodiment of the invention, also can utilize a decrescendo phase transfer mask (attenuated phase shifting mask) and collocation to carry out photoetching process one time, then the grid layer that can define a TFT area I and the 2nd TFT area I I simultaneously by convex character shape pattern photoresist layer and etch process with the pattern of gate insulator.
After finishing the step shown in Fig. 2 A and Fig. 2 B, provide a decrescendo phase transfer (attenuatedphase shifting) mask 6 so that first photoresist layer 26 is carried out exposure imaging technology, can make first photoresist layer 26 of a TFT area I become the photoresist pattern 26I of a convex character shape, and make first photoresist layer 26 of the 2nd TFT area I I become the photoresist pattern 26II of a convex character shape simultaneously.For example, decrescendo phase transfer mask 6 includes a first exposure area 2 and one second exposure area 4.First exposure area 2 is to be positioned at a TFT area I, and includes: a light tight regional 2a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; The regional 2b of a pair of phase transfer (phase-shifting) is the both sides that are positioned at light tight regional 2a, and its position and size are with respect to a predetermined lightly doped region; Pair of light-transmissive zone 2c is the both sides that are positioned at phase transfer zone 2b, and its position and size are with respect to a predetermined heavy and light doped region.Generally speaking, phase transfer zone 2b and transmission region 2c have different light transmittances, and its light transmittance difference can be done suitable design according to product and technology.Similarly, second portion exposure area 4 is to be positioned at the 2nd TFT area I I, and includes: a light tight regional 4a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; A pair of phase transfer zone 4b is the both sides that are positioned at light tight regional 4a, and its position and size are with respect to a predetermined lightly doped region; Pair of light-transmissive zone 4c is the both sides that are positioned at phase transfer zone 4b, and its position and size are with respect to a predetermined heavy and light doped region.Generally speaking, phase transfer zone 4b and transmission region 4c have different light transmittances, and its light transmittance difference can be done suitable design according to product and technology.
Thus, utilize the decrescendo mask eurymeric photoresist material of arranging in pairs or groups to carry out after the photoetching process, different light transmittances by each zone, can make each opposite position of first photoresist layer 26 accept the exposure effect of varying strength, so that the etched degree of depth difference of each opposite position, just can make the first area 26I of the photoresist pattern 26I of convex character shape aThickness greater than second area 26I bThickness.In the same manner, the first area 26II of the photoresist pattern 26II of convex character shape aThickness greater than second area 26II bThickness.As for second area 26I b, 26II bLateral length then depend on the lateral length design of LDD structure.
Thereafter, utilize the photoresist pattern 26I of convex character shape, 26II is as covering curtain to carry out etch process, with photoresist pattern 26I, conductive layer 24 beyond the 26II and insulating barrier 18 are removed, continue etching again with photoresist pattern 26I, the 26II thinning is until removing second area 26Ib fully, the conductive layer 24 of 26IIb and below thereof, then conductive layer 24 definition can be become first grid layer 25, the pattern of second grid layer 27, and insulating barrier 18 definition can be become first grid insulating barrier 20, the pattern of second grid insulating barrier 22, follow-up with after 26 removals of first photoresist layer, the result is as shown in Fig. 2 F.Follow-up ion implantation technology 29 and the result thereof of carrying out is as shown in Fig. 2 G, so book in detail.
Second embodiment:
See also Fig. 3, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of second embodiment of the invention.
The TFT assembly of second embodiment is roughly described identical with first embodiment with architectural feature, and something in common no longer repeats book.
In a TFT area I, first grid insulating barrier 20 includes one first elongated area 20c in addition 1And one second elongated area 20c 2The first elongated area 20c 1Be to be positioned at the first shaded areas 20b 1The left side, and cover the first heavily doped region 14c 1The second elongated area 20c 2Be to be positioned at the second shaded areas 20b 2The right side, and cover the second heavily doped region 14c 2Particularly, the first elongated area 20c 1Thickness T 1Less than the first shaded areas 20b 1Thickness T 2, also can make the first elongated area 20c 1Thickness T 1Near a minimum.In the same manner, the second elongated area 20c 2Thickness T 1Less than the second shaded areas 20b 2Thickness T 2, also can make the second elongated area 20c 2Thickness T 1Near a minimum.The feature of second embodiment is the elongated area that keeps gate insulator in the TFT zone, can protect the polysilicon material of the grid layer of below, and can not influence the ion concentration of heavily doped region.Thus, then can utilize the bigger shaded areas 20b of thickness 1, 20b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
In the same manner, in the 2nd TFT area I I, second grid insulating barrier 22 includes one first elongated area 22c in addition 1And one second elongated area 22c 2The first elongated area 22c 1Be to be positioned at the first shaded areas 22b 1The left side, and cover the first heavily doped region 16b 1The second elongated area 22c 2Be to be positioned at the second shaded areas 22b 2The right side, and cover the second heavily doped region 16b 2Particularly, the first elongated area 22c 1Thickness t 1Less than the first shaded areas 22b 1Thickness t 2, also can make the first elongated area 22c 1Thickness t 1Near a minimum.In the same manner, the second elongated area 22c 2Thickness t 1Less than the second shaded areas 22b 2Thickness t 2, also can make the second elongated area 22c 2Thickness t 1Near a minimum.Thus, then can utilize the bigger shaded areas 22b of thickness 1, 22b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for second embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is etching isolation layer 18 with in the process of finishing first grid insulating barrier 20 and second grid insulating barrier 22, needs suitably control etch depth, so that elongated area 20c 1, 20c 2Thickness T 1And elongated area 22c 1, 22c 2Thickness t 1Reach a preferred values.
The 3rd embodiment:
See also Fig. 4, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of third embodiment of the invention.
The TFT assembly of the 3rd embodiment is roughly described identical with second embodiment with architectural feature, and something in common no longer repeats book.
In a TFT area I, first grid insulating barrier 20 is to be formed by one first insulating barrier 20I and one second insulating barrier 20II institute storehouse.The preferably of the first insulating barrier 20I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 20II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 20a, the double-decker of the first insulating barrier 20I and the second insulating barrier 20II is to cover channel region 14a.Be positioned at shaded areas 20b 1, 20b 2In, the double-decker of the first insulating barrier 20I and the second insulating barrier 20II is to cover the LDD structure.Be positioned at elongated area 20c 1, 20c 2In, the single layer structure of the first insulating barrier 20I is covering source/drain region.Therefore, in comparison, elongated area 20c 1, 20c 2The thickness T of interior first grid insulating barrier 20 1Less, and shaded areas 20b 1, 20b 2The thickness T of interior first grid insulating barrier 20 2Bigger.Thus, then can utilize the bigger shaded areas 20b of thickness 1, 20b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
In the same manner, in the 2nd TFT area I I, second grid insulating barrier 22 is to be formed by one first insulating barrier 22I and one second insulating barrier 22II institute storehouse.The preferably of the first insulating barrier 22I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 22II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 22a, the double-decker of the first insulating barrier 22I and the second insulating barrier 22II is to cover channel region 16a.Be positioned at shaded areas 22b 1, 22b 2In, the double-decker of the first insulating barrier 22I and the second insulating barrier 22II is to cover the LDD structure.Be positioned at elongated area 22c 1, 22c 2In, the single layer structure of the first insulating barrier 22I is covering source/drain region.Therefore, in comparison, elongated area 22c 1, 22c 2The thickness t of interior second grid insulating barrier 22 1Less, and shaded areas 22b 1, 22b 2The thickness t of interior second grid insulating barrier 22 2Bigger.Thus, then can utilize the bigger shaded areas 22b of thickness 1, 22b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for the 3rd embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is etching isolation layer 18 with in the process of finishing first grid insulating barrier 20 and second grid insulating barrier 22, needs suitably control etch depth, so that elongated area 20c 1, 20c 2Thickness T 1And elongated area 22c 1, 22c 2Thickness t 1Reach a preferred values.
The 4th embodiment:
Fourth embodiment of the invention is at an one-sided LDD structure of TFT establishment of component, by gate insulator be exposed to the one-sided shaded areas of grid layer as the cover curtain and the primary ions injection technology of arranging in pairs or groups, can finish an one-sided LDD structure and a pair of source territory simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is to describe asymmetric LDD structure and preparation method thereof in detail.
See also Fig. 5, the generalized section of the asymmetric LDD structure of the TFT assembly of demonstration fourth embodiment of the invention.
Be manufactured with a resilient coating 32, an active layer 34, a gate insulator 38 and a grid layer 42 on one substrate, 30 surfaces in regular turn.The preferably of substrate 30 is a transparent insulation substrate or a substrate of glass, the preferably of resilient coating 32 is a dielectric materials layer or one silica layer, the preferably of active layer 34 is a semiconductor silicon layer or a polysilicon layer, the preferably of gate insulator 38 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of grid layer 42 is a metal level or a polysilicon layer.
Active layer 34 includes not doped region 34a, a lightly doped region 34b and two heavily doped region 34c 1, 34c 2Doped region 34a is not used as a channel region.Lightly doped region 34b is formed at the not right side of doped region 34a, is to be used as a LDD structure; The first heavily doped region 34c 1Be to be formed at the not left side of doped region 14a, and the second heavily doped region 34c 2Being the right side that is formed at lightly doped region 14b, is to be used as one source/drain diffusion region.The doping content of lightly doped region 34b is 1 * 10 12～1 * 10 14Atom/cm 2, heavily doped region 34c 1, 34c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2
Gate insulator 38 includes a middle section 38a and a shaded areas 38b.Middle section 38a covers not doped region 34a.Shaded areas 38b is the right side that is positioned at middle section 38a, and covers lightly doped region 34b.The bottom of grid layer 42 is to cover middle section 38a.Thus, then can utilize the cover curtain of shaded areas 38b as the ion implantation technology of LDD structure, and the injection energy and the dosage of collocation adjustment ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Shaded areas 38b is the cover curtain that is used as the LDD structure, so the width of lightly doped region 34b is the width W that corresponds to shaded areas 38b.The preferably is that the lateral length W of shaded areas 38b is 0.1 μ m～2.0 μ m.
See also Fig. 6 A to Fig. 6 C, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration fourth embodiment of the invention.
At first, as shown in Figure 6A, deposition one resilient coating 32 in a substrate 30 is made an active layer 34 again on the presumptive area of resilient coating 32, deposit an insulating barrier 36 and a conductive layer 40 more in regular turn, the follow-up photoresist layer 44 of definition one patterning on conductive layer 40 again.The preferably of insulating barrier 36 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 40 is a metal level or a polysilicon layer.
Fig. 6 B shows the layout plane graph of photoresist layer 44 and active layer 34, and Fig. 6 A is the generalized section that shows photoresist layer 44 and active layer 34 along the tangent line 6-6 of Fig. 6 B.The photoresist layer 44 of patterning is to correspond to a pre-defined gate layer pattern.
Thereafter, shown in Fig. 6 C, the photoresist layer 44 that utilizes patterning can be with the pattern of conductive layer 40 definition a becoming grid layer 42 as covering curtain to carry out an etch process, and can be with the pattern of insulating barrier 36 definition a becoming gate insulator 38, follow-up photoresist layer 44 is removed.Gate insulator 38 includes a middle section 38a and a shaded areas 38b, middle section 38a is covered by the bottom of grid layer 42, shaded areas 38b is bottom one side that is positioned at the side of middle section 38a and is exposed to grid layer 42, and gate insulator 38 exposes the predetermined origin/drain diffusion region of active layer 34.The preferably is that the lateral length W of shaded areas 38b is 0.1 μ m～2.0 μ m.The etch process preferably of this step is plasma etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, carry out an ion implantation technology 46, the shaded areas 38b that utilizes grid layer 42 and gate insulator 38 is as the cover curtain, then can form not doped region 34a, a lightly doped region 34b and two heavily doped region 34c in active layer 34 1, 34c 2Wherein, doped region 34a is not the corresponding below that is formed at middle section 38a, is to be used as a channel region; Lightly doped region 34b correspondingly is formed at the below of shaded areas 38b and is formed at the one-sided of channel region 34a, is to be used as a LDD structure; Two heavily doped region 34c 1, 34c 2Being the two bottom sides that is exposed to gate insulator 38 respectively, is to be used as one source/drain diffusion region.Because the shaded areas 38b of gate insulator 38 is the cover curtains that are used as the LDD structure, so the width of lightly doped region 34b is the width W that corresponds to shaded areas 38b.
The preferably is, the transverse width W of lightly doped region 34b is 0.1～2.0 μ m, and the injection energy is 10～100keV, and the doping content of lightly doped region 34b is 1 * 10 12～1 * 10 14Atom/cm 2, heavily doped region 34c 1, 34c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N -Doped region, and source/drain diffusion region is a N +Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P -Doped region, and source/drain region is a P +Doped region.
Follow-uply carry out interconnected technology, include inter-dielectric layer, contact hole and interconnected making, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.
From the above, TFT assembly of fourth embodiment of the invention and preparation method thereof has the following advantages:
The first, by adjusting the just lateral length W of the shaded areas 38b of may command gate insulator 38 of etching condition, therefore can accurately control the position of LDD structure, to meet the electrical demand of TFT assembly.
The second, do not need additionally to provide mask or make sidewall to define the pattern of LDD structure, so can avoid the problem of alignment error (photo misalignment) offset that causes of exposure technique, then can further accurately control the position of LDD structure.
The 3rd, reduce and use a mask, thus have advantages such as the processing step of simplification, reduction technology cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.
The 4th, the inventive method is by the one-sided shaded areas 38b of the gate insulator 38 cover curtain as the ion implantation technology of LDD structure, therefore can be in LDD structure of one-sided formation of the channel region 34a of active layer 34, with the reliability that meets special operational voltage assembly and the requirement on the service speed.
The 5th embodiment:
See also Fig. 7, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of fifth embodiment of the invention.
The TFT assembly of the 5th embodiment is roughly described identical with the 4th embodiment with architectural feature, and something in common no longer repeats book.
Gate insulator 38 includes an elongated area 38c in addition, is to be positioned at shaded areas 38b right side, and covers the second heavily doped region 34c 2Particularly, the thickness T of elongated area 38c 1Thickness T less than shaded areas 38b 2, also can make the thickness T of elongated area 38c 1Near a minimum.Thus, then can utilize the cover curtain of the bigger shaded areas 38b of thickness as the ion implantation technology of LDD structure, and the injection energy and the dosage of collocation adjustment ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for the 5th embodiment is roughly described identical with the 4th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 36 with in the process of finishing gate insulator 38, needs suitably control etch depth, so that the thickness T of elongated area 38c 1Reach a preferred values.
The 6th embodiment:
See also Fig. 8, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of sixth embodiment of the invention.
The TFT assembly of the 6th embodiment is roughly described identical with the 5th embodiment with architectural feature, and something in common no longer repeats book.
Gate insulator 38 is to be formed by one first insulating barrier 38I and one second insulating barrier 38II institute storehouse.The preferably of the first insulating barrier 38I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 38II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 38a, the double-decker of the first insulating barrier 38I and the second insulating barrier 38II is to cover channel region 34a.Be positioned at shaded areas 38b, the double-decker of the first insulating barrier 38I and the second insulating barrier 38II is to cover the LDD structure.Be positioned at elongated area 38c, the single layer structure of the first insulating barrier 38I is covering source/drain region.Therefore, in comparison, the thickness T of the gate insulator 38 in the 38c of elongated area 1Less, and the thickness T of the gate insulator 38 in the shaded areas 38b 2Bigger.Thus, then can utilize the cover curtain of the bigger shaded areas 38b of thickness as the ion implantation technology of LDD structure, and the injection energy and the dosage of collocation adjustment ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for the 6th embodiment is roughly described identical with the 5th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 36 with in the process of finishing gate insulator 38, needs suitably to control the etch depth of the first insulating barrier 38I and the second insulating barrier 38II, so that the thickness T of elongated area 38c 1Reach a preferred values.
The 7th embodiment:
Seventh embodiment of the invention is the LDD structure at the asymmetric length of TFT establishment of component bilateral, by the asymmetric length that is exposed to the grid layer both sides of gate insulator as the cover curtain and the primary ions injection technology of arranging in pairs or groups, LDD structure and the pair of source territory that can finish two asymmetric length simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is to describe asymmetric LDD structure and preparation method thereof in detail.
See also Fig. 9, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration seventh embodiment of the invention.
One substrate 50 includes a resilient coating 52, an active layer 54, a gate insulator 58 and a grid layer 62.The preferably of resilient coating 52 is a dielectric materials layer or one silica layer, the preferably of active layer 54 is a semiconductor silicon layer or a polysilicon layer, the preferably of two gate insulators 58 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of grid layer 62 is a metal level or a polysilicon layer.
Active layer 54 includes not doped region 54a, two lightly doped region 54b 1, 54b 2And two heavily doped region 54c 1, 54c 2Wherein, doped region 54a is not used as a channel region; First, second lightly doped region 54b 1, 54b 2Being to be formed at the not both sides of doped region 54a respectively, is to be used as a LDD structure; First, second heavily doped region 54c 1, 54c 2Be to be formed at first, second lightly doped region 54b respectively 1, 54b 2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 54b 1, 54b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, heavily doped region 54c 1, 54c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2
Gate insulator 58 includes a middle section 58a and two shaded areas 58b 1, 58b 2Wherein, middle section 58a covers not doped region 54a; The first shaded areas 58b 1Be to be positioned at middle section 58a left side, and cover the first lightly doped region 54b 1The second shaded areas 58b 2Be to be positioned at middle section 58a right side, and cover the second lightly doped region 54b 2The bottom of first grid layer 62 is to cover middle section 58a.Thus, then can utilize shaded areas 58b 1, 58b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Shaded areas 58b 1, 58b 2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 54b 1Width be to correspond to the first shaded areas 58b 1Width W 1, and the second lightly doped region 54b 2Width be to correspond to the second shaded areas 58b 2Width W 2The preferably is the lateral length W of the first shaded areas 58b1 1Be 0.1 μ m～2.0 μ m, the second shaded areas 58b 2Lateral length W 2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W 1, W 2Length and asymmetry thereof so that W 1Be not equal to W 2, the preferably is W 1＜W 2
See also Figure 10 A to Figure 10 C, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration seventh embodiment of the invention.
At first, shown in Figure 10 A, deposition one resilient coating 52 in a substrate 50 is made an active layer 54 again on the presumptive area of resilient coating 52, deposit an insulating barrier 56 and a conductive layer 60 more in regular turn, the follow-up photoresist layer 64 of definition one patterning on conductive layer 60 again.The preferably of insulating barrier 56 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 60 is a metal level or a polysilicon layer.
Figure 10 B shows the layout plane graph of photoresist layer 64 and active layer 54, and 10A figure is the generalized section that shows photoresist layer 64 and active layer 54 along the tangent line 10-10 of 10B figure.The photoresist layer 64 of patterning is to correspond to a pre-defined gate layer pattern.
Thereafter, shown in Figure 10 C, the photoresist layer 64 that utilizes patterning can be with the pattern of conductive layer 60 definition a becoming grid layer 62 as covering curtain to carry out an etch process, and can be with the pattern of insulating barrier 56 definition a becoming gate insulator 58, follow-up photoresist layer 64 is removed.Gate insulator 58 includes a middle section 58a, one first shaded areas 58b 1And one second shaded areas 58 b2, middle section 58a is covered by the bottom of grid layer 62, the first shaded areas 58b 1Be the bottom left that is positioned at the left side of middle section 58a and is exposed to grid layer 62, the second shaded areas 58b 2Be the right side, bottom that is positioned at the right side of middle section 58a and is exposed to grid layer 62, and gate insulator 58 expose the predetermined origin/drain diffusion region of active layer 54.The preferably is the first shaded areas 58b 1Lateral length W 1Be 0.1 μ m～2.0 μ m, the second shaded areas 58b 2Lateral length W 2Be 0.1 μ m～2.0 μ m, and W 1Be not equal to W 2The graphic demonstration W of second embodiment 1＜W 2The etch process preferably of this step is plasma etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, carry out an ion implantation technology 66, utilize grid layer 62 with the shaded areas 58b of gate insulator 58 1, 58b 2As cover curtain, then can in active layer 54, form not doped region 54a, two lightly doped region 54b 1, 54b 2And two heavily doped region 54c 1, 54c 2Wherein, doped region 54a is not the corresponding below that is formed at middle section 58a, is to be used as a channel region; The first lightly doped region 54b 1Be the corresponding first shaded areas 58b that is formed at 1The below, the second lightly doped region 54b 2Be the corresponding second shaded areas 58b that is formed at 2The below, be to be used as a LDD structure; Heavily doped region 54c 1, 54c 2Being the two bottom sides that is exposed to gate insulator 58, is to be used as one source/drain diffusion region.Because the shaded areas 58b of gate insulator 58 1, 58b 2Be the cover curtain that is used as the LDD structure, so lightly doped region 54b 1, 54b 2Width be to correspond to shaded areas 58b 1, 58b 2Width W 1, W 2
The preferably is the first lightly doped region 54b 1Transverse width W 1Be 0.1～2.0 μ m, the second lightly doped region 54b 2Transverse width W 2Be 0.1～2.0 μ m, and W 1Be not equal to W 2The injection energy is 10～100keV, lightly doped region 54b 1, 54b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, heavily doped region 54c 1, 54c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N -Doped region, and source/drain diffusion region is a N +Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P -Doped region, and source/drain region is a P +Doped region.
Follow-uply carry out interconnected technology, include inter-dielectric layer, contact hole and interconnected making, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.
From the above, TFT assembly of seventh embodiment of the invention and preparation method thereof is same as the described advantage of the 4th embodiment except having, still can be by the shaded areas 58b of the asymmetric length of bilateral of gate insulator 58 1, 58b 2As the cover curtain of the ion implantation technology of LDD structure, therefore can form two asymmetric LDD structures of length, with the reliability that meets special operational voltage assembly and the requirement on the service speed in the bilateral of the channel region 54a of active layer 54.
The 8th embodiment:
See also Figure 11, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration eighth embodiment of the invention.
The TFT assembly of the 8th embodiment is roughly described identical with the 7th embodiment with architectural feature, and something in common no longer repeats book.
Gate insulator 58 includes two elongated area 58c in addition 1, 58c 2, be to lay respectively at first, second shaded areas 58b 1, 58b 2The outside, and cover first, second heavily doped region 54c respectively 1, 54c 2Particularly, elongated area 58c 1, 58c 2Thickness T 1Less than shaded areas 58b 1, 58b 2Thickness T 2, also can make elongated area 58c 1, 58c 2Thickness T 1Near a minimum.Thus, then can utilize the bigger shaded areas 58b of thickness 1, 58b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for the 8th embodiment is roughly described identical with the 7th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 56 with in the process of finishing gate insulator 58, needs suitably control etch depth, so that elongated area 58c 1, 58c 2Thickness T 1Reach a preferred values.
The 9th embodiment:
See also Figure 12, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration ninth embodiment of the invention.
The TFT assembly of the 9th embodiment is roughly described identical with the 8th embodiment with architectural feature, and something in common no longer repeats book.
Gate insulator 58 is to be formed by one first insulating barrier 58I and one second insulating barrier 58II institute storehouse.The preferably of the first insulating barrier 58I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 58II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 58a, the double-decker of the first insulating barrier 58I and the second insulating barrier 58II is to cover channel region 54a.Be positioned at shaded areas 58b 1, 58b 2In, the double-decker of the first insulating barrier 58I and the second insulating barrier 58II is to cover the LDD structure.Be positioned at elongated area 58c 1, 58c 2In, the single layer structure of the first insulating barrier 58I is covering source/drain region.Therefore, in comparison, elongated area 58c 1, 58c 2The thickness T of interior gate insulator 58 1Less, and shaded areas 58b 1, 58b 2The thickness T of interior gate insulator 58 2Bigger.Thus, then can utilize the bigger shaded areas 58b of thickness 1, 58b 2As the cover curtain of the ion implantation technology of LDD structure, and collocation adjusts the injection energy and the dosage of ion implantation technology, then just can finish the making of LDD structure and source/drain region simultaneously via ion implantation technology once.
Manufacture method as for the 9th embodiment is roughly described identical with the 7th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 56 with in the process of finishing gate insulator 58, needs suitably to control the etch depth of the first insulating barrier 58I and the second insulating barrier 58II, so that elongated area 58c 1, 58c 2Thickness T 1Reach a preferred values.
The tenth embodiment:
Tenth embodiment of the invention is to utilize a decrescendo phase transfer mask (attenuated phaseshifting mask) and collocation to carry out a photoetching process, shaded areas and elongated area with the definition gate insulator, then by the shaded areas of the asymmetric length of gate insulator as the cover curtain and the primary ions injection technology of arranging in pairs or groups, LDD structure and the pair of source territory that can finish two asymmetric length simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is the manufacture method that describes asymmetric LDD structure in detail.
See also Figure 13 A to Figure 13 E, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration tenth embodiment of the invention.
At first, as shown in FIG. 13A, deposition one resilient coating 72 in a substrate 70 is made an active layer 74 again on the presumptive area of resilient coating 72, deposit an insulating barrier 76, a conductive layer 80 and a photoresist layer 84 more in regular turn.The preferably of substrate 70 is a transparent insulation substrate or a substrate of glass, the preferably of resilient coating 72 is a dielectric materials layer or one silica layer, the preferably of active layer 74 is semiconductor silicon layer, a polysilicon layer or a low-temperature polycrystalline silicon layer, the preferably of insulating barrier 76 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 80 is a metal level or a polysilicon layer.
Shown in Figure 13 B, provide a decrescendo phase transfer (attenuated phase shifting) mask 87 so that photoresist layer 84 is carried out exposure imaging technology, so that photoresist layer 84 becomes the photoresist pattern 85 of a convex character shape.For example, mask 87 includes: a light tight regional 87a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; The regional 87b of one first phase transfer (phase-shifting) 1Be the left side that is positioned at light tight regional 87a, its position and size are with respect to predetermined first lightly doped region; One second phase transfer zone 87b 2Be the right side that is positioned at light tight regional 87a, its position and size are with respect to predetermined second lightly doped region; One first transmission region 87c 1Be to be positioned at first phase transfer zone 87b 1The left side, its position and size are with respect to predetermined first a heavy and light doped region; And one second transmission region 87c 2Be to be positioned at second phase transfer zone 87b 2The right side, its position and size are with respect to predetermined second heavily doped region.Generally speaking, phase transfer zone 87b 1, 87b 2And transmission region 87c 1, 87c 2Have different light transmittances, its light transmittance difference can be according to product and technology and is done suitable design.Thus, utilize 87 pairs one eurymeric photoresists of decrescendo mask material to carry out after the photoetching process, different light transmittances by each zone, can make each opposite position of photoresist layer 84 accept the exposure effect of varying strength, so that the etched degree of depth difference of each opposite position, the thickness of first area 85a of photoresist pattern 85 that just can make convex character shape is greater than second area 85b 1, 85b 2Thickness.Certainly, decrescendo mask 87 also can be applied to the negative photoresist material, as long as by each the regional position relation that changes on the decrescendo mask 87, just can form identical convex character shape profile on the negative photoresist material.
Thereafter, shown in Figure 13 C, the photoresist pattern 85 that utilizes convex character shape is removed conductive layer 80 beyond the photoresist pattern 85 and insulating barrier 76, and is kept a part of insulating barrier 76 to cover active layer 74 and resilient coating 72 as covering curtain to carry out one first etch process.Then, shown in Figure 13 D, carry out one second etch process, with 85 thinnings of photoresist pattern until removing second area 85b fully 1, 85b 2And the conductive layer 80 of below, then conductive layer 80 can be defined the pattern that becomes a grid layer 82, and can be with the pattern of insulating barrier 76 definition a becoming gate insulator 78.
Gate insulator 78 includes a middle section 78a, one first shaded areas 78b 1, one second shaded areas 78b 2, one first elongated area 78c 1And one second elongated area 78c 2Middle section 78a is covered by the bottom of grid layer 82, the first shaded areas 78b 1Be the bottom left that is positioned at the left side of middle section 78a and is exposed to grid layer 82, the second shaded areas 78b 2Be the right side, bottom that is positioned at the right side of middle section 78a and is exposed to grid layer 82, the first elongated area 78c 1Be to be positioned at the first shaded areas 78b 1The left side, the second elongated area 78c 2Be to be positioned at the second shaded areas 78b 2The right side.The first shaded areas 78b 1Lateral length W 1Be 0.1 μ m～2.0 μ m, the second shaded areas 78b 2Lateral length W 2Be 0.1 μ m～2.0 μ m, and W 1Be not equal to W 2The graphic demonstration W of second embodiment 1＜W 2Particularly, elongated area 78c 1, 78c 2Thickness T 1Less than shaded areas 78b 1, 78b 2Thickness T 2, also can make elongated area 78c 1, 78c 2Thickness T 1Near a minimum.The etch process preferably of this step is plasma etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, shown in Figure 13 E, after photoresist pattern 85 removed, carry out an ion implantation technology 86, utilize grid layer 82 with the shaded areas 78b of gate insulator 78 1, 78b 2As cover curtain, then can in active layer 74, form not doped region 74a, two lightly doped region 74b 1, 74b 2And two heavily doped region 74c 1, 74c 2Wherein, doped region 74a is not the corresponding below that is formed at middle section 78a, is to be used as a channel region; The first lightly doped region 74b 1Be the corresponding first shaded areas 78b that is formed at 1The below, the second lightly doped region 74b 2Be the corresponding second shaded areas 78b that is formed at 2The below, be to be used as a LDD structure; Heavily doped region 74c 1, 74c 2Being the two bottom sides that is exposed to gate insulator 78, is to be used as one source/drain diffusion region.Because the shaded areas 78b of gate insulator 78 1, 78b 2Be the cover curtain that is used as the LDD structure, so lightly doped region 74b 1, 74b 2Width be to correspond to shaded areas 78b 1, 78b 2Width W 1, W 2
The preferably is the first lightly doped region 74b 1Transverse width W 1Be 0.1～2.0 μ m, the second lightly doped region 74b 2Transverse width W 2Be 0.1～2.0 μ m, and W 1Be not equal to W 2The injection energy is 10～100keV, lightly doped region 74b 1, 74b 2Doping content be 1 * 10 12～1 * 10 14Atom/cm 2, heavily doped region 74c 1, 74c 2Doping content be 1 * 10 14～1 * 10 16Atom/cm 2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N -Doped region, and source/drain diffusion region is a N +Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P -Doped region, and source/drain region is a P +Doped region.
Follow-uply carry out interconnected technology, include inter-dielectric layer, contact hole and interconnected making, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.In addition, the method for the tenth embodiment also can be applicable to the technology of Fig. 9 and the described TFT assembly of Figure 12.

Claims (28)

1. thin-film transistor is characterized in that described thin-film transistor includes:
One substrate, it includes a first film transistor area and one second TFT regions;
One first active layer, be to be formed on this first film transistor area of this substrate, and include a channel region, two lightly doped regions and two heavily doped regions, wherein each lightly doped region is to be formed between this channel region and the heavily doped region;
One first grid insulating barrier, be to be formed on this first active layer, and include a middle section and two shaded areas, this middle section is the channel region that covers this first active layer, and each shaded areas is a lightly doped region that covers this first active layer;
One first grid layer is to be formed on this first grid insulating barrier, and covers the middle section of this first grid insulating barrier;
One second active layer, be to be formed on this second TFT regions of this substrate, and include a channel region, two lightly doped regions and two heavily doped regions, wherein each lightly doped region is to be formed between this channel region and the heavily doped region;
One second grid insulating barrier, be to be formed on this second active layer, and include a middle section and two shaded areas, this middle section is the channel region that covers this second active layer, and each shaded areas is a lightly doped region that covers this second active layer;
One second grid layer is to be formed on this second grid insulating barrier, and covers the middle section of this second grid insulating barrier;
Wherein, the lateral length of the shaded areas of this first grid insulating barrier is greater than the lateral length of the shaded areas of this second grid insulating barrier; And
Wherein, the lateral length of the lightly doped region of this first active layer is greater than the lateral length of the lightly doped region of this second active layer.
2. thin-film transistor according to claim 1 is characterized in that: this first film transistor area is as a pixel array region, and second TFT regions is as a peripheral drive circuit zone.
3. thin-film transistor according to claim 1 is characterized in that: this first grid insulating barrier is the heavily doped region that exposes this first active layer.
4. thin-film transistor according to claim 1, it is characterized in that: this first grid insulating barrier includes an elongated area in addition, this shaded areas is between this middle section and this elongated area, and this elongated area is the heavily doped region that covers this first active layer, and the thickness of this elongated area is less than the thickness of this shaded areas; And
This first grid insulating barrier is made of one first insulating barrier and one second insulating barrier, wherein the shaded areas of this first grid insulating barrier is to be formed by this first insulating barrier and this second insulating barrier institute storehouse, and the elongated area of this first grid insulating barrier is made of this first insulating barrier.
5. thin-film transistor according to claim 1 is characterized in that: this second grid insulating barrier is the heavily doped region that exposes this second active layer.
6. thin-film transistor according to claim 1, it is characterized in that: this second grid insulating barrier includes an elongated area in addition, this shaded areas is between this middle section and this elongated area, and this elongated area covers the heavily doped region of this second active layer, and the thickness of this elongated area is less than the thickness of this shaded areas; And
This second grid insulating barrier is made of one first insulating barrier and one second insulating barrier, wherein the shaded areas of this second grid insulating barrier is to be formed by this first insulating barrier and this second insulating barrier institute storehouse, and the elongated area of this second grid insulating barrier is made of this first insulating barrier.
7. thin-film transistor according to claim 1 is characterized in that: the doping content of the lightly doped region of this first, second active layer is 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of the heavily doped region of this first, second active layer is 1 * 10 14～1 * 10 16Atom/cm 2
8. thin-film transistor according to claim 1 is characterized in that: other includes a resilient coating, is to be formed between this substrate and this first active layer, and is formed between this substrate and this second active layer;
Wherein, this substrate is to be a transparent insulation substrate or a substrate of glass, this first, second active layer is to be a semiconductor silicon layer or a polysilicon layer, and this first, second gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
9. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided, and it includes a first film transistor area and one second TFT regions;
Form one first active layer on the first film transistor area of this substrate, and form one second active layer on second TFT regions of this substrate;
Form an insulating barrier in this substrate, to cover this first active layer and this second active layer;
Form a conductive layer on this insulating barrier;
Carry out an etch process, this conductive layer is defined as a first grid layer and a second grid layer, and this insulating barrier is defined as a first grid insulating barrier and a second grid insulating barrier;
Wherein, this first grid insulating barrier is to be formed on this first active layer, and includes a middle section and two shaded areas;
Wherein, this first grid layer is to be formed on this first grid insulating barrier, and covers the middle section of this first grid insulating barrier;
Wherein, this second grid insulating barrier is to be formed on this second active layer, and includes a middle section and two shaded areas;
Wherein, this second grid layer is to be formed on this second grid insulating barrier, and covers the middle section of this second grid insulating barrier;
Wherein, the lateral length of the shaded areas of this first grid insulating barrier is greater than the lateral length of the shaded areas of this second grid insulating barrier; And
Carry out an ion implantation technology, in this first active layer, form a channel region, two lightly doped regions and two heavily doped regions, and in this second active layer, form a channel region, two lightly doped regions and two heavily doped regions simultaneously;
Wherein, each lightly doped region of this first active layer is to be formed between this channel region and the heavily doped region, this channel region of this first active layer is covered by the middle section of this first grid insulating barrier, and each lightly doped region of this first active layer is covered by a shaded areas of this first grid insulating barrier;
Wherein, each lightly doped region of this second active layer is to be formed between this channel region and the heavily doped region, this channel region of this second active layer is covered by the middle section of this second grid insulating barrier, and each lightly doped region of this second active layer is covered by a shaded areas of this second grid insulating barrier; And
Wherein, the lateral length of the lightly doped region of this first active layer is greater than the lateral length of the lightly doped region of this second active layer.
10. the manufacture method of thin-film transistor according to claim 9, wherein:
This etch process is the heavily doped region that exposes this first active layer, and exposes the heavily doped region of this second active layer simultaneously.
11. the manufacture method of thin-film transistor according to claim 9, wherein: this etch process makes this first grid insulating barrier form an elongated area in addition, be the heavily doped region that is positioned at the peripheral of this shaded areas and covers this first active layer, and the thickness of this elongated area is less than the thickness of this shaded areas; And
The shaded areas of this first grid insulating barrier is made of one first insulating barrier and one second insulating barrier, and the elongated area of this first grid insulating barrier is made of this first insulating barrier.
12. the manufacture method of thin-film transistor according to claim 9, wherein:
This etch process makes this second grid insulating barrier form an elongated area in addition, be the heavily doped region that is positioned at the peripheral of this shaded areas and covers this second active layer, and the thickness of this elongated area is less than the thickness of this shaded areas; And
The shaded areas of this second grid insulating barrier is made of one first insulating barrier and one second insulating barrier, and the elongated area of this second grid insulating barrier is made of this first insulating barrier.
13. the manufacture method of thin-film transistor according to claim 9, wherein the doping content of the lightly doped region of this first, second active layer is 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of the heavily doped region of this first, second active layer is 1 * 10 14～1 * 10 16Atom/cm 2
14. the manufacture method of thin-film transistor according to claim 9, wherein:
Before forming this first, second active layer, be to form a resilient coating in this substrate;
This substrate is to be a transparent insulation substrate or a substrate of glass;
This active layer is to be a semiconductor silicon layer or a polysilicon layer; And
This gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
15. the manufacture method of thin-film transistor according to claim 9, wherein this etch process includes the following step:
First photoresist layer of one patterning is provided, covering the pre-defined gate area of the pattern of this first film transistor area, and covers whole this second TFT regions;
Carry out one first etching step, this conductive layer and this insulating barrier of this first film transistor area is defined as this first grid layer and this first grid insulating barrier;
Remove first photoresist layer of this patterning;
Second photoresist layer of one patterning is provided, covering the pre-defined gate area of the pattern of this second TFT regions, and covers whole this first film transistor area;
Carry out one second etching step, this conductive layer and this insulating barrier of this second TFT regions is defined as this second grid layer and this second grid insulating barrier; And
Remove second photoresist layer of this patterning.
16. the manufacture method of thin-film transistor according to claim 9, wherein this etch process includes the following step:
Provide a photoresist layer on this first film transistor area and this second TFT regions;
Utilize a decrescendo phase transfer mask to carry out exposure imaging technology, so that this photoresist layer forms one first convex character shape photoresist pattern and one second convex character shape photoresist pattern, the wherein pre-defined gate area of the pattern of this this first film transistor area of first convex character shape photoresist pattern covers, and this second convex character shape photoresist pattern is the pre-defined gate area of the pattern that covers this second TFT regions;
Utilize this first convex character shape photoresist pattern and this second convex character shape photoresist pattern as covering curtain to carry out etch process, this conductive layer and this insulating barrier of this first film transistor area this first grid layer and this first grid insulating barrier can be defined as, and this conductive layer and this insulating barrier of this second TFT regions this second grid layer and this second grid insulating barrier can be defined as; And
Remove this photoresist layer.
17. a thin-film transistor is characterized in that described thin-film transistor includes:
One substrate;
One active layer is to be formed in this substrate, and includes a channel region, a lightly doped region, one first heavily doped region and one second heavily doped region;
Wherein, this channel region and this lightly doped region are to be formed between this first heavily doped region and this second heavily doped region;
Wherein, this lightly doped region is to be formed between this channel region and this second heavily doped region;
One gate insulator, be to be formed to include a middle section and a shaded areas on this active layer and expose first of this active layer, second heavily doped region, perhaps also comprise an elongated area, this shaded areas is between this middle section and this elongated area, this elongated area covers first of this active layer, second heavily doped region, and the thickness of this elongated area is less than the thickness of this shaded areas, and this gate insulator is made of one first insulating barrier and one second insulating barrier, wherein the shaded areas of this gate insulator is to be formed by this first insulating barrier and this second insulating barrier institute storehouse, and the elongated area of this gate insulator is made of this first insulating barrier;
Wherein, this middle section is the channel region that covers this active layer;
Wherein, this shaded areas is the lightly doped region that covers this active layer; And
One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
18. thin-film transistor according to claim 17 is characterized in that: the doping content of the lightly doped region of this active layer is 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of first, second heavily doped region of this active layer is 1 * 10 14～1 * 10 16Atom/cm 2
19. thin-film transistor according to claim 17 is characterized in that: other includes a resilient coating and is formed between this substrate and this active layer, wherein:
This substrate is to be a transparent insulation substrate or a substrate of glass;
This active layer is to be a semiconductor silicon layer or a polysilicon layer; And
This gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
20. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided;
Form an active layer in this substrate;
Form an insulating barrier in this substrate, to cover this active layer;
Form a conductive layer on this insulating barrier;
Carry out an etch process, this conductive layer is defined as a grid layer, and this insulating barrier is defined as a gate insulator, expose first of this active layer, second heavily doped region, perhaps make this gate insulator form one first elongated area and one second elongated area in addition, this first elongated area is to be positioned at this middle section outside, and cover this first heavily doped region, this second elongated area is to be positioned at this shaded areas outside, and cover this second heavily doped region, and this is first years old, the thickness of second elongated area is less than the thickness of this shaded areas, and the shaded areas of this gate insulator is made of one first insulating barrier and one second insulating barrier, and this gate insulator first, second elongated area is made of this first insulating barrier;
Wherein, this gate insulator includes a middle section and a shaded areas; And
Wherein, this grid layer is the middle section that covers this gate insulator;
Carry out an ion implantation technology, in this active layer, form a channel region, a lightly doped region, one first heavily doped region and one second heavily doped region;
Wherein, this channel region and this lightly doped region are to be formed between this first heavily doped region and this second heavily doped region, and this lightly doped region is to be formed between this channel region and this second heavily doped region; And
Wherein, this channel region is covered by the middle section of this gate insulator, and this lightly doped region is covered by the shaded areas of this gate insulator.
The manufacture method of technology process 21. thin-film transistors according to claim 20, wherein the doping content of this lightly doped region is 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of this first, second heavily doped region is 1 * 10 14～1 * 10 16Atom/cm 2
22. the manufacture method of thin-film transistor according to claim 20, wherein:
Before forming this active layer, form a resilient coating in this substrate;
This substrate is to be a transparent insulation substrate or a substrate of glass;
This active layer is to be a semiconductor silicon layer or a polysilicon layer; And
This gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
23. a thin-film transistor is characterized in that described thin-film transistor includes:
One substrate;
One active layer is to be formed in this substrate, and includes a channel region, one first lightly doped region, one second lightly doped region, one first heavily doped region and one second heavily doped region;
Wherein, this channel region is to be formed between this first lightly doped region and this second lightly doped region;
Wherein, this first lightly doped region is to be formed between this channel region and this first heavily doped region;
Wherein, this second lightly doped region is to be formed between this channel region and this second heavily doped region; And
Wherein, the lateral length of this first lightly doped region is the lateral length greater than this second lightly doped region;
One gate insulator, be to be formed on this active layer, and include a middle section, one first shaded areas and one second shaded areas, be used to expose first of this active layer, second heavily doped region, perhaps this gate insulator also comprises one first elongated area and one second elongated area, this first shaded areas is between this middle section and this first elongated area, this second shaded areas is between this middle section and this second elongated area, this first elongated area covers first heavily doped region of this active layer, this second elongated area covers second heavily doped region of this active layer, and this first, the thickness of second elongated area less than this first, the thickness of second shaded areas; And this gate insulator is made of one first insulating barrier and one second insulating barrier, wherein first, second shaded areas of this gate insulator is to be formed by this first insulating barrier and this second insulating barrier institute storehouse, and first, second elongated area of this gate insulator is made of this first insulating barrier;
Wherein, this middle section is the channel region that covers this active layer;
Wherein, this first shaded areas is first lightly doped region that covers this active layer;
Wherein, this second shaded areas is second lightly doped region that covers this active layer;
Wherein, the lateral length of this first shaded areas is the lateral length greater than this second shaded areas; And
One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
24. thin-film transistor according to claim 23 is characterized in that: the doping content of first, second lightly doped region of this active layer is 1 * 10 12～1 * 10 14Atom/cm 2, the doping content of first, second heavily doped region of this active layer is 1 * 10 14～1 * 10 16Atom/cm 2
25. thin-film transistor according to claim 23 is characterized in that: other includes a resilient coating is to be formed between this substrate and this active layer;
Wherein this substrate is to be a transparent insulation substrate or a substrate of glass, and this active layer is to be a semiconductor silicon layer or a polysilicon layer, and this gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
26. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided;
Form an active layer in this substrate;
Form an insulating barrier in this substrate, to cover this active layer;
Form a conductive layer on this insulating barrier;
Carry out an etch process, this conductive layer is defined as a grid layer, and this insulating barrier is defined as a gate insulator, expose first of this active layer, second heavily doped region or make this gate insulator form one first elongated area and one second elongated area in addition, this first elongated area is to be positioned at this first shaded areas outside, and cover this first heavily doped region, this second elongated area is to be positioned at this second shaded areas outside and to cover this second heavily doped region, and this is first years old, the thickness of second elongated area less than this first, the thickness of second shaded areas, and this gate insulator first, second shaded areas is constituted first of this gate insulator by one first insulating barrier and one second insulating barrier, second elongated area is made of this first insulating barrier;
Wherein, this gate insulator includes a middle section, one first shaded areas and one second shaded areas;
Wherein, this middle section is between this first shaded areas and this second shaded areas;
Wherein, the lateral length of this first shaded areas is not equal to the lateral length of this second shaded areas; And
Wherein, this grid layer is the middle section that covers this gate insulator;
Carry out an ion implantation technology, in this active layer, form a channel region, one first lightly doped region, one second lightly doped region, one first heavily doped region and one second heavily doped region;
Wherein, this channel region is to be formed between this first lightly doped region and this second lightly doped region;
Wherein, this first lightly doped region is to be formed between this first heavily doped region and this channel region, and this second lightly doped region is to be formed between this second heavily doped region and this channel region; And
Wherein, this channel region is covered by the middle section of this gate insulator, and this first lightly doped region is covered by this first shaded areas, and this second lightly doped region is covered by this second shaded areas.
The manufacture method of technology process 27. thin-film transistors according to claim 26, wherein:
Before forming this active layer, form a resilient coating in this substrate;
This substrate is to be a transparent insulation substrate or a substrate of glass;
This active layer is to be a semiconductor silicon layer or a polysilicon layer; And
This gate insulator is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.
28. the manufacture method of thin-film transistor according to claim 26, wherein the manufacture method of this grid layer and this gate insulator comprises the following steps:
Provide a photoresist layer on this conductive layer;
One decrescendo phase transfer mask is provided, and it includes a zone of opacity, one first phase transfer zone, one second phase transfer zone, one first transparent region and one second transparent region;
Wherein, this zone of opacity is between this first phase transfer zone and this second phase transfer zone;
Wherein, this first phase transfer zone is between this first transparent region and zone of opacity;
Wherein, this second phase transfer zone is between this second transparent region and zone of opacity;
Carry out a photoetching process, with the photoresist pattern of this photoresist layer definition becoming convex character shape, it includes a first area and a second area;
Wherein the thickness of the first area of photoresist layer is greater than the thickness of the second area of this mask;
Wherein, the first area of this photoresist layer is the zone of opacity that corresponds to this mask;
Wherein, the second area of this photoresist layer is first, second phase transfer zone that corresponds to this mask;
Carry out one first etch process, conductive layer beyond this photoresist pattern and insulating barrier are removed;
Carry out one second etch process, with this photoresist pattern thinning, conductive layer until the second area of removing this photoresist layer fully and below thereof, then this conductive layer can be defined as the pattern of a grid layer, and this insulating barrier can be defined as the pattern of a gate insulator, wherein this grid layer is first, second shaded areas and first, second elongated area that exposes this gate insulator; And
Remove this photoresist pattern.
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