CN1388590A - Low temperature polysilicon thin film transistor with lightly doped drain structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a low-temperature polycrystalline silicon thin film transistor with a Lightly doped drain structure and a manufacturing method thereof. The invention uses the low-temperature polysilicon thin film transistor with the embedded lightly doped drain structure to replace the known low-temperature polysilicon thin film transistor with the surface type lightly doped drain structure. In the invention, when the ion doping procedure of the lightly doped drain is manufactured, ions are implanted in a first incidence direction and a second incidence direction respectively, and the manufacture of the embedded type lightly doped drain is further completed. The invention can effectively reduce the hot electron effect of the known low-temperature polycrystalline silicon thin film transistor, so that the stability of the low-temperature polycrystalline silicon thin film transistor during working can be obviously improved.

Description

Low temperature polysilicon thin film transistor with lightly doped drain structure and manufacturing method thereof

technical field

The invention relates to a low-temperature polysilicon thin-film transistor structure and a manufacturing method, in particular to a low-temperature polysilicon thin-film transistor with a lightly doped drain (Lightly doped drain, LDD for short) structure and a manufacturing method thereof.

Background technique

Generally speaking, a thin film transistor (Thin Film Transistor) is a basic circuit element used on a liquid crystal display (Liquid Crystal Display, LCD) to control the brightness of each pixel (Pixel). Therefore, thin film transistors must be formed on a glass substrate. However, since the glass substrate cannot withstand high temperature, the manufacturing process of the thin film transistor is different from the general transistor manufacturing process. Please refer to FIG. 1 , which illustrates the structure of a known thin film transistor. First, a gate conductor 105 is formed on the glass substrate 100 . Next, a gate insulating layer (Gate Insulator) 110 is covered on the glass substrate 100 and the gate conductor 105. Then, an amorphous silicon (Amorphous Si) layer 115 is formed on the gate insulating layer 110 as a channel (Channel) layer of the thin film transistor. Finally, heavily doped drain 120 and source 120 are formed on the intrinsically amorphous silicon 115 .

In the manufacturing process of the thin film transistor, since the glass substrate 100 cannot withstand high temperature, only the amorphous silicon layer 115 can be formed in a low temperature environment, and the polycrystalline silicon (Ploy Si) structure with better quality cannot be formed. Therefore, the electrical characteristics of such thin film transistors are poor.

With the advancement of technology, the polysilicon structure can be formed in a low-temperature environment using a laser annealing (Laser Annealing) manufacturing process. Therefore, the new thin film transistor manufacturing process can greatly improve the electrical characteristics of the thin film transistor and can be directly formed on the glass substrate. Please refer to FIG. 2 , which shows a schematic diagram of a standard low temperature polysilicon thin film transistor (Low temperature polysilicon, LTPS-TFT for short). In the figure, a polysilicon layer 200, an N-type heavily doped region (n+region) 205, a gate insulating layer (Gate insulator) 210, and a dielectric layer (Interlayer dielectric layer) 215 are included on a glass substrate (not shown). , gate conductor 220 , drain and source connection 225 . In such a low-temperature polysilicon thin film transistor structure, since the doping concentration of the two N-type heavily doped regions 205 is relatively high, and the distance between the two N-type heavily doped regions 205 and the gate conductor 220 is very small, the electric field near the drain 225 will be too large. Strong, resulting in a hot electron effect (hot electron effect), which seriously affects the stability of the component.

In order to solve the above-mentioned problems, it is the most common way in the industry today to improve the thermal electron effect by using a low-temperature polysilicon thin film transistor with a lightly doped drain structure. 3A-3E and 4A-4C are the low-temperature polysilicon thin-film transistors with lightly doped drain structures and their manufacturing processes. The structures described below are all formed on a glass substrate (not shown). In FIG. 3A, a polysilicon layer (Poly-Si) 300 is formed using a laser thermal annealing process, and an insulating layer (Gate Insulator) 310 is formed thereon, and a gate conductor 320 is formed on the insulating layer 310, and then used The gate conductor 320 implements the first ion doping procedure for a mask, and forms an N-type doped region (n region) 305 . Next, as shown in FIG. 3B , a dielectric layer 330 (dielectric layer) is covered on the insulating layer 310 and the gate conductor 320 . An etching process is then performed to form side wall spacer structures 335 on both sides of the gate conductor 320 as shown in FIG. 3C . At this time, the gate conductor 320 and the spacer 335 are used as a mask to implement the second ion doping procedure, so that a lightly doped drain region 340 (LDD) can be formed on the surface of the polysilicon layer 300, and the original N-type The doped region also becomes an N-type heavily doped region 305, and the lightly doped drain region 340 is between the two N-type heavily doped regions 305, and is close to the N-type heavily doped region, as shown in FIG. 3D Show. Finally, a dielectric layer 315 (interlayer dielectric layer) and source and drain connections 325 are sequentially formed to form a low-temperature polysilicon thin film transistor with a lightly doped drain structure as shown in FIG. 3E .

In FIG. 4A , firstly, the first ion doping process is performed on the polysilicon layer 400 using a photoresist (PR) 430 as a mask, and an N-type doped region 405 is implanted on the surface of the polysilicon layer 400 . Next, as shown in FIG. 4B, the photoresist 430 is removed, and an insulating layer 410 is sequentially formed on the polysilicon layer 400, and a gate conductor 420 is formed on the insulating layer 410 at the same position of the photoresist, Wherein, the area occupied by the gate conductor 420 must be smaller than the area covered by the previous photoresist 430, and then implement the second ion doping procedure, so the lightly doped drain 440 will be on the polysilicon layer 400, and the original N-type doped region becomes N-type heavily doped region 405. Finally, the dielectric layer 415 and the source and drain connections 425 are sequentially formed to form a low temperature polysilicon thin film transistor with a lightly doped drain structure as shown in FIG. 4C .

The low-temperature polysilicon thin film transistors with two lightly doped drain structures shown in FIG. 3E and FIG. 4C both form the lightly doped drain on the surface of polysilicon, which is a surface lightly doped drain structure (Surface LDDStructure). , the doping method can be ion implantation (Ion implantation) or ion implantation (ionshower), and the doped substance is P, As ions or PH _x , AsH _x ions. This structure is called gate-drain overlapped LDD ( Gate-Drain Overlapped LDD (referred to as GO-LD), in which ion implantation controls the distribution of valence electrons of ions to be doped more strictly, while ion implantation controls the distribution of valence electrons of ions to be doped more loosely. . Because in the drain doped region, in addition to the N-type heavily doped region, there is also a lightly doped drain on the surface close to the gate, so that the electric field strength near the drain can be reduced, and thus Reduces the influence of thermionic effects. However, in such a structure, the electric field strength near the drain is still too large, which will affect the movement of electrons on the channel. When electrons flow through the channel near the drain, the electric field near the drain is too strong. , so that the electron energy is too high, which will cause two effects: first, the energy released by the electrons breaks the silicon-hydrogen bond at the interface between the gate insulating layer and the polysilicon, resulting in an increase in the surface energy level (surface state), making the sub-threshold (sub -threshold swing) changes; 2. Electrons are scattered into the gate insulating layer to form an oxide trap state, which changes the threshold voltage and causes the device to work abnormally.

Due to the increasingly high quality requirements for low-temperature polysilicon liquid crystal displays, the corresponding display size and resolution requirements are also increasing. In addition, more and more circuits need to be integrated in the display. Shift registers (shift register) to level shifter (level shifter), digital-to-analog converter (referred to as DAC) to dynamic random access memory (referred to as DRAM), and even the operational amplifier (referred to as OP) will be integrated into the circuit in the future In this way, the channel length of the thin film transistor will become smaller and smaller, and the electric field strength on the channel will be relatively stronger, and the above two effects will have more and more serious impact on the transistor. If Only using the low-temperature polysilicon thin-film transistors with two surface-type lightly doped drain structures shown in FIG. 3E and FIG. 4C will not be able to improve the influence of the above two effects on the transistor, nor will it be able to meet future demands.

Contents of the invention

In view of the above-mentioned background of the invention, the traditional low-temperature polysilicon thin-film transistor with a surface-type lightly doped drain structure cannot effectively improve the stability of the device itself. Therefore, the present invention provides a low-temperature polysilicon thin-film transistor with a buried lightly doped drain structure and a manufacturing method thereof in response to the above-mentioned needs.

The purpose of the present invention is achieved in this way: a thin film transistor structure with a buried lightly doped drain structure applied to a liquid crystal display, comprising: a semiconductor layer; an insulating layer covering a surface of the semiconductor layer ; A first heavily doped region and a second heavily doped region, located on the surface in the semiconductor layer and separated by a first length; a first lightly doped drain region and a second lightly doped drain An electrode region is located inside the semiconductor layer and has a distance from the surface, and the first lightly doped drain is adjacent to the first heavily doped region, and the second lightly doped drain is adjacent to the second heavily doped drain The doped regions are adjacent, and a channel is formed between the first lightly doped drain region and the second lightly doped drain region, and the channel has a second length, wherein the first length is greater than the first two lengths; and a gate conductor located on the insulating layer and covering the region corresponding to the channel.

According to the above idea, the thin film transistor structure with buried lightly doped drain structure of the present invention further includes: a dielectric layer covering the gate conductor and the insulating layer; and a drain connection and a source connection, The insulating layer and the dielectric layer are respectively in contact with the first heavily doped region and the second heavily doped region.

According to the above idea, the present invention has a thin film transistor structure with a buried lightly doped drain structure, wherein the semiconductor layer is a polysilicon layer.

According to the above idea, the present invention has a thin film transistor structure with a buried lightly doped drain structure, wherein the first heavily doped region and the second heavily doped region are respectively a first N-type heavily doped region and a second N-type heavily doped region.

According to the above idea, the present invention has a buried lightly doped drain structure thin film transistor structure, wherein the first lightly doped drain region, the second lightly doped drain region, the first heavily doped drain region, and the first heavily doped drain region are formed. region and the second heavily doped region are formed using an ion doping process.

According to the above idea, the present invention has a thin film transistor structure with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, a PH _x ion and An ion selected from an AsH _x ion.

According to the above idea, the present invention has a thin film transistor structure with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, a PH _x ion and At least one ion selected from an AsH _x ion.

According to the above idea, the present invention has a buried lightly doped drain structure thin film transistor structure, wherein both the first lightly doped drain region and the second lightly doped drain region have a density distribution in a gradient January halo structure.

On the other hand, the object of the present invention is achieved in this way: a method for manufacturing a thin film transistor with a buried lightly doped drain structure applied to a liquid crystal display, comprising the following steps: providing a semiconductor structure, wherein , the semiconductor structure has a semiconductor layer, an insulating layer covering a surface of the semiconductor layer, and a gate conductor is provided on the insulating layer; a first ion doping procedure is performed, wherein a A first incident direction of the surface is used to dope at least one ion on the surface in the semiconductor layer; a second ion doping procedure is performed, wherein the at least one ion is doped in a second incident direction The interior of the semiconductor layer is separated from the surface by a first distance; and a third ion doping process is performed, wherein the at least one ion is doped in the interior of the semiconductor layer with a third incident direction and is in contact with the surface. The surfaces are separated by a second distance.

According to the above idea, the present invention provides a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the semiconductor layer is a polysilicon layer, and the gate conductor has a sidewall structure around it.

According to the above idea, the present invention has a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, a PH _x ions and an ion selected from an AsH _x ion.

According to the above idea, the present invention has a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, and a PH _x ion and at least one ion selected from an AsH _x ion.

According to the above idea, the present invention provides a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the second incident direction and the third incident direction are located on two sides of the first incident direction.

According to the above idea, the method for manufacturing a thin film transistor with a buried lightly doped drain structure of the present invention, wherein the angle formed by the second incident direction and the first incident direction is greater than 0 degrees to 30 degrees .

According to the above idea, the method for manufacturing a thin film transistor with a buried lightly doped drain structure of the present invention, wherein the angle formed by the third incident direction and the first incident direction is greater than 0 degrees to 30 degrees .

In another aspect, the purpose of the present invention can also be achieved in the following way: a method for manufacturing a thin film transistor with a buried lightly doped drain structure applied to a liquid crystal display, comprising the following steps: providing a semiconductor layer; forming A mask covering part of a surface of the semiconductor layer; performing a first ion doping process, wherein at least one ion is doped into the semiconductor layer with a first incident direction perpendicular to the surface the surface; removing the mask; forming an insulating layer on the surface; forming a gate conductor on the surface of the insulating layer; performing a second ion doping process, wherein a second incident direction is used to The at least one ion is doped inside the semiconductor layer with a first distance from the surface; and a third ion doping process is performed, wherein the at least one ion is doped with a third incident direction There is a second distance between the inside of the semiconductor layer and the surface.

According to the above idea, the present invention provides a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the semiconductor layer is a polysilicon layer.

According to the above idea, the present invention has a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, a PH _x ions and an ion selected from an AsH _x ion.

According to the above idea, the present invention has a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the ion doping procedure is an ion implantation procedure, and consists of a P ion, an As ion, and a PH _x ion and at least one ion selected from an AsH _x ion.

According to the above idea, the present invention provides a method for manufacturing a thin film transistor with a buried lightly doped drain structure, wherein the second incident direction and the third incident direction are located on two sides of the first incident direction.

According to the above idea, the method for manufacturing a thin film transistor with a buried lightly doped drain structure of the present invention, wherein the angle formed by the second incident direction and the first incident direction is greater than 0 degrees to 30 degrees .

According to the above idea, the method for manufacturing a thin film transistor with a buried lightly doped drain structure of the present invention, wherein the angle formed by the third incident direction and the first incident direction is greater than 0 degrees to 30 degrees .

Below, the present invention will be described in further detail in combination with specific embodiments and accompanying drawings.

Description of drawings

1 is a cross-sectional view of a known thin film transistor;

2 is a cross-sectional view of another known thin film transistor;

3A to 3E are flow charts of manufacturing process steps of low-temperature polysilicon thin-film transistors with surface-type lightly doped drain structures;

4A to 4C are flow charts of manufacturing process steps of another known surface-type lightly doped drain structure low-temperature polysilicon thin film transistor;

5A to 5D are flowcharts of manufacturing process steps of a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure according to the first embodiment of the present invention;

6 is a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure according to the second embodiment of the present invention;

7A to 7D are flowcharts of manufacturing process steps of a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure according to the third embodiment of the present invention;

FIG. 8 is a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure according to the fourth embodiment of the present invention;

FIG. 9 is a trajectory diagram of electrons moving on the channel of the low-temperature polysilicon thin film transistor with buried lightly doped drain structure of the present invention.

Detailed ways

In the known low-temperature polysilicon thin-film transistor element, because of its planar lightly doped drain structure, the low-temperature polysilicon thin-film transistor will be relatively unstable during operation. Therefore, the present invention proposes a new manufacturing method and The structure can solve the disadvantages of known low temperature polysilicon thin film transistors.

As shown in FIGS. 5A-5D , they are flow charts of manufacturing process steps of the low-temperature polysilicon thin film transistor with embedded lightly doped drain structure according to the first embodiment of the present invention. The structures described below are all formed on a glass substrate (not shown). As shown in FIG. 5A, a polysilicon layer (Poly-Si) 500 is formed by using a laser thermal annealing process, and a gate insulating layer (Gate Insulator) 510 is formed on it, and then a gate insulating layer (Gate Insulator) 510 is formed sequentially on the gate insulating layer 510. The gate conductor 520 and the spacers 535 on both sides thereof, and then use the gate conductor 520 and the spacers 535 on both sides thereof as a mask to implement the first ion doping procedure, and form an N-type doped region (n Region) 505. Next, as shown in FIG. 5B , using the gate conductor 520 and the spacer 535 as a mask, a second ion doping process is performed to form the first lightly doped drain 542 . It can be seen from FIG. 5B that the second ion doping procedure is performed by doping the doped ions into the polysilicon layer 500 in a first incident direction. Therefore, the first lightly doped drain 542 is formed in the polysilicon layer 500 as a buried lightly doped drain structure not in contact with the surface. According to this embodiment, the first incident direction and the normal line of the insulating layer 510 form an included angle greater than 0 degrees and less than about 30 degrees. Next, as shown in FIG. 5C , again using the gate conductor 520 and the spacer structure 535 as a mask, a third ion doping process is performed to form a second lightly doped drain 544 . It can be seen from FIG. 5C that the third ion doping procedure is to dope the doped ions into the polysilicon layer 500 in the second incident direction. Therefore, the second lightly doped drain 544 is formed in the polysilicon layer 500 as a buried lightly doped drain structure that is not in contact with the surface. According to this embodiment, the second incident direction and the first incident direction are located on two sides of the normal line of the insulating layer 510 , and the second incident direction and the normal line of the insulating layer 510 form an included angle greater than 0 degrees and less than about 30 degrees. After this step, the original N-type doped region also becomes an N-type heavily doped region 505, and the first lightly doped drain region 542 and the second doped drain 544 are located between the two N-type heavily doped regions 505 between, and close to the N-type heavily doped region 505. Wherein, the distance between the two N-type heavily doped regions 505 is greater than the distance between the two lightly doped drain regions 542, 544, and the first lightly doped drain region 542 and the second lightly doped drain region 544 to form a channel. As shown in Figure 5C. Since the incident direction of ions is controlled during implantation, the lightly doped drains 542, 544 will not be formed at the interface between the insulating layer 510 and the polysilicon layer 500, but will be formed under the interface between the insulating layer 510 and the polysilicon layer 500. , some distance away from this interface. Finally, as shown in FIG. 5D , an interlayer dielectric layer (Interlayer Dielectric Layer) 515 and source and drain connections 525 are sequentially formed.

In the manufacturing process steps in the above embodiments, more than two kinds of doping materials, such as PH ₃ and AsH ₃ , can be used simultaneously in the ion doping procedures in FIG. 5B and FIG. 5C . Please refer to FIG. 6 , which is a low temperature polysilicon thin film transistor with a buried lightly doped drain structure according to a second embodiment of the present invention. Due to the difference in the mass of P and As ions, at the same incident energy, the lightly doped drains 642, 644 will automatically form the lightly doped drains 642, 644 halo structure as shown in Figure 6, so that the lightly doped The concentration of the drain electrodes 642, 644 has a gradient effect.

As shown in FIGS. 7A to 7D , they are flowcharts of manufacturing process steps of a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure according to the third embodiment of the present invention. As shown in FIG. 7A , firstly, the first ion doping procedure is performed using the photoresist 730 as a mask, and an N-type doped region (nRegion) 705 is implanted on the polysilicon layer 700 . Next, as shown in FIG. 7B , the photoresist 730 is removed, and an insulating layer 710 is sequentially formed on the polysilicon layer, and a gate conductor 720 is formed on the insulating layer 710 at the same position of the photoresist. Next, using the gate conductor 720 as a mask, a second ion doping process is performed to form a first lightly doped drain 742 . It can be seen from FIG. 7B that the second ion doping process is performed by doping the doped ions into the polysilicon layer 700 in a first insertion direction. Therefore, the first lightly doped drain 742 is formed in the polysilicon layer 700 as a buried lightly doped drain structure that is not in contact with the surface. According to this embodiment, the first incident direction and the normal line of the insulating layer 710 form an included angle greater than 0 degrees and less than about 30 degrees. Next, as shown in FIG. 7C , again using the gate conductor 720 as a mask, a third ion doping process is performed to form a second lightly doped drain 744 . It can be seen from FIG. 7C that the third ion doping procedure is to dope the doped ions into the polysilicon layer 700 in the second incident direction. Therefore, the second lightly doped drain 744 is formed in the polysilicon layer 700 as a buried lightly doped drain structure that is not in contact with the surface. According to this embodiment, the second incident direction and the first incident direction are located on two sides of the normal line of the insulating layer 710 , and the second incident direction and the normal line of the insulating layer 710 form an included angle greater than 0 degrees and less than about 30 degrees. After this step, the original N-type doped region also becomes N-type heavily doped region 705, and the first lightly doped drain region 742 and the second doped drain 744 are between the two N-type heavily doped regions 705 Between and close to the N-type heavily doped region 705 . Wherein, the distance between the two N-type heavily doped regions 705 is greater than the distance between the two lightly doped drain regions 742, 744, and the first lightly doped drain region 742 and the second lightly doped drain region 744 to form a channel. As shown in Figure 7C. Since the incident direction of ions is controlled during implantation, the lightly doped drains 742 and 744 will not be formed at the interface between the insulating layer 710 and the polysilicon layer 700, but will be formed under the interface between the insulating layer 710 and the polysilicon layer 700. There is a distance from this interface. Finally, as shown in FIG. 7D , a dielectric layer (Interlayer Dielectric Layer) 715 and source and drain connections (Source and Drain Metal) 725 are formed in sequence.

In the manufacturing process steps in the above embodiments, more than two kinds of doping materials, such as PH ₃ and AsH ₃ , can be used simultaneously in the ion doping procedures in FIG. 7B and FIG. 7C . Please refer to FIG. 8 , which is a low temperature polysilicon thin film transistor with a buried lightly doped drain structure according to a fourth embodiment of the present invention. Due to the difference in the mass of P and As ions, at the same incident energy, the lightly doped drains 842, 844 will automatically form the lightly doped drains 842, 844 halo structure as shown in Figure 8, so that the lightly doped The concentration of the drain electrodes 842, 844 has a gradient effect.

And these four embodiments will eventually form a structure similar to that shown in Figure 9, because during the implantation, ion doping with different incident angles is performed on both sides of the vertical angle respectively, and higher energy is used, so that The lightly doped drains 942 and 944 are far away from the interface between the polysilicon layer 900 and the gate insulating layer 910, and the doping method can be ion implantation or ion shower, and the doped material is P , As ions or PH _x , AsH _x ions, or two kinds of fabric materials can be used for lightly doped drain implantation. The biggest feature of the structure shown in Figure 9 is that the positions of the lightly doped drains 942 and 944 will not be formed at the interface between the insulating layer 910 and the polysilicon layer 900, but will be formed under the interface, a certain distance from the interface. The distance becomes a low-temperature polysilicon thin film transistor with a buried lightly doped drain structure (Buried-LDD). As shown in the figure, when the electrons are close to the drain, the path the electrons move will be away from the interface between the polysilicon layer 900 and the insulating layer 910, so hot electrons are not easy to enter the interface and break the silicon-hydrogen bond to cause a sub-threshold (sub- threshold swing), it is not easy to scatter to the insulating layer 910 to cause instability of the threshold voltage (Threshold Voltage). Therefore, this invention will greatly improve the stability of low-temperature polysilicon thin film transistors and meet the requirements of future products.

The gate conductor (with a thickness of about 200 nm) in the above-mentioned preferred embodiments can be formed by sputtering, and it can be formed by one of materials selected from chromium, tungsten molybdenum, tantalum, aluminum or copper. Among them, the amorphous silicon layer (about 100nm in thickness) needs to be annealed and dehydrogenated in a high-temperature furnace at 400 degrees for 30 minutes before using the laser annealing crystallization process to form polysilicon, and the energy of the laser crystallization process must be 300mJ/cm ² 100 shots were performed under the following conditions. As for the gate insulating layer (thickness about 100nm), it is formed by plasma chemical vapor deposition (PECVD), which is usually completed by silicon oxide. Therefore, the present invention can be modified variously by those skilled in the art without departing from the scope of protection expected by the claims. The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. All other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the claims within the scope of protection.

Claims (10)

1. A thin film transistor structure with a buried lightly doped drain structure applied to a liquid crystal display, characterized in that it includes: a semiconductor layer; an insulating layer covering a surface of the semiconductor layer; A first heavily doped region and a second heavily doped region are located on the surface in the semiconductor layer and are separated by a first length; A first lightly doped drain region and a second lightly doped drain region are located inside the semiconductor layer and have a distance from the surface, and the first lightly doped drain and the first heavily doped drain regions are adjacent, the second lightly doped drain is adjacent to the second heavily doped region, and a channel is formed between the first lightly doped drain region and the second lightly doped drain region, and the channel has a second length, wherein the first length is greater than the second length; and A gate conductor is located on the insulating layer and covers the region corresponding to the channel. 2. The thin film transistor structure with buried lightly doped drain structure according to claim 1, further comprising: a dielectric layer covering the gate conductor and the insulating layer; and A drain connection and a source connection pass through the insulating layer and the dielectric layer and are respectively in contact with the first heavily doped region and the second heavily doped region. 3. The thin film transistor structure with a buried lightly doped drain structure according to claim 1, wherein the semiconductor layer is a polysilicon layer, the first heavily doped region and the second heavily doped region The regions are respectively a first N-type heavily doped region and a second N-type heavily doped region. 4. The thin film transistor structure with a buried lightly doped drain structure according to claim 1, wherein the first lightly doped drain region and the second lightly doped drain region both have a concentration of Gradient distribution of the halo structure. 5. A method for manufacturing a thin film transistor with a buried lightly doped drain structure applied to a liquid crystal display, comprising the following steps: A semiconductor structure is provided, wherein the semiconductor structure has a semiconductor layer, an insulating layer covering a surface of the semiconductor layer, and a gate conductor is provided on the insulating layer; performing a first ion doping process, wherein at least one ion is doped to the surface in the semiconductor layer with a first incident direction perpendicular to the surface; performing a second ion doping procedure, wherein the at least one ion is doped inside the semiconductor layer with a first distance from the surface with a second incident direction; and A third ion doping procedure is performed, wherein the at least one ion is doped inside the semiconductor layer with a second distance from the surface with a third incident direction. 6 . The method for manufacturing a thin film transistor with a buried lightly doped drain structure as claimed in claim 5 , wherein the semiconductor layer is a polysilicon layer, and there is a sidewall structure around the gate conductor. 7. The method for manufacturing a thin film transistor with a buried lightly doped drain structure as claimed in claim 5, wherein the second incident direction and the third incident direction are located on two sides of the first incident direction , the angle formed by the second incident direction and the first incident direction is greater than 0 degrees to 30 degrees, and the angle formed by the third incident direction and the first incident direction is greater than 0 degrees to 30 degrees between degrees. 8. A method for manufacturing a thin film transistor with a buried lightly doped drain structure applied to a liquid crystal display, characterized in that it comprises the following steps: providing a semiconductor layer; forming a mask covering part of a surface of the semiconductor layer; performing a first ion doping process, wherein at least one ion is doped to the surface in the semiconductor layer with a first incident direction perpendicular to the surface; remove the veil; forming an insulating layer on the surface; forming a gate conductor on the surface of the insulating layer; performing a second ion doping procedure, wherein the at least one ion is doped inside the semiconductor layer with a first distance from the surface with a second incident direction; and A third ion doping procedure is performed, wherein the at least one ion is doped inside the semiconductor layer with a second distance from the surface with a third incident direction. 9. The method for manufacturing a thin film transistor with a buried lightly doped drain structure as claimed in claim 8, wherein the semiconductor layer is a polysilicon layer. 10. The method for manufacturing a thin film transistor with a buried lightly doped drain structure according to claim 8, wherein the second incident direction and the third incident direction are located on two sides of the first incident direction , the angle formed by the second incident direction and the first incident direction is greater than 0 degrees to 30 degrees, and the angle formed by the third incident direction and the first incident direction is greater than 0 degrees to 30 degrees between degrees.

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