CN1388590A - Low-temperature polysilicon film transistor with slightly doped drain structure and its making process - Google Patents
Low-temperature polysilicon film transistor with slightly doped drain structure and its making process Download PDFInfo
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- CN1388590A CN1388590A CN 02123086 CN02123086A CN1388590A CN 1388590 A CN1388590 A CN 1388590A CN 02123086 CN02123086 CN 02123086 CN 02123086 A CN02123086 A CN 02123086A CN 1388590 A CN1388590 A CN 1388590A
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Abstract
The present invention is low-temperature polysilicon film transistor with lightly doped drain structure and its making process. The present invention has one embedded, rather than convertional surface, lightly doped drain structure in the transistor. During the ion doping to make the lightly doped drain, ions are implanted in one first incident direction and one second incident direction. The present invention can reduce the hot electron effect in low-temperature polysilicon film transistor effectively and raise the stability of low-temperature polysilicon film transistor obviously.
Description
Technical field
The present invention relates to a kind of low-temperature polycrystalline silicon thin film transistor structure and manufacture method, particularly relate to low-temperature polysilicon film transistor of a kind of lightly doped drain (Lightly doped drain is called for short LDD) structure and preparation method thereof.
Background technology
In general, thin-film transistor (Thin Film Transistor) be applied in LCD (Liquid Crystal Display, LCD) on, be used for controlling the basic circuit elements of each pixel (Pixel) brightness.Therefore, thin-film transistor must be formed on the glass substrate.But because glass substrate can not be high temperature resistant, so the thin-film transistor manufacture craft can be different from general transistor fabrication technology.Please refer to Fig. 1, it has illustrated the structure of known thin-film transistor.At first, on glass substrate 100, form a grid conductor 105.Then, gate insulator (Gate Insulator) 110 is covered on glass substrate 100 and the grid conductor 105.Then, amorphous silicon (Amorphous Si) layer 115 is formed on the gate insulator 110 raceway groove (Channel) layer as thin-film transistor.At last, heavily doped drain electrode 120 is formed on the essential amorphous silicon 115 with source electrode 120.
In the manufacture craft of this thin-film transistor, because glass substrate 100 can not be high temperature resistant, therefore in the environment of low temperature, only can form amorphous silicon layer 115, can not form the preferable polysilicon of quality (Ploy Si) structure.So the opering characteristic of electric apparatus of this type of thin-film transistor is relatively poor.
Along with the progress of science and technology, polysilicon structure can utilize LASER HEAT annealing (Laser Annealing) manufacture craft to form under low temperature environment.Therefore, the manufacture craft of new thin-film transistor can be improved the opering characteristic of electric apparatus of thin-film transistor greatly and be formed directly on the glass substrate.Please refer to Fig. 2, it has illustrated standard cryogenic polycrystalline SiTFT (Low temperature poly silicon is called for short LTPS-TFT) schematic diagram.Among the figure, a polysilicon layer 200, N type heavily doped region (n+region) 205, gate insulator (Gate insulator) 210, dielectric layer (Interlayer dielectric layer) 215, grid conductor 220, drain electrode and source connection 225 on glass substrate (not illustrating), have been comprised.In such low-temperature polycrystalline silicon thin film transistor structure, because the doping content of two N type heavily doped regions 205 is higher, and and the spacing between the grid conductor 220 is very little, near so can cause draining 225 electric field is too strong, thereby produce thermoelectronic effect (hot electron effect), make element stability be seriously influenced.
In order to address the above problem, utilizing the low-temperature polysilicon film transistor of ldd structure to improve thermoelectronic effect is the most general mode of industry now.The low-temperature polysilicon film transistor of ldd structure and manufacture craft flow chart are shown in Fig. 3 A～Fig. 3 E and Fig. 4 A～Fig. 4 C at present, and the structure of the following stated all is formed on the glass substrate (not illustrating).In Fig. 3 A, utilize LASER HEAT annealing manufacture craft to form polysilicon layer (Poly-Si) 300, and form an insulating barrier (Gate Insu lator) 310 thereon, and on insulating barrier 310, form grid conductor 320, utilize grid conductor 320 to implement the program of ion doping for the first time afterwards, and form N type doped region (n region) 305 for cover curtain (Mask).Then, shown in Fig. 3 B, on insulating barrier 310 and grid conductor 320, cover a dielectric layer 330 (dielectric layer).Then carry out clearance wall (the Side Wallor Spacer) structure 335 of etch process formation grid conductor 320 both sides shown in Fig. 3 C.At this moment, utilize grid conductor 320 and clearance wall 335 to be the cover curtain again, implement the program of ion doping for the second time, can form lightly mixed drain area 340 (LDD) in polysilicon layer 300 surfaces, and former N type doped region also becomes N type heavily doped region 305, and lightly mixed drain area 340 is between between two N type heavily doped regions 305, and is close to N type heavily doped region, shown in Fig. 3 D.At last, form dielectric layer 315 (interlayer dielectric layer) and source electrode, drain connection 325 more in regular turn, can form the low-temperature polysilicon film transistor of the ldd structure shown in Fig. 3 E.
And in Fig. 4 A, at first, utilize photoresistance (PR) 430 to carry out the program of ion doping for the first time for the cover curtain on polysilicon layer 400, and cloth is planted N type doped region 405 in polysilicon layer 400 surfaces.Then, shown in Fig. 4 B, photoresistance 430 is removed, and on polysilicon layer 400, form an insulating barrier 410 in regular turn, and on insulating barrier 410, form a grid conductor 420 in the same position place of photoresistance, wherein, the area that grid conductor 420 shared areas must be covered than photoresistance 430 before is little, afterwards, implement the program of ion doping for the second time again, therefore, lightly doped drain 440 will form in polysilicon layer 400 surfaces, and former N type doped region also becomes N type heavily doped region 405.At last, form dielectric layer 415 and source electrode, drain connection 425 more in regular turn, can form the low-temperature polysilicon film transistor of the ldd structure shown in Fig. 4 C.
Low-temperature polysilicon film transistor at two kinds of ldd structures shown in Fig. 3 E and Fig. 4 C, all lightly doped drain is formed at polysilicon surface, this is surface-type ldd structure (Surface LDDStructure), doping way can be implanting ions (Ion implantation) or ion injects (ionshower), and the material of its doping is P, As ion or PH
x, AsH
xIon, this structure is called grid drain electrode overlapping LDD (Gate-Drain Overlapped LDD abbreviates GO-LD as), wherein, implanting ions is tighter for the valence electron distribution control of the ion that mixes, and ion injects then loose for the valence electron distribution control of the ion that mixes.Because in drain doping region, except N type heavily doped region, near more than the surface of grid a lightly doped drain, thus, can reduce near the electric field strength its drain electrode, and and then reduce the influence of thermoelectronic effect.Yet, in such structure, it is too big that near the drain electrode electric field strength is still disliked slightly, will have influence on the situation that electronics moves on raceway groove, when electron stream is near the close drain electrode of raceway groove, because near the electric field of drain electrode is too strong, make electron energy too high, will cause two effects: one, the energy that disengages of electronics interrupts the si-h bond at gate insulator and polysilicon interface, causes surface energy rank (surface state) to increase, and makes subthreshold (sub-threshold swing) change; Two, electronics is scattered into gate insulator, forms oxide layer capturing state (oxide trap state), makes threshold voltage (threshold voltage) change, and causes element work undesired.
Because the quality requirements to the low temperature polycrystalline silicon LCD is more and more higher now, relative required display sizes and resolution also require more and more higher, in addition, the circuit that needs to integrate in display also gets more and more, shift register (shift register) is to level displacement shifter (level shifter), digital analog converter (abbreviating DAC as) is to dynamic random access memory (abbreviating DRAM as), even will be integrated into operational amplifier (abbreviating OP as) in the circuit future, thus, to make that the channel length of thin-film transistor is more and more littler, relative also more and more stronger of electric field strength on the raceway groove, and two above-mentioned effects also can be more and more serious to transistorized influence, if only utilize the low-temperature polysilicon film transistor of two kinds of surface-type ldd structures among Fig. 3 E and Fig. 4 C, can't improve above-mentioned two effects to the influence that transistor caused, also can't satisfy following demand.
Summary of the invention
In above-mentioned background of invention, the low-temperature polysilicon film transistor of conventional surface formula ldd structure can't effectively improve the problem of element stability itself.Therefore, the present invention is directed to the demand, a kind of low-temperature polysilicon film transistor and manufacture method thereof of flush type ldd structure is provided.
The object of the present invention is achieved like this: a kind of thin-film transistor structure that is applied to the tool flush type ldd structure on the LCD comprises: semi-conductor layer; One insulating barrier is covered in a surface of this semiconductor layer; One first heavily doped region and one second heavily doped region are positioned on this surface of this semiconductor layer and at a distance of one first length; One first lightly mixed drain area and one second lightly mixed drain area, be positioned at this semiconductor layer inner and and this surface between have a spacing, and this first lightly doped drain is adjacent with this first heavily doped region, this second lightly doped drain is adjacent with this second heavily doped region, and formation one raceway groove between this first lightly mixed drain area and this second lightly mixed drain area, and this raceway groove has one second length, and wherein this first length is greater than this second length; And a grid conductor, be positioned on this insulating barrier, and be covered in this raceway groove The corresponding area.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention further comprises: a dielectric layer is covered on this grid conductor and this insulating barrier; And a drain connection and an one source pole wiring, run through insulating barrier and contact with this second heavily doped region with this first heavily doped region respectively with this dielectric layer.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, this semiconductor layer is a polysilicon layer.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, this first heavily doped region and this second heavily doped region are respectively one the one N type heavily doped region and one the 2nd N type heavily doped region.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, forming this first lightly mixed drain area, this second lightly mixed drain area, this first heavily doped region and this second heavily doped region is to utilize an ion doping program to form.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, this ion doping program is an implanting ions program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xThe middle ion of selecting of ion forms.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, this ion doping program is this ion injecting program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xSelected at least one ion forms in the ion.
According to above-mentioned conception, the thin-film transistor structure of tool flush type ldd structure of the present invention, wherein, this first lightly mixed drain area and this second lightly mixed drain area all have concentration and are the gradually dizzy structure in January of layer distribution.
On the other hand, the object of the present invention is achieved like this: a kind of manufacture method that is applied to the thin-film transistor of the tool flush type ldd structure on the LCD, it comprises the following steps: to provide semiconductor structure, wherein, this semiconductor structure has semi-conductor layer, be covered in an insulating barrier on a surface of this semiconductor layer, and have a grid conductor on this insulating barrier; Carry out one first ion doping program, wherein, be with one perpendicular to one first incident direction on this surface with at least one ion doping this surface in this semiconductor layer; Carry out one second ion doping program, wherein, with one second incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one first spacing; And carry out one the 3rd ion doping program, wherein, with one the 3rd incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one second spacing.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this semiconductor layer is a polysilicon layer, and has a side wall construction around this grid conductor.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this ion doping program is an implanting ions program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xThe middle ion of selecting of ion forms.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this ion doping program is an ion injecting program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xMiddle this at least one ion of selecting of ion forms.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this second incident direction and the 3rd incident direction are positioned at two sides of this first incident direction.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this second incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, the 3rd incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
Again on the one hand, purpose of the present invention can also be achieved in that a kind of manufacture method of thin-film transistor of the tool flush type ldd structure that is applied to a LCD, comprises the following steps: to provide semi-conductor layer; Form the surface that a cover curtain is covered in this semiconductor layer of part; Carry out one first ion doping program, wherein, be with one perpendicular to one first incident direction on this surface with at least one ion doping this surface in this semiconductor layer; Remove this cover curtain; Forming an insulating barrier is positioned on this surface; Form a grid conductor on this surface of insulating layer; Carry out one second ion doping program, wherein, with one second incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one first spacing; And carry out one the 3rd ion doping program, wherein, with one the 3rd incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one second spacing.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this semiconductor layer is a polysilicon layer.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this ion doping program is an implanting ions program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xThe middle ion of selecting of ion forms.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this ion doping program is an ion injecting program, and by a P ion, an As ion, a PH
xAn ion and an AsH
xMiddle this at least one ion of selecting of ion forms.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this second incident direction and the 3rd incident direction are positioned at two sides of this first incident direction.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, this second incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
According to above-mentioned conception, the manufacture method of the thin-film transistor of tool flush type ldd structure of the present invention, wherein, the 3rd incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
Below, in conjunction with specific embodiments and accompanying drawing, the present invention is described in further detail.
Description of drawings
Fig. 1 is the profile of known thin-film transistor;
Fig. 2 is the profile of another known thin-film transistor;
Fig. 3 A～3E is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of known surface formula ldd structure;
Fig. 4 A～4C is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of another kind of known surface formula ldd structure;
Fig. 5 A～5D is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of first embodiment of the invention flush type ldd structure;
Fig. 6 is the low-temperature polysilicon film transistor of second embodiment of the invention flush type ldd structure;
Fig. 7 A～7D is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of third embodiment of the invention flush type ldd structure;
Fig. 8 is the low-temperature polysilicon film transistor of fourth embodiment of the invention flush type ldd structure;
Fig. 9 is the trajectory diagram that the low-temperature polysilicon film transistor electronics of flush type ldd structure of the present invention moves on raceway groove.
Embodiment
In known low-temperature polysilicon film transistor element, because this is as the cause of plane formula ldd structure, make that this low-temperature polysilicon film transistor can be unstable when work, therefore, the present invention proposes the shortcoming that a kind of new manufacture method and structure can solve known low-temperature polysilicon film transistor.
Shown in Fig. 5 A～5D, it is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of first embodiment of the present invention flush type ldd structure.And the structure of the following stated all is formed on the glass substrate (not illustrating).Shown in Fig. 5 A, utilize LASER HEAT annealing manufacture craft to form polysilicon layer (Poly-Si) 500, and form a gate insulator (Gate Insulator) 510 thereon, on gate insulator 510, form the clearance wall 535 of a grid conductor 520 and both sides thereof afterwards in regular turn, utilize clearance wall 535 structures of grid conductor 520 and both sides thereof to implement the program of ion doping for the first time afterwards, and form N type doped region (n Region) 505 for the cover curtain.Then, shown in Fig. 5 B, utilize grid conductor 520 and clearance wall 535 structures to be the cover curtain again, implementing for the second time, the ion doping program forms first lightly doped drain 542.By Fig. 5 B as can be known, implementing for the second time, the ion doping program is that the ion that will mix is gone into polysilicon layer 500 with one first incident direction with the ion doping that mixes.Therefore, first lightly doped drain 542 can be formed at the flush type ldd structure that does not contact with the surface in the polysilicon layer 500.According to present embodiment, this first incident direction and insulating barrier 510 normals are greater than the angle of 0 degree less than about 30 degree.Then, shown in Fig. 5 C, utilize grid conductor 520 and clearance wall structure 535 to be the cover curtain once more, implementing for the third time, the ion doping program forms second lightly doped drain 544.By Fig. 5 C as can be known, implementing the ion doping program for the third time is that the ion that will mix is gone into polysilicon layer 500 with second incident direction with the ion doping that mixes.Therefore, second lightly doped drain 544 can be formed at the flush type ldd structure that does not contact with the surface in the polysilicon layer 500.According to present embodiment, this second incident direction and first incident direction are positioned at two sides with insulating barrier 510 normals, and second incident direction and insulating barrier 510 normals are greater than the angles of 0 degree less than about 30 degree.Former N type doped region also becomes N type heavily doped region 505 after this step, and first lightly mixed drain area 542 and second doped-drain 544 be between two N type heavily doped regions 505, and is close to N type heavily doped region 505.Wherein, the distance between the two N type heavily doped regions 505 is greater than the distance between two lightly mixed drain areas 542,544, and can form a raceway groove between first lightly mixed drain area 542 and second lightly mixed drain area 544.Shown in Fig. 5 C.Because cloth is the incident direction of control ion when planting, therefore the position of lightly doped drain 542,544 will can not be formed at insulating barrier 510 and polysilicon layer 500 interfaces, but be formed under insulating barrier 5 10 and polysilicon layer 500 interfaces, apart from this interface one segment distance is arranged.At last, shown in Fig. 5 D, form dielectric layer (Interlayer Dielectric Layer) 515 and source electrode, drain connection 525 more in regular turn.
Manufacturing process steps in the above-described embodiments can be used two or more cloth phyteral (Doping Material), for example: PH simultaneously in the ion doping program among Fig. 5 B and Fig. 5 C
3With AsH
3Or the like.Please refer to Fig. 6, it is the low-temperature polysilicon film transistor of second embodiment of the invention flush type ldd structure.Because the difference of P and As mass of ion, when identical projectile energy, lightly doped drain 642,644 will form 642,644 months dizzy structures of lightly doped drain as shown in Figure 6 automatically, makes the effect that lightly doped drain 642,644 concentration have gradually layer.
Shown in Fig. 7 A～7D, it is the manufacturing process steps flow chart of the low-temperature polysilicon film transistor of third embodiment of the present invention flush type ldd structure.Shown in Fig. 7 A, at first, utilize photoresistance 730 to carry out the program of ion doping for the first time for the cover curtain, on polysilicon layer 700, implant N type doped region (nRegion) 705.Then, shown in Fig. 7 B, photoresistance 730 is removed, and on polysilicon layer, form an insulating barrier 710 in regular turn, and on insulating barrier 710, form a grid conductor 720 in the same position place of photoresistance.Then, utilize grid conductor 720 to be the cover curtain, implementing for the second time, the ion doping program forms first lightly doped drain 742.By Fig. 7 B as can be known, implementing ion doping program for the second time is that the ion that will mix is gone into set direction with one first the ion doping that mixes is gone into polysilicon layer 700.Therefore, first lightly doped drain 742 can be formed at the flush type ldd structure that does not contact with the surface in the polysilicon layer 700.According to present embodiment, this first incident direction and insulating barrier 710 normals are greater than the angle of 0 degree less than about 30 degree.Then, shown in Fig. 7 C, utilize grid conductor 720 to be the cover curtain once more, implementing for the third time, the ion doping program forms second lightly doped drain 744.By Fig. 7 C as can be known, implementing the ion doping program for the third time is that the ion that will mix is gone into polysilicon layer 700 with second incident direction with the ion doping that mixes.Therefore, second lightly doped drain 744 can be formed at the flush type ldd structure that does not contact with the surface in the polysilicon layer 700.According to present embodiment, this second incident direction and first incident direction are positioned at two sides with insulating barrier 710 normals, and second incident direction and insulating barrier 710 normals are greater than the angles of 0 degree less than about 30 degree.After this step, former N type doped region also becomes N type heavily doped region 705, and first lightly mixed drain area 742 and second doped-drain 744 be between two N type heavily doped regions 705, and is close to N type heavily doped region 705.Wherein, the distance between the two N type heavily doped regions 705 is greater than the distance between two lightly mixed drain areas 742,744, and can form a raceway groove between first lightly mixed drain area 742 and second lightly mixed drain area 744.Shown in Fig. 7 C.Because cloth is the incident direction of control ion when planting, so the position of lightly doped drain 742,744 will can not be formed at insulating barrier 710 and polysilicon layer 700 interfaces, but be formed under insulating barrier 710 and polysilicon layer 700 interfaces, apart from this interface one segment distance be arranged.At last, shown in Fig. 7 D, form dielectric layer (Interlayer Dielectric Layer) 715 and source electrode, drain connection (Source andDrain Metal) 725 more in regular turn.
Manufacturing process steps in the above-described embodiments can be used two or more cloth phyteral (Doping Material), for example: PH simultaneously in the ion doping program among Fig. 7 B and Fig. 7 C
3With AsH
3Or the like.Please refer to Fig. 8, it is the low-temperature polysilicon film transistor of fourth embodiment of the invention flush type ldd structure.Because the difference of P and As mass of ion, when identical projectile energy, lightly doped drain 842,844 will form 842,844 months dizzy structures of lightly doped drain as shown in Figure 8 automatically, makes the effect that lightly doped drain 842,844 concentration have gradually layer.
And these four embodiment will form similar structure shown in Figure 9 at last, because when cloth is planted, do the ion doping of twice different incidence angles degree respectively in the vertical angle both sides, and utilize higher-energy, and make lightly doped drain 942,944 structures away from polysilicon layer 900 and gate insulator 910 interfaces, and the mode of mixing can be implanting ions (ion implantation) or ion injects (ion shower), and the material of its doping is P, As ion or PH
x, AsH
xIon also can use two kinds of cloth phyterals to make lightly doped drain cloth and plant.The characteristic of structure maximum shown in Figure 9 is that the position of its lightly doped drain drain electrode 942,944 will can not be formed at insulating barrier 910 and polysilicon layer 900 interfaces, but be formed under the interface, apart from this interface one segment distance is arranged, become the low-temperature polysilicon film transistor of flush type ldd structure (Buried-LDD).As shown in the figure, when electronics near when drain electrode, the path that move the electron institute will be away from the interface of polysilicon layer 900 with insulating barrier 910, thereby hot electron is difficult for entering the interface and interrupts the change that si-h bond causes subthreshold (sub-threshold swing), also is difficult for scattering to insulating barrier 910 and the instability that causes critical voltage (Threshold Voltage).Therefore, this invention will improve the stability of low-temperature polysilicon film transistor greatly, and satisfies the demand of future products.
And the grid conductor in above-mentioned each preferred embodiment (the about 200nm of thickness) can use sputtering way to form, and it one of is selected from the materials such as chromium, molybdenum tungsten, tantalum, aluminium or copper finishes.Wherein amorphous silicon layer (the about 100nm of thickness) before using laser annealing crystallization manufacture craft to form polysilicon before, need to use earlier high temperature furnace in 400 degree annealing dehydrogenations 30 minutes, and the energy of laser crystallization manufacture craft needs at 300mJ/cm
2Under carry out 100 shootings (shots) under the condition.As for gate insulator (the about 100nm of thickness) is to form with plasma chemical vapor deposition (PECVD), is normally finished with silica.Therefore the present invention can be appointed by the person skilled in the art and executes the craftsman and think and carry out various modifications, but it does not all break away from the scope of the desired protection of claim.The above is preferred embodiment of the present invention only, is not in order to qualification protection scope of the present invention, and all other do not break away from the equivalence of being finished under the disclosed spirit and change or modification, all should be included in the protection range of claim.
Claims (10)
1, a kind of thin-film transistor structure that is applied to the tool flush type ldd structure of a LCD is characterized in that, comprising:
Semi-conductor layer;
One insulating barrier is covered in a surface of this semiconductor layer;
One first heavily doped region and one second heavily doped region are positioned on this surface of this semiconductor layer and at a distance of one first length;
One first lightly mixed drain area and one second lightly mixed drain area, be positioned at this semiconductor layer inner and and this surface between have a spacing, and this first lightly doped drain is adjacent with this first heavily doped region, this second lightly doped drain is adjacent with this second heavily doped region, and formation one raceway groove between this first lightly mixed drain area and this second lightly mixed drain area, and this raceway groove has one second length, and wherein this first length is greater than this second length; And
One grid conductor is positioned on this insulating barrier, and is covered in this raceway groove The corresponding area.
2, the thin-film transistor structure of tool flush type ldd structure as claimed in claim 1 is characterized in that, further comprises:
One dielectric layer is covered on this grid conductor and this insulating barrier; And
One drain connection and one source pole wiring run through insulating barrier and contact with this second heavily doped region with this first heavily doped region respectively with this dielectric layer.
3, the thin-film transistor structure of tool flush type ldd structure as claimed in claim 1, it is characterized in that, this semiconductor layer is a polysilicon layer, and this first heavily doped region and this second heavily doped region are respectively one the one N type heavily doped region and one the 2nd N type heavily doped region.
4, the thin-film transistor structure of tool flush type ldd structure as claimed in claim 1 is characterized in that, this first lightly mixed drain area and this second lightly mixed drain area all have concentration and be the gradually dizzy structure in January of layer distribution.
5, a kind of manufacture method that is applied to the thin-film transistor of the tool flush type ldd structure on the LCD is characterized in that, comprises the following steps:
Semiconductor structure is provided, and wherein, this semiconductor structure has semi-conductor layer, is covered in an insulating barrier on a surface of this semiconductor layer, and has a grid conductor on this insulating barrier;
Carry out one first ion doping program, wherein, be with one perpendicular to one first incident direction on this surface with at least one ion doping this surface in this semiconductor layer;
Carry out one second ion doping program, wherein, be with one second incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one first spacing; And
Carry out one the 3rd ion doping program, wherein, be with one the 3rd incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one second spacing.
6, the manufacture method of the thin-film transistor of tool flush type ldd structure as claimed in claim 5 is characterized in that, this semiconductor layer is a polysilicon layer, and has a side wall construction around this grid conductor.
7, the manufacture method of the thin-film transistor of tool flush type ldd structure as claimed in claim 5, it is characterized in that, this second incident direction and the 3rd incident direction are positioned at two sides of this first incident direction, this second incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree, and the 3rd incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
8, a kind of manufacture method of thin-film transistor of the tool flush type ldd structure that is applied to a LCD is characterized in that, comprises the following steps:
Semi-conductor layer is provided;
Form the surface that a cover curtain is covered in this semiconductor layer of part;
Carry out one first ion doping program, wherein, be with one perpendicular to one first incident direction on this surface with at least one ion doping this surface in this semiconductor layer;
Remove this cover curtain;
Forming an insulating barrier is positioned on this surface;
Form a grid conductor on this surface of insulating layer;
Carry out one second ion doping program, wherein, be with one second incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one first spacing; And
Carry out one the 3rd ion doping program, wherein, be with one the 3rd incident direction with this at least one ion doping in this semiconductor layer inner and and this surface between at a distance of one second spacing.
9, the manufacture method of the thin-film transistor of tool flush type ldd structure as claimed in claim 8 is characterized in that, this semiconductor layer is a polysilicon layer.
10, the manufacture method of the thin-film transistor of tool flush type ldd structure as claimed in claim 8, it is characterized in that, this second incident direction and the 3rd incident direction are positioned at two sides of this first incident direction, this second incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree, and the 3rd incident direction and the formed angle of this first incident direction are between spending to 30 greater than 0 degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021230862A CN1182586C (en) | 2002-06-13 | 2002-06-13 | Low-temperature polysilicon film transistor with slightly doped drain structure and its making process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021230862A CN1182586C (en) | 2002-06-13 | 2002-06-13 | Low-temperature polysilicon film transistor with slightly doped drain structure and its making process |
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| Publication Number | Publication Date |
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| CN1388590A true CN1388590A (en) | 2003-01-01 |
| CN1182586C CN1182586C (en) | 2004-12-29 |
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| CNB021230862A Expired - Fee Related CN1182586C (en) | 2002-06-13 | 2002-06-13 | Low-temperature polysilicon film transistor with slightly doped drain structure and its making process |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1312525C (en) * | 2003-06-12 | 2007-04-25 | 统宝光电股份有限公司 | Method of making liquid crystal display |
| CN100358157C (en) * | 2003-10-28 | 2007-12-26 | 统宝光电股份有限公司 | Thin film transistor and its manufacturing method |
| CN100395875C (en) * | 2003-08-07 | 2008-06-18 | 友达光电股份有限公司 | Thin film transistor manufacturing method and its structure |
| CN102683207A (en) * | 2011-03-07 | 2012-09-19 | 北大方正集团有限公司 | Method for manufacturing MOS (metal oxide semiconductor) transistor and MOS transistor device |
-
2002
- 2002-06-13 CN CNB021230862A patent/CN1182586C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1312525C (en) * | 2003-06-12 | 2007-04-25 | 统宝光电股份有限公司 | Method of making liquid crystal display |
| CN100395875C (en) * | 2003-08-07 | 2008-06-18 | 友达光电股份有限公司 | Thin film transistor manufacturing method and its structure |
| CN100358157C (en) * | 2003-10-28 | 2007-12-26 | 统宝光电股份有限公司 | Thin film transistor and its manufacturing method |
| CN102683207A (en) * | 2011-03-07 | 2012-09-19 | 北大方正集团有限公司 | Method for manufacturing MOS (metal oxide semiconductor) transistor and MOS transistor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1182586C (en) | 2004-12-29 |
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