CN1266518C - Storage capacitor structure of flat display and its preparing process - Google Patents
Storage capacitor structure of flat display and its preparing process Download PDFInfo
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- CN1266518C CN1266518C CN 02127099 CN02127099A CN1266518C CN 1266518 C CN1266518 C CN 1266518C CN 02127099 CN02127099 CN 02127099 CN 02127099 A CN02127099 A CN 02127099A CN 1266518 C CN1266518 C CN 1266518C
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Abstract
The present invention relates to the storage capacitor structure of a flat display and a manufacture method thereof. The structure of the flat display comprises one substrate, one bottom electrode, one insulating layer and one top electrode, wherein the bottom electrode is positioned above the substrate and is finished with one semiconductor material, the insulating layer is positioned on the surface of the bottom electrode, and the top electrode is provided with one dopant implantation passage. The method of the flat display comprises the following steps: the bottom electrode is implanted for dopant by using the dopant implantation passage to improve the conductive capability of the bottom electrode.
Description
Technical field
The present invention is a kind of storage capacitor structure of flat-panel screens and manufacture method thereof, refers to be applied to the storage capacitor structure and the manufacture method thereof of top grid (top gate) Thin Film Transistor-LCD especially.
Background technology
Along with manufacture technology progress, (Liquid Crystal Display, LCD) replaced traditional crt display becomes following display main flow trend to LCD, is that it is large with Thin Film Transistor-LCD (TFT-LCD) again wherein.See also Fig. 1, it is the circuit diagram of a pixel cell in the Thin Film Transistor-LCD, and its switch unit of mainly being finished by a thin film transistor (TFT) 11, a liquid crystal display 12 and a storage capacitors 13 (storage capacitor) constitute.And wherein this storage capacitors 13 is connected in parallel to this liquid crystal display 12 (it also is an electric capacity), in order to strengthen the not enough originally charge storage capacity of liquid crystal display 12, and then when improving thin film transistor (TFT) 11 and closing, the magnitude of voltage of the liquid crystal display 12 too fast phenomenon that descends.
See also Fig. 2, it is that (LowTemperature Poly Silicon Thin Film Transistor, LTPS-TFT) CMOS that grows up on a glass substrate has the fabrication steps synoptic diagram to a top grid low-temperature polysilicon film transistor.Fig. 2 (a) expression is for forming cushion a 21 (buffer layer on this glass substrate 20, usually finish with silicon dioxide) and an essential amorphous silicon (i-a-Si) layer after, utilize a radium-shine crystallization (laser crystallization) processing procedure again, essential amorphous silicon (i-a-Si) layer is transformed into an essential polysilicon (i-poly-Si) layer 22, utilize a light shield micro image etching procedure subsequently, the first essential polysilicon that essential polysilicon (i-poly-Si) layer 22 forms shown in Fig. 2 (b) is constructed 221, second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223, it provides follow-up N channel thin film transistors respectively, the use of the manufacturing process of P channel thin film transistors and storage capacitors.
Again referring to Fig. 2 (c), it is to utilize a light shield micro-photographing process and construct after 222 tops form a photoresistance cover curtain structure 23 in first essential polysilicon structure, 221, the second essential polysilicon, again part first essential polysilicon structure the 221 and the 3rd essential polysilicon that exposes is constructed 223, carry out the implantation process of a N type admixture, and then form the source/drain electrode structure 2211 of N channel thin film transistors and the bottom electrode 2231 of storage capacitors.After removing photoresistance cover curtain structure 23, cover last layer insulation material (finishing with silicon dioxide usually) again in the whole base plate top, then in order to form the gate insulator 24 shown in Fig. 2 (d).
See also Fig. 2 (e) again, it is behind sputter (sputtering) last layer gate conductor layer on the gate insulator 24, form the required grid conductor structure 251 and the top electrode 252 of storage capacitors with another light shield micro image etching procedure again, utilize this grid conductor structure 251 as the cover curtain then, carry out the implantation process of a micro-N type admixture, and then in the N channel thin film transistors, form lightly doped drain structure 2212 (Lightly Doped Drain).And utilize the formed photoresistance cover of another light shield micro-photographing process curtain structure 26 that first essential polysilicon structure the 221 and the 3rd essential polysilicon structure 223 is covered (shown in Fig. 2 (f)) again, and then the second essential polysilicon that exposes is constructed 222 carry out the implantation process of a P type admixture, and then form source/drain electrode structure 2221 of P channel thin film transistors.
And above-mentioned structure is again after successive process, just form the structure shown in (h) as Fig. 2 (g), it is after forming a core dielectric material layer (inter-layer dielectricslayer) 27 in the whole base plate top, define required contact hole (contact hole) 28 in the appropriate location, form the layer of metal conductor layer in sputter (sputtering) mode more at last and define the wiring structure 292 of required grid connection structure 290, source/drain connection structure 291 and storage capacitors upper/lower electrode.
And can know by above-mentioned explanation and to learn, splendid by the electrical conductivity of heavily doped N type polysilicon (N+-poly-Si) bottom electrode of finishing 2231, therefore, be enough to deal with required with 252 storage capacitors of finishing jointly of electrode of metal.But, when lightly doped drain being constructed the processing procedure omission of (Lightly Doped Drain) when considering manufacturing cost, then only can utilize grid conductor structure 251 to carry out the dopping process of aligning voluntarily that thin film transistor (TFT) source/drain electrode is constructed as the cover curtain.As shown in Figure 3, Fig. 3 (a) is that expression is for forming cushion a 21 (buffer layer on this glass substrate 20, usually finish with silicon dioxide) and an essential amorphous silicon (i-a-Si) layer after, utilize a radium-shine crystallization (laser crystallization) processing procedure again, essential amorphous silicon (i-a-Si) layer is transformed into an essential polysilicon (i-poly-Si) layer 22, utilize a light shield micro image etching procedure subsequently, the first essential polysilicon that essential polysilicon (i-poly-Si) layer 22 forms shown in Fig. 3 (b) is constructed 221, second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223, it provides follow-up N channel thin film transistors respectively, the manufacturing process of P channel thin film transistors and storage capacitors is used.
Again referring to Fig. 3 (c), after it covers last layer gate insulator 24 (finishing with silicon dioxide usually) and a gate conductor layer in the whole base plate top, utilize a light shield micro-photographing process that this gate conductor layer is defined again, and then in the first essential polysilicon structure 221, the top of second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223 respectively forms a grid structure 35, grid structure 36 and electrode of metal 37, but construct 222 tops in the second essential polysilicon again and form a photoresistance cover curtain structure 38 (shown in Fig. 3 (d)), and desire is constructed the 223 storage capacitors bottom electrodes of being finished when carrying out the implantation process of a N type admixture to the part exposed first essential polysilicon structure the 221 and the 3rd essential polysilicon, bottom electrode will be finished (shown in Fig. 3 (e)) because of electrode of metal can't effectively be implanted admixture, and then can't form heavily doped N type polysilicon, cause the conductive capability deficiency of this bottom electrode, make storage capacitors can't bring into play due function.
In addition, only carry out PMOS processing procedure (or NMOS processing procedure as shown in Figure 4 separately for reducing cost, but actual due to leakage current is used greatly and seldom very much) time, wherein Fig. 4 (a) is that expression is for forming cushion a 21 (buffer layer on this glass substrate 20, usually finish with silicon dioxide) and an essential amorphous silicon (i-a-Si) layer after, utilize radium-shine crystallization (lasercrystallization) processing procedure again, essential amorphous silicon (i-a-Si) layer is transformed into an essential polysilicon (i-poly-Si) layer, utilize a light shield micro image etching procedure subsequently, essential polysilicon (i-poly-Si) layer is formed second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223, and it provides the manufacturing process of follow-up P channel thin film transistors and storage capacitors to use respectively.After covering last layer gate insulator 24 (finishing with silicon dioxide usually) and a gate conductor layer in whole base plate 20 tops subsequently, utilize a light shield micro-photographing process that this gate conductor layer is defined again, and then respectively form grid structure 36 and electrode of metal 37 in the top of second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223.But when desire utilizes grid structure 36 for cover curtain second essential polysilicon structure 221 implantation process that carry out a p type admixture to be come formation source/drain electrode structure (shown in Fig. 4 (b)), the 3rd essential polysilicon structure 223 storage capacitors bottom electrodes of being finished will have been finished and can't have been implanted admixture effectively simultaneously because of electrode of metal 37, and then can't form heavily doped P type polysilicon, cause the conductive capability deficiency of this bottom electrode, make storage capacitors can't bring into play due function.And how to improve the problem of above-mentioned all existing means, be for developing fundamental purpose of the present invention.
Summary of the invention
The present invention is a kind of storage capacitor structure of flat-panel screens, and it comprises: a substrate; One bottom electrode is positioned at the top of this substrate, and it is finished with the semiconductor material; One insulation course is positioned on the surface of this bottom electrode; An and top electrode, be positioned on the surface of this insulation course, this top electrode is finished with metal, the shape of this top electrode is to be selected from pectination and netted one of them, and the gap that is had on this pectination and the netted structure is just for implanting passage for admixture by the admixture of implanting in this bottom electrode, by implanting in this bottom electrode, and then improve the conductive capability of this bottom electrode for admixture.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, its applied this flat-panel screens is a top grid Thin Film Transistor-LCD.
According to above-mentioned conception, this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor.
According to above-mentioned conception, this bottom electrode is to be finished through the polysilicon that mixes in the storage capacitor structure of flat-panel screens of the present invention.
According to above-mentioned conception, this bottom electrode is the drain electrode that is electrically connected to this top grid thin film transistor (TFT) in the storage capacitor structure of flat-panel screens of the present invention.
According to above-mentioned conception, this insulation course is finished with silicon dioxide in the storage capacitor structure of flat-panel screens of the present invention.
Another aspect of the invention is a kind of storage capacitor structure manufacture method of flat-panel screens, it comprises the following step: a substrate is provided; Form a bottom electrode in the top of this substrate, the material of this bottom electrode is a semiconductor; On the surface of this bottom electrode, form an insulation course; Form a top electrode with metal on the surface of this insulation course, the shape of this top electrode is to be selected from pectination and netted one of them, and the gap that is had on this pectination and the netted structure is just for implanting passage for admixture by the admixture of implanting in this bottom electrode; And utilize this admixture to implant passage this bottom electrode is implanted admixture, and then improve the conductive capability of this bottom electrode.
According to above-mentioned conception, in the storage capacitor structure manufacture method of flat-panel screens of the present invention, this flat-panel screens is a top grid Thin Film Transistor-LCD, and this substrate is to be a transparent substrates.
According to above-mentioned conception, this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor.
According to above-mentioned conception, the channel layer of this bottom electrode and this top grid thin film transistor (TFT) is all finished with polysilicon in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, this bottom electrode is the drain electrode that is electrically connected to this top grid thin film transistor (TFT) in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, this insulation course is finished with silicon dioxide in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
Of the present invention is a kind of storage capacitor structure manufacture method of flat-panel screens more on the one hand, and it comprises the following step: a substrate is provided; Form a bottom electrode in the top of this substrate, the material of this bottom electrode is a semiconductor; On the surface of this bottom electrode, form an insulation course; Form a top electrode on the surface of this insulation course, the material of this top electrode is a semiconductor; By this top electrode this bottom electrode is carried out one first admixture and implant action, to improve the conductive capability of this bottom electrode; And this top electrode is carried out one second admixture implant action, to improve the conductive capability of this top electrode.
According to above-mentioned conception, this flat-panel screens is a top grid Thin Film Transistor-LCD, and this substrate is to be a transparent substrates.
According to above-mentioned conception, this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor.
According to above-mentioned conception, the channel layer of this bottom electrode and this top grid thin film transistor (TFT) is all finished with polysilicon in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, this bottom electrode is the drain electrode that is electrically connected to this top grid thin film transistor (TFT) in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, this insulation course is finished with silicon dioxide in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, this top electrode is finished with polysilicon in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
According to above-mentioned conception, the admixture implantation depth of this first admixture implantation action is an admixture implantation depth of implanting action greater than this second admixture in the storage capacitor structure manufacture method of flat-panel screens of the present invention.
Another aspect of the present invention is a kind of storage capacitor structure of flat-panel screens, and it comprises: a substrate; One bottom electrode is formed at the top of this substrate, and the material of this bottom electrode is the heterogeneous semiconductor through mixing; One insulation course is formed on the surface of this bottom electrode; And a top electrode, being formed on the surface of this insulation course, the material of this top electrode is the heterogeneous semiconductor through mixing.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this flat-panel screens is a top grid Thin Film Transistor-LCD, and this substrate is a transparent substrates.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this bottom electrode is to be finished through the heterogeneous polysilicon that mixes.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this bottom electrode is the drain electrode that is electrically connected to this top grid thin film transistor (TFT).
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this insulation course is finished with silicon dioxide.
According to above-mentioned conception, the storage capacitor structure of flat-panel screens of the present invention, wherein this top electrode is to be finished through the heterogeneous polysilicon that mixes.
Description of drawings
The present invention can get a more deep understanding by following graphic and detailed description:
Fig. 1 is the circuit diagram of a pixel cell in the Thin Film Transistor-LCD.
Fig. 2 (a) (b) (c) (d) (e) (f) (g) (h): be a top grid low-temperature polysilicon film transistor (Low Temperature Poly Silicon Thin Film Transistor, LTPS-TFT) grow up existing CMOS fabrication steps synoptic diagram on a glass substrate.
Fig. 3 (a) is (c) (d) (e) (b): be with the existing thin film transistor (TFT) fabrication steps synoptic diagram in the processing procedure abridged of lightly doped drain structure (Lightly Doped Drain).
Fig. 4 (a) is that (Low TemperaturePoly Silicon Thin Film Transistor, LTPS-TFT) PMOS that grows up on a glass substrate has the fabrication steps synoptic diagram to a top grid low-temperature polysilicon film transistor (b).
Fig. 5 (a) is (c) (d) (e) (b): the preferred embodiment fabrication steps synoptic diagram that develops the storage capacitor structure manufacture method that when it is the present invention for the CMOS processing procedure that omits lightly doped drain structure (Lightly Doped Drain).
Fig. 6 (a) is (b): it is the present invention for top grid low-temperature polysilicon film transistor (LowTemperature Poly Silicon Thin Film Transistor, LTPS-TFT) the grow up preferred embodiment fabrication steps synoptic diagram of the storage capacitor structure manufacture method that PMOS processing procedure on a glass substrate developed.
Fig. 7 (a) is (b): it is the present invention for the grow up preferred embodiment fabrication steps synoptic diagram of another storage capacitor structure manufacture method that processing procedure developed on a glass substrate of top grid low-temperature polysilicon film transistor.
Embodiment
See also Fig. 5, when being the present invention for the CMOS processing procedure that omits lightly doped drain structure (Lightly DopedDrain), it develops the storage capacitor structure manufacture method that, Fig. 5 (a) is shown in to form cushion a 21 (buffer layer on this glass substrate 20, usually finish with silicon dioxide) and an essential amorphous silicon (i-a-Si) layer after, utilize radium-shine crystallization (lasercrystallization) processing procedure again, essential amorphous silicon (i-a-Si) layer is transformed into an essential polysilicon (i-poly-Si) layer 22, utilize a light shield micro image etching procedure subsequently, the first essential polysilicon that essential polysilicon (i-poly-Si) layer 22 forms shown in Fig. 5 (b) is constructed 221, second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223, it provides follow-up N channel thin film transistors respectively, the manufacturing process of P channel thin film transistors and storage capacitors is used.
Again referring to Fig. 5 (c), after it covers last layer gate insulator 24 (finishing with silicon dioxide usually) and a gate conductor layer in the whole base plate top, utilize a light shield micro-photographing process that this gate conductor layer is defined again, and then respectively form a grid structure 35, grid structure 36 and electrode of metal 57 in the top of first essential polysilicon structure 221, second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223.Form a photoresistance cover curtain structure 38 (shown in Fig. 5 (d)) and ought construct 222 tops in the second essential polysilicon again, and the part exposed first essential polysilicon structure the 221 and the 3rd essential polysilicon is constructed the 223 storage capacitors bottom electrodes of being finished when carrying out the implantation process of a N type admixture, because of the view in shape of electrode of metal 57 of the present invention is defined as pectination (shown in Fig. 5 (e)) or netted, therefore bottom electrode can be implanted passage and can effectively be implanted admixture by its admixture that has, and then diffuse to form heavily doped N type polysilicon, cause this bottom electrode to have enough conductive capabilities, make storage capacitors can bring into play due function.
In addition, only carry out PMOS processing procedure (or NMOS processing procedure as shown in Figure 6 separately for reducing cost, but actual due to leakage current is used greatly and seldom very much) time, wherein Fig. 6 (a) is shown in to form cushion a 21 (buffer layer on this glass substrate 20, usually finish with silicon dioxide) and an essential amorphous silicon (i-a-Si) layer after, utilize a radium-shine crystallization (laser crystallization) processing procedure again, essential amorphous silicon (i-a-Si) layer is transformed into an essential polysilicon (i-poly-Si) layer, utilize a light shield micro image etching procedure subsequently, essential polysilicon (i-poly-Si) layer is formed second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223, and it provides the manufacturing process of follow-up P channel thin film transistors and storage capacitors to use respectively.After covering last layer gate insulator 24 (finishing with silicon dioxide usually) and a gate conductor layer in whole base plate 20 tops subsequently, utilize a light shield micro-photographing process that this gate conductor layer is defined again, and then respectively form grid structure 36 and electrode of metal 57 in the top of second essential polysilicon structure the 222 and the 3rd essential polysilicon structure 223.But when desire utilizes grid structure 36 for cover curtain second essential polysilicon structure 222 implantation process that carry out a P type admixture to be come formation source/drain electrode structure (shown in Fig. 6 (b)), the 3rd essential polysilicon structure 223 storage capacitors bottom electrodes of being finished are pectination (also shown in Fig. 5 (e)) or netted because of the view definition in shape of electrode of metal 57 of the present invention, therefore the 3rd essential polysilicon structure 223 bottom electrodes of being finished can utilize the gap that has on this pectination and the netted structure, as implanting passage by the admixture of implanting in this bottom electrode for admixture, and then admixture effectively implanted this bottom electrode and then diffuse to form heavily doped P type polysilicon, cause this bottom electrode to have enough conductive capabilities, make storage capacitors can bring into play due function.
In addition, when the top electrode 71 of storage capacitors is all finished with essential polysilicon with bottom electrode 70, this top electrode just need not form above-mentioned pectination or netted, and only need respectively this bottom electrode and top electrode to be carried out one first admixture implantation action and one second admixture implantation action, but the admixture implantation depth that needs this first admixture of control to implant action is implanted the admixture implantation depth of action greater than this second admixture, make upper/lower electrode all can form heavily doped polysilicon, so finish this storage capacitor structure (as Fig. 7 (a) (b) shown in).
And the transparent substrates in above-mentioned each preferred embodiment can be finished with transparent glass, and conductor layer (the about 200nm of thickness) can use sputtering way to form, and it is one of to be selected from the materials such as chromium, molybdenum tungsten, tantalum, aluminium or copper to finish.Cushion (the about 600nm of thickness) is that electricity consumption pulp vapour deposition process (PECVD) forms, and can be selected from silicon nitride, monox or both combinations and finish.Wherein amorphous silicon layer (the about 100nm of thickness) is in using before radium-shine annealing crystallization processing procedure forms polysilicon, need to use earlier high temperature furnace in 400 degree annealing dehydrogenations 30 minutes, and the energy of radium-shine crystallization processing procedure needs at 300mJ/cm
2Under condition under carry out 100 times the shooting (shots).This heavy doping ion cloth value processing procedure can As or the P ion mixes and its doping content (doping concentration) is about 10
15Cm
-2And pectination or the tusk gap of net metal top electrode 57 is about 10 microns.As for gate insulator (the about 100nm of thickness) is that electricity consumption pulp vapour deposition process (PECVD) forms, and is normally finished with monox.So the present invention must be thought and is to modify the neither protection domain that takes off as claim as all by the personage Ren Shi craftsman who has the knack of this technology.
Claims (4)
1, a kind of storage capacitor structure of flat-panel screens, it comprises:
One substrate;
One bottom electrode is positioned at the top of this substrate, and it is finished with the semiconductor material;
One insulation course is positioned on the surface of this bottom electrode; And
One top electrode, be positioned on the surface of this insulation course, this top electrode is finished with metal, the shape of this top electrode is to be selected from pectination and netted one of them, and the gap that is had on this pectination and the netted structure is just for implanting passage for admixture by the admixture of implanting in this bottom electrode, by implanting in this bottom electrode, and then improve the conductive capability of this bottom electrode for admixture.
2, the storage capacitor structure of flat-panel screens as claimed in claim 1, it is characterized in that this flat-panel screens is a top grid Thin Film Transistor-LCD, this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor, and this substrate is a transparent substrates, this bottom electrode is being finished and to be electrically connected to the drain electrode of this top grid thin film transistor (TFT) through the polysilicon that mixes, and this insulation course is finished with silicon dioxide.
3, a kind of storage capacitor structure manufacture method of flat-panel screens, it comprises the following step:
One substrate is provided;
Form a bottom electrode in the top of this substrate, the material of this bottom electrode is a semiconductor;
On the surface of this bottom electrode, form an insulation course; And
Form a top electrode with metal on the surface of this insulation course, the shape of this top electrode is to be selected from pectination and netted one of them, and the gap that is had on this pectination and the netted structure is just for implanting passage for admixture by the admixture of implanting in this bottom electrode; And
Utilize this admixture to implant passage this bottom electrode is implanted admixture, and then improve the conductive capability of this bottom electrode.
4, the storage capacitor structure manufacture method of flat-panel screens as claimed in claim 3, it is characterized in that this flat-panel screens is a top grid Thin Film Transistor-LCD, this top grid thin film transistor (TFT) is a low-temperature polysilicon film transistor, and this substrate is a transparent substrates, wherein this bottom electrode is the drain electrode that is electrically connected to this top grid thin film transistor (TFT), and the channel layer of this bottom electrode and this top grid thin film transistor (TFT) is all finished with polysilicon, and this insulation course is finished with silicon dioxide.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02127099 CN1266518C (en) | 2002-07-29 | 2002-07-29 | Storage capacitor structure of flat display and its preparing process |
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| CN 02127099 CN1266518C (en) | 2002-07-29 | 2002-07-29 | Storage capacitor structure of flat display and its preparing process |
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| CNB2006100923712A Division CN100426456C (en) | 2002-07-29 | 2002-07-29 | Structure of storage capacitance in panel display, and manufacturing method |
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| CN1266518C true CN1266518C (en) | 2006-07-26 |
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| US20060061701A1 (en) * | 2004-09-22 | 2006-03-23 | Shih-Chang Chang | Pixel of a liquid crystal panel, method of fabricating the same and driving method thereof |
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