CN108807422B - Array substrate manufacturing method, array substrate and display panel - Google Patents
Array substrate manufacturing method, array substrate and display panel Download PDFInfo
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- CN108807422B CN108807422B CN201810605946.9A CN201810605946A CN108807422B CN 108807422 B CN108807422 B CN 108807422B CN 201810605946 A CN201810605946 A CN 201810605946A CN 108807422 B CN108807422 B CN 108807422B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention provides an array substrate, a manufacturing method thereof and a display panel. The grid electrode layer is obtained by etching the grid electrode material layer twice, and the polycrystalline silicon material layer is subjected to ion doping twice, so that the polycrystalline silicon layers corresponding to low-doped regions with different lengths of different thin film transistors are obtained under the condition that no photomask is added, and the manufacturing cost of the array substrate and the manufacturing cost of the display panel are reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate manufacturing method, an array substrate and a display panel.
Background
The polysilicon array substrate has high carrier mobility, and thus is widely applied to a middle-sized, small-sized and high-resolution liquid crystal display panel (L CD) or an organic light emitting display panel (O L ED).
In a conventional polysilicon array substrate, in order to effectively improve the reliability of a TFT device in the polysilicon array substrate, to reduce hot carrier effects caused by a horizontal or lateral electric field of the TFT device, and to reduce optical display defects such as cross, flicker, contrast, etc. caused by excessive leakage current under a negative bias condition, the TFT device is generally fabricated by using NP IMP MASK and GE self-alignment techniques to form a low-doped high-impedance L DD region (MASK L DD), which functions as a large resistor in series at both ends of a channel.
Disclosure of Invention
The invention provides an array substrate manufacturing method, an array substrate and a display panel comprising the array substrate, wherein low-doped regions with different lengths are obtained without adding a photomask, so that the manufacturing cost of the array substrate is reduced.
The manufacturing method of the array substrate comprises the following steps:
providing a substrate, forming a polycrystalline silicon material layer on the substrate, and patterning the polycrystalline silicon material layer to obtain a polycrystalline silicon pattern layer; the polycrystalline silicon pattern layer comprises a first polycrystalline silicon pattern and a second polycrystalline silicon pattern;
sequentially forming a grid insulation layer and a grid material layer on the polycrystalline silicon pattern layer, and patterning the grid material layer through a second photomask to obtain a grid pattern layer; the grid pattern layer comprises a first grid pattern, a second grid pattern and one or more auxiliary patterns which are arranged at intervals and positioned on at least one side of the second grid pattern, and the first grid pattern and the second grid pattern respectively comprise a first part and second parts positioned on two sides of the first part; the first grid pattern is laminated on the first polysilicon pattern and partially covers the first polysilicon pattern in the direction vertical to the substrate; the second grid pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in the direction vertical to the substrate;
heavily doping the polysilicon pattern layer from one side of the gate pattern layer, wherein the region of the first polysilicon pattern not covered by the first gate pattern is doped to form a highly doped region; the region of the second polysilicon pattern layer which is not covered by the second grid pattern and the auxiliary pattern is doped to form a high-doped region;
etching the gate pattern layer to etch away the auxiliary pattern, etching away a second portion of the first gate pattern to obtain a first gate, and etching away a second portion of the second gate pattern to obtain a second gate, wherein the first gate and the second gate are both located on the gate layer;
lightly doping the polysilicon pattern layer from one side of the gate layer so as to form a low-doped region of the first polysilicon pattern in a region corresponding to the second part of the first gate pattern, and form a low-doped region of the second polysilicon pattern in a region corresponding to the second part of the second gate pattern and a region covered by the auxiliary pattern; the region corresponding to the first grid electrode forms the channel region of the first polysilicon pattern, and the region corresponding to the second grid electrode forms the channel region of the second polysilicon pattern.
Wherein, the method further comprises the following steps after the first polysilicon pattern and the second polysilicon pattern are obtained:
and forming a flat layer on the gate layer and the gate insulating layer which is not covered by the gate layer, forming a pixel electrode and a signal wire on the flat layer, electrically connecting the pixel electrode with the high-doping area on one side of the channel area of the first polysilicon pattern through a via hole, and electrically connecting the signal wire with the high-doping area of the first polysilicon pattern which is not electrically connected with the pixel electrode, and electrically connecting the two sides of the channel area of the second polysilicon layer far away from the high-doping area of the channel area.
Before the polysilicon material layer is formed on the substrate, the method further comprises the following steps:
and forming a buffer layer on the substrate, wherein the buffer layer is positioned between the substrate and the polycrystalline silicon material layer.
Wherein, before forming the buffer layer on the substrate, the method further comprises the steps of:
and forming a shading material layer on the substrate, patterning the shading material layer to obtain a shading layer, wherein the shading layer comprises a plurality of shading areas arranged at intervals in an array mode, and the orthographic projection of each shading area on the polycrystalline silicon material layer covers the channel area of the first polycrystalline silicon pattern.
And carrying out the heavy doping and the light doping by a GE self-alignment technology and an ion doping technology to obtain the high-doped region and the low-doped region.
The array substrate comprises a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first polycrystalline silicon layer, and the second thin film transistor comprises a second polycrystalline silicon layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer are positioned on the same layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer respectively comprise a channel region, a low-doped region and a high-doped region, and the low-doped region and the high-doped region are arranged on two sides of the channel region; the two sides of the channel region of the first polycrystalline silicon layer respectively comprise a low-doped region and a high-doped region, and the low-doped region is positioned between the channel region and the high-doped region; at least one side of the channel region of the second polycrystalline silicon layer comprises at least two low-doped regions and at least two high-doped regions, the high-doped regions and the low-doped regions are alternately arranged, and the low-doped regions are close to the channel region relative to the high-doped regions; the length of the low-doped region of the first polysilicon layer is the same as the length of one of the at least two low-doped regions of the second polysilicon layer that is close to the channel region.
Wherein, a first grid insulation layer and a first grid are sequentially laminated on the first polysilicon layer; a second grid electrode insulating layer and a second grid electrode are sequentially laminated on the second polycrystalline silicon layer; the first grid electrode insulating layer and the second grid electrode insulating layer are positioned on the same layer and connected; the first grid and the second grid are positioned on the same layer and are arranged at intervals; the projection of the first grid electrode on the first polycrystalline silicon layer, which is vertical to the first polycrystalline silicon layer, covers the first grid electrode; the projection of the second grid electrode on the second polycrystalline silicon layer, which is perpendicular to the second polycrystalline silicon layer, covers the second grid electrode.
The first polycrystalline silicon layer and/or the second polycrystalline silicon layer are/is a U-shaped polycrystalline silicon layer or a square polycrystalline silicon layer.
The low-doped regions and the high-doped regions on two sides of the channel regions of the first thin film transistor and the second thin film transistor are symmetrically arranged.
The display panel comprises the array substrate.
The grid electrode layer is obtained by etching the grid electrode material layer twice, and the polycrystalline silicon material layer is subjected to ion doping twice, so that the polycrystalline silicon layers of low-doped regions with different lengths corresponding to different thin film transistors are obtained under the condition of not increasing a photomask. Specifically, in the present invention, the low-doped region of the second polysilicon layer includes a region corresponding to the auxiliary pattern, and a region corresponding to a portion of the second gate pattern etched away to form the second gate; and the low-doped region of the first polysilicon layer only comprises a region corresponding to the etched-out part of the first gate pattern forming the first gate. In addition, when the second etching is performed, the etching time for the first gate pattern and the second gate pattern is the same, so that the size of the etched portion of the first gate pattern and the second gate pattern is the same, and thus, the length of the low-doped region of the second polysilicon layer is longer than that of the low-doped region of the first polysilicon layer. Therefore, the low-doped regions with different lengths corresponding to different thin film transistors can be obtained under the condition of not increasing a photomask.
Drawings
To more clearly illustrate the structural features and effects of the present invention, a detailed description is given below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention;
fig. 2 is a flow chart illustrating a manufacturing process of the array substrate according to an embodiment of the invention;
fig. 3 to 7 are cross-sectional views of steps of a manufacturing process of the array substrate according to an embodiment of the invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The drawings are for illustrative purposes only and are merely schematic representations, not intended to limit the present patent.
The invention provides a display panel which is used for displaying pictures, and the display panel can be a liquid crystal display panel (L CD display panel) or a light emitting diode display panel (O L ED display panel). The display panel comprises an array substrate, a color film substrate opposite to the array substrate and a liquid crystal layer positioned between the array substrate and the color film substrate when the display panel is the liquid crystal display panel, and a light emitting layer and a cathode layer which are arranged on the array substrate when the display panel is the light emitting diode display panel.
The array substrate comprises a display area and a non-display area surrounding the display area, the array substrate comprises a plurality of different thin film transistors, for example, the different thin film transistors comprise thin film transistors positioned in the display area and used for controlling pixel units to emit light, electrostatic protection thin film transistors (ESD) positioned in the non-display area, multi-splitter thin film transistors (demux TFT), and the like, wherein the lengths of low-doped areas (L DD) of the different thin film transistors are different due to different sizes and functions of the different thin film transistors so as to adaptively reduce the hot carrier effect of the thin film transistors and improve the reliability of the thin film transistors.
Referring to fig. 1, the present application provides an array substrate 100. The array substrate 100 includes a first thin film transistor 10 and a second thin film transistor 20. In this embodiment, the first thin film transistor is a thin film transistor located in the display region; the second thin film transistor 20 is an esd protection thin film transistor located in the non-display region. The first thin film transistor 10 includes a first polysilicon layer 11, a first gate insulating layer 12, and a first gate electrode 13, which are sequentially stacked. The second thin film transistor 20 includes a second polysilicon layer 21, a second gate insulating layer 22, and a second gate 23, which are sequentially stacked. The first polysilicon layer 11 and the second polysilicon layer 21 are positioned on the same layer and are arranged at intervals, and the layer where the first polysilicon layer 11 and the second polysilicon layer 21 are positioned is a polysilicon layer; the first gate insulating layer 12 and the second gate insulating layer 22 are located on the same layer and connected, and the layer where the first gate insulating layer 12 and the second gate insulating layer 22 are located is a gate insulating layer; the first gate 13 and the second gate 23 are located on the same layer and are spaced apart from each other. The first polysilicon layer 11 and the second polysilicon layer 21 may be U-shaped polysilicon layers, square-shaped polysilicon layers, or polysilicon layers of other shapes. Wherein the U-shaped polysilicon layer can be obtained by bending the square-shaped polysilicon layer. The present invention will be described by taking a case where the first polysilicon layer 11 and the second polysilicon layer 21 are both square-block-shaped polysilicon layers.
The first polysilicon layer 11 includes a channel region 111, a low-doped region 112, and a high-doped region 113. Both sides of the channel region 111 of the first polysilicon layer 11 include one of the low-doped regions 112 and one of the high-doped regions 113, and the low-doped region 112 is located between the channel region 111 and the high-doped region 113. The projection of the first gate 13 on the first polysilicon layer 11 perpendicular to the first polysilicon layer 11 covers the channel region 111. The second silicon layer includes a channel region 211, a low doped region 212, and a high doped region 213. At least one side of the channel region 211 includes at least two low-doped regions 212 and at least two high-doped regions 213, the high-doped regions 213 and the low-doped regions 212 are alternately disposed, and the low-doped regions 212 are close to the channel region 211 relative to the high-doped regions 213. The projection of the second gate 23 on the second polysilicon layer 21 perpendicular to the second polysilicon layer 21 covers the channel region 211. In this embodiment, two low-doped regions 212 and two high-doped regions 213 are disposed on two sides of the channel region 211, and the two low-doped regions 212 and the two high-doped regions 213 are alternately disposed. In this embodiment, the low doped region and the high doped region on both sides of the channel region 111 and the channel region 211 are symmetrical. In this embodiment, the two low-doped regions 212 on two sides of the channel region 211 are a first low-doped region 2121 and a second low-doped region 2122; the two highly doped regions 213 on two sides of the channel region 211 are a first highly doped region 2131 and a second highly doped region 2132, respectively. The first low-doped region 2121, the first high-doped region 2131, the second low-doped region 2122 and the second high-doped region 2132 extend from the channel region 211 in a direction away from the channel region 211, that is, the first low-doped region 2121 is closest to the channel region 211, and the second high-doped region 2132 is farthest from the channel region 211. In the present invention, the low-doped region 112 of the first polysilicon layer 11 has the same length as the low-doped region 212 of the at least two low-doped regions 212 of the second polysilicon layer 21 close to the channel region 211. In this embodiment, the low-doped region 112 of the first polysilicon layer 11 and the first low-doped region 2121 of the second polysilicon layer 21 have the same length. Wherein the direction of the length refers to a direction extending from the channel region to the doped region. In another embodiment of the present invention, one side of the channel region has two low-doped regions and two high-doped regions, and the other side has one low-doped region and one high-doped region.
In the present invention, since the lengths of the lowly doped region 112 of the first polysilicon layer 11 and the first lowly doped region 2121 of the second polysilicon layer 21 are the same, and the lowly doped region 212 of the second polysilicon layer 21 further includes a second lowly doped region 2122, the total length of the lowly doped region 212 of the second thin film transistor 2021 of the present application is longer than the total length of the lowly doped region 112 of the first thin film transistor 1011, so as to satisfy the requirement of practical use.
Further, a planarization layer 60 is stacked on both the first gate electrode 13 of the first thin film transistor 10 and the second gate electrode 23 of the second thin film transistor 20. The flat layer is provided with a plurality of signal traces (SD traces) 70 and pixel electrodes 80 which are arranged at intervals in an insulating manner. Wherein the pixel electrode 80 is located in the display region and electrically connected to a highly doped region 113 on one side of the channel layer of the first thin film transistor 10 through a via hole. A highly doped region 113 of the first thin film transistor 10, which is not connected to the pixel electrode 80, is electrically connected to one of the signal traces 70 through a via. One of the highly doped regions of the second thin film transistor 20 away from the channel region 211 is electrically connected to one of the signal traces 70. In this embodiment, the second highly doped region 2132 of the second thin film transistor 20 is electrically connected to a signal trace 70. Data signals are transmitted for the first thin film transistor 10 and the second thin film transistor 20 through the signal trace 70.
Further, the array substrate 100 of the present invention further includes a substrate 30, and the first thin film transistor 10 and the second thin film transistor 20 are formed on the substrate 30. the substrate 30 may be a rigid substrate or a flexible substrate, for example, when a rigid L CD display panel or an O L ED display panel is required, the substrate 30 may be a rigid glass substrate, and when a flexible display panel (such as an AMO L ED panel) is required, the substrate 30 may be a flexible plastic substrate.
Further, in some embodiments of the present invention, a light shielding layer 40 and a buffer layer 50 are sequentially stacked on the substrate 30. The light shielding layer 40 is located in the display region and includes a plurality of light shielding regions arranged in an array at intervals. The orthographic projection of each light shielding region on the first polysilicon layer 11 covers the channel region of the first polysilicon layer 11, so as to prevent light from irradiating the channel region 111 of the first polysilicon layer 11 and prevent the channel region 111 from being damaged due to illumination. The buffer layer 50 is located between the light shielding layer 40 and the first polysilicon layer 11 and the second polysilicon layer 21 of the first thin film transistor 10 and the second thin film transistor 20, so as to ensure that the first polysilicon layer 11 and the second polysilicon layer 21 can be well combined with the substrate 30.
Referring to fig. 2, the present invention further provides a method for manufacturing an array substrate 100, which is used to manufacture and obtain the array substrate 100. The patterning of the present invention includes the steps of exposure, development, etching, etc. through a mask. Specifically, the method for manufacturing the array substrate 100 of the present application includes the steps of:
In this embodiment, the first polysilicon pattern 11a includes a first portion 111a, a second portion 112a located at two sides of the first portion 111a, and a third portion 113a located at a side of the second portion 112a away from the first portion 111 a. The second polysilicon pattern 21a includes a first portion 211a, a second portion 212a located at two sides of the first portion 211a, and a third portion 213a, a fourth portion 214a, and a fifth portion 215a sequentially disposed from a side of the second portion 212a away from the first portion 211 a.
In some embodiments of the present invention, before forming the polysilicon material layer on the substrate 30, the method further includes step 111: a buffer layer 50 is formed on the substrate 30. The buffer layer 50 is located between the substrate 30 and the polysilicon material layer. In other embodiments of the present invention, before forming the buffer layer 50 on the substrate 30, the method further includes step 112: forming a light shielding material layer on the substrate 30, and patterning the light shielding material layer to obtain a light shielding layer 40, wherein the light shielding layer 40 includes a plurality of light shielding regions arranged in an array at intervals. The buffer layer 50 covers the light-shielding layer 40.
In step 120, referring to fig. 4, a gate insulating layer and a gate material layer are sequentially formed on the polysilicon pattern layer. And patterning the grid material layer to obtain a grid pattern layer.
The gate insulation layer includes a first gate insulation layer 12 and a second gate insulation layer 22. The first gate insulating layer 21 is stacked over the first polysilicon pattern 11 a; the first gate insulating layer 22 is stacked over the first polysilicon pattern 21 a. The gate pattern layer includes a first gate pattern 13a, a second gate pattern 23a, and one or more auxiliary patterns 24a disposed at intervals, and the one or more auxiliary patterns 24a are located at least one side of the second gate pattern facing the pattern 23 a. The first gate pattern 13a, the second gate pattern 23a, and the auxiliary pattern 24a are disposed at intervals. The first gate pattern 13a and the second gate pattern 23a each include a first portion and second portions located at both sides of the first portion. The first gate pattern 13a is stacked on the first polysilicon pattern 21a, and partially covers the first polysilicon pattern 21a in a direction perpendicular to the substrate 30. In this embodiment, the first gate pattern 13a covers the first and second portions 111a and 112a of the first polysilicon pattern in a direction perpendicular to the substrate 30. Specifically, a first portion of the first gate pattern 13a corresponds to a first portion 111a of the first polysilicon pattern, and a second portion corresponds to a second portion 112a of the first polysilicon pattern. The second gate pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in a direction perpendicular to the substrate. In this embodiment, the second gate pattern 23a covers the first portion 211a and the second portion 212a of the second polysilicon pattern in a direction perpendicular to the substrate 30. The auxiliary pattern 24a covers the fourth portion 214a of the second polysilicon pattern. Specifically, the first portion of the second gate pattern corresponds to the first portion 211 of the second polysilicon pattern, and the second portion of the second gate pattern corresponds to the second portion 212a of the second polysilicon pattern.
In the invention, the polysilicon material layer is heavily doped from the gate pattern layer by a gate self-alignment technology (GE self-alignment technology) and an ion heavy doping technology. In this embodiment, the polysilicon material layer is heavily doped to N-type ions. Specifically, the N-type ions in this embodiment are phosphorus ions. Specifically, when the polysilicon material layer is heavily doped from the gate pattern layer, the N-type ions cannot diffuse to the polysilicon material layer through the gate pattern layer, and thus, the position covered by the gate pattern layer is not doped, and the position not covered by the gate pattern layer is doped to form a heavily doped region. In this embodiment, the third portion 113a of the first polysilicon pattern 11a is ion heavily doped to form the heavily doped region. The heavily doped region of the first polysilicon pattern 11a is a highly doped region 113 of the first polysilicon layer 11 in this embodiment; the third portion 213a and the fifth portion 215a of the second polysilicon pattern 21a are heavily doped with ions to form the heavily doped region, the heavily doped region obtained by heavily doping the third portion 213a is the first highly doped region 2131 of the second polysilicon layer 21 of this embodiment, and the highly doped region obtained by heavily doping the fifth portion 215a with ions is the second highly doped region 2132 of the second polysilicon layer 21 of this embodiment.
In step 140, referring to fig. 6, the gate pattern layer is further etched to obtain a gate layer, where the gate layer includes the first gate 13 and the second gate 23. When the gate pattern layer is etched to obtain the gate layer, the auxiliary pattern 24a is etched, the first gate pattern 13a is etched to obtain the first gate 13, and the second gate pattern 23a is etched to obtain the second gate 23.
Specifically, the gate pattern layer is subjected to wet etching or dry etching to simultaneously remove the auxiliary pattern 24a, partially etch the first gate pattern 13a to obtain the first gate 13, and partially etch the second gate pattern 23a to obtain the second gate 23. During etching, the first gate pattern 13a and the second gate pattern 23a are simultaneously etched, so that the first gate pattern 13a and the etched portion of the gate pattern have the same size. The sizes of the first gate 13 and the second gate 23 obtained by etching the gate pattern layer are reduced compared with the sizes of the first gate pattern 13a and the second gate pattern 23a, so that the area of the first polysilicon pattern originally covered by the first gate pattern 13a is not completely covered by the first gate 13, the area of the second polysilicon pattern originally covered by the second gate pattern 23a is not completely covered by the second gate 23, and the area of the second polysilicon pattern originally covered by the auxiliary pattern 24a is not covered. In this embodiment, the first electrode covers the first portion 111a of the first polysilicon pattern. The second electrode covers the second polysilicon pattern first portion 211 a.
In step 150, referring to fig. 7, the first polysilicon pattern and the second polysilicon pattern are lightly doped to obtain a first polysilicon layer 11 and a second polysilicon layer 21.
The first polysilicon pattern is not covered by the first gate 13 and the region except the high doped region is doped to form a low doped region 112 of the first polysilicon layer 11, and the region covered by the first gate 13 forms a channel region 111 of the first polysilicon layer 11. In this embodiment, the second portion 112a of the first polysilicon pattern 21a is lightly doped to obtain the low-doped region 112 of the first polysilicon layer 21. The region not covered by the second gate 23 and the position where the auxiliary pattern 24a is located are doped to form a low doped region of the second polysilicon layer 21, and the region covered by the second gate 23 forms a channel region 211 of the second polysilicon layer 21. In this embodiment, the second portion 212a and the fourth portion 214a of the second polysilicon pattern are lightly doped to obtain the low-doped region 2121 and the low-doped region 2122 of this embodiment.
Further, step 160 is included, referring back to fig. 1, forming a planarization layer 60 on the gate layer and the gate insulating layer not covered by the gate layer, and forming a pixel electrode 80 and a signal trace 70 on the planarization layer 60, electrically connecting the pixel electrode 80 to the highly doped region 113 on one side of the channel region 111 of the first polysilicon layer 11 through a via hole, and electrically connecting the signal trace 70 to the highly doped region 113 of the first polysilicon layer not electrically connected to the pixel electrode, and electrically connecting the highly doped region 2132 of the second polysilicon layer 21, which is far away from the channel region 211, on two sides of the channel region 211.
Specifically, a planarization layer 60 and a pixel electrode material layer are sequentially formed on the gate electrode layer and the gate insulating layer not covered by the gate electrode layer; and patterning the pixel electrode material layer to obtain a pixel electrode layer. The pixel electrode layer includes a plurality of pixel electrodes 80 disposed at intervals, and the pixel electrodes 80 are connected to the highly doped regions 113 of the first polysilicon layer 11 through via holes. Further, a signal routing layer is formed on the planarization layer 60, and the signal routing layer is patterned to obtain a plurality of signal routing lines 70, where the signal routing lines 70 are electrically connected to the highly doped region 113 of the first polysilicon layer 11, which is not electrically connected to the pixel electrode 80, through vias, and one highly doped region 2132 of the second polysilicon layer 21, which is far away from the channel region 211, on both sides of the channel region 211.
According to the manufacturing method of the array substrate 100, the grid electrode layer is obtained by etching the grid electrode material layer twice, and the polycrystalline silicon material layer is subjected to ion doping twice, so that the polycrystalline silicon layers corresponding to low-doped regions with different lengths of different thin film transistors are obtained under the condition that no photomask is added. Specifically, in the present invention, the low-doped region of the second polysilicon layer 21 includes a low-doped region 2122 corresponding to the auxiliary pattern 24a, and a low-doped region 2123 corresponding to a portion of the second gate pattern etched away to form the second gate 23; and the low doped region of the first polysilicon layer 11 includes only the corresponding low doped region 112 of the portion etched away by the first gate pattern forming the first gate 13. In addition, when the second etching is performed, the first gate pattern and the second gate pattern are etched simultaneously by the same method for the same etching time, so that the etched portions of the first gate pattern and the second gate pattern have the same size, that is, the length of the low-doped region 2123 is the same as that of the low-doped region 112. Therefore, the total length of the lowly doped region of the second polysilicon layer 23 of the present invention (the sum of the lengths of the lowly doped regions 2123 and 2122) is greater than the total length of the lowly doped region 112 of the first polysilicon layer. The low-doped regions with different lengths corresponding to different thin film transistors can be obtained under the condition of not increasing the number of photomasks. Further, since the first gate pattern is etched at the same time, the first polysilicon layer 11 and the second polysilicon layer 21 having different total lengths of the lowly doped regions can be obtained at the same time by the method of the present application. In addition, the total length of the lowly doped region of the second polysilicon layer 21 can be adjusted by adjusting the length of the auxiliary pattern 24a without adding additional operations. In addition, in the present invention, by simultaneously etching the first gate pattern and the second gate pattern by the same method, when the low-doped layers of the first polysilicon layer 11 and the second polysilicon layer 21 of the present invention are obtained by doping, compared to the manner of obtaining the high-doped region and the low-doped region through the mask in the prior art, since there is a certain distance between the mask and the polysilicon layer, it is difficult to truly realize bilateral symmetry between the high-doped region and the low-doped region on both sides of the channel layer when performing ion doping. And the application does not need to use a photomask, so that the bilateral symmetry of the high-doped region and the low-doped region on the two sides of the channel layer can be better realized.
The foregoing is directed to the preferred embodiment of the present invention, and it is understood that various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
providing a substrate, forming a polycrystalline silicon material layer on the substrate, and patterning the polycrystalline silicon material layer to obtain a polycrystalline silicon pattern layer; the polycrystalline silicon pattern layer comprises a first polycrystalline silicon pattern and a second polycrystalline silicon pattern;
sequentially forming a grid insulation layer and a grid material layer on the polycrystalline silicon pattern layer, and patterning the grid material layer through a second photomask to obtain a grid pattern layer; the grid pattern layer comprises a first grid pattern, a second grid pattern and one or more auxiliary patterns which are arranged at intervals and positioned on at least one side of the second grid pattern, the auxiliary patterns and the second grid pattern are arranged at intervals, and the first grid pattern and the second grid pattern respectively comprise a first part and second parts positioned on two sides of the first part; the first grid pattern is laminated on the first polysilicon pattern and partially covers the first polysilicon pattern in the direction vertical to the substrate; the second grid pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in the direction vertical to the substrate;
heavily doping the polysilicon pattern layer from one side of the gate pattern layer, wherein the region of the first polysilicon pattern not covered by the first gate pattern is doped to form a highly doped region; the region of the second polysilicon pattern which is not covered by the second grid pattern and the auxiliary pattern is doped to form a high-doped region;
etching the gate pattern layer to etch away the auxiliary pattern, etching away a second portion of the first gate pattern to obtain a first gate, and etching away a second portion of the second gate pattern to obtain a second gate, wherein the first gate and the second gate are both located on the gate layer;
lightly doping the polysilicon pattern layer from one side of the gate layer so as to form a low-doped region of the first polysilicon pattern in a region corresponding to the second part of the first gate pattern, and form a low-doped region of the second polysilicon pattern in a region corresponding to the second part of the second gate pattern and a region covered by the auxiliary pattern; the region corresponding to the first grid electrode forms the channel region of the first polysilicon pattern, and the region corresponding to the second grid electrode forms the channel region of the second polysilicon pattern.
2. The method for manufacturing an array substrate according to claim 1, wherein the step of obtaining the first polysilicon pattern and the second polysilicon pattern further comprises the steps of:
and forming a flat layer on the gate layer and the gate insulating layer which is not covered by the gate layer, forming a pixel electrode and a signal wire on the flat layer, electrically connecting the pixel electrode with the high-doping area on one side of the channel area of the first polysilicon pattern through a via hole, and electrically connecting the signal wire with the high-doping area of the first polysilicon pattern which is not electrically connected with the pixel electrode, and electrically connecting the two sides of the channel area of the second polysilicon pattern far away from the high-doping area of the channel area.
3. The method for fabricating an array substrate according to claim 1, further comprising, before forming the polysilicon material layer on the substrate, the steps of:
and forming a buffer layer on the substrate, wherein the buffer layer is positioned between the substrate and the polycrystalline silicon material layer.
4. The method for fabricating an array substrate according to claim 3, further comprising, before forming the buffer layer on the substrate, the steps of:
and forming a shading material layer on the substrate, patterning the shading material layer to obtain a shading layer, wherein the shading layer comprises a plurality of shading areas arranged at intervals in an array mode, and the orthographic projection of each shading area on the polycrystalline silicon material layer covers the channel area of the first polycrystalline silicon pattern.
5. The method of claim 1, wherein the heavily and lightly doping are performed by GE self-aligned and ion doping to obtain the highly and lightly doped regions.
6. An array substrate is characterized by comprising a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first polycrystalline silicon layer, and the second thin film transistor comprises a second polycrystalline silicon layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer are positioned on the same layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer respectively comprise a channel region, a low-doped region and a high-doped region, and the low-doped region and the high-doped region are arranged on two sides of the channel region; the two sides of the channel region of the first polycrystalline silicon layer respectively comprise a low-doped region and a high-doped region, and the low-doped region is positioned between the channel region and the high-doped region; at least one side of the channel region of the second polycrystalline silicon layer comprises at least two low-doped regions and at least two high-doped regions, the high-doped regions and the low-doped regions are alternately arranged, and the low-doped regions are close to the channel region relative to the high-doped regions; the length of the low-doped region of the first polysilicon layer is the same as the length of one of the at least two low-doped regions of the second polysilicon layer that is close to the channel region.
7. The array substrate of claim 6, wherein a first gate insulating layer and a first gate are sequentially stacked on the first polysilicon layer; a second grid electrode insulating layer and a second grid electrode are sequentially laminated on the second polycrystalline silicon layer; the first grid electrode insulating layer and the second grid electrode insulating layer are positioned on the same layer and connected; the first grid and the second grid are positioned on the same layer and are arranged at intervals; the projection of the first grid electrode on the first polycrystalline silicon layer covers the channel region of the first polycrystalline silicon layer; the projection of the second grid electrode on the second polycrystalline silicon layer covers the channel region of the second polycrystalline silicon layer.
8. The array substrate of claim 6 or 7, wherein the first polysilicon layer and/or the second polysilicon layer is a U-shaped polysilicon layer or a block-shaped polysilicon layer.
9. The array substrate of claim 6, wherein the low doped region and the high doped region are symmetrically disposed on both sides of the channel region of the first thin film transistor and the second thin film transistor.
10. A display panel comprising the array substrate according to any one of claims 6 to 9.
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| JP4422919B2 (en) * | 2001-02-05 | 2010-03-03 | シャープ株式会社 | Substrate for liquid crystal display device and liquid crystal display device including the same |
| CN100358157C (en) * | 2003-10-28 | 2007-12-26 | 统宝光电股份有限公司 | Thin film transistor and its manufacturing method |
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| CN103996716B (en) * | 2014-04-25 | 2017-02-15 | 京东方科技集团股份有限公司 | Preparation method of poly-silicon thin film transistor and thereof |
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| CN107275340A (en) * | 2017-05-24 | 2017-10-20 | 厦门天马微电子有限公司 | Film crystal tube preparation method, array base palte, its preparation method and display device |
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