CN108807422A - Array substrate manufacturing method and array substrate, display panel - Google Patents
Array substrate manufacturing method and array substrate, display panel Download PDFInfo
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- CN108807422A CN108807422A CN201810605946.9A CN201810605946A CN108807422A CN 108807422 A CN108807422 A CN 108807422A CN 201810605946 A CN201810605946 A CN 201810605946A CN 108807422 A CN108807422 A CN 108807422A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
A kind of array substrate of present invention offer and preparation method thereof and a kind of display panel.Grid layer is obtained by carrying out etching twice to the gate material layers, and ion doping twice is carried out to the polysilicon material layer, with in the case where not increasing light shield, the polysilicon layer of the doped regions of the different length corresponding to different thin film transistor (TFT)s is obtained, to reduce the cost of manufacture of the array substrate and the display panel.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of array substrate manufacturing methods and array substrate, display surface
Plate.
Background technology
It is high-resolution to be widely used in small-medium size due to there is higher carrier mobility for polysilicon array substrate
In liquid crystal display panel (LCD) or organic light emitting display panel (OLED).
In traditional polysilicon array substrate, in order to effectively improve the reliable of the TFT devices in polysilicon array substrate
Property, to reduce the horizontally or laterally electric field of TFT devices caused by hot carrier's effect, and reduce under the conditions of negative bias because of mistake
Such as Crosstalk, flicker, contrast optics caused by big leakage current show bad that the preparation of TFT devices is usually adopted
The LDD region domain (MASK LDD) of low-doped high impedance, effect etc. are formed with one of NP IMP MASK and GE self-aligned technology
Effect is in the upper big resistance of raceway groove both ends series connection.Polysilicon array substrate includes being used there are many different thin film transistor (TFT)s (TFT)
In the different function of realization.For different thin film transistor (TFT)s, the corresponding length of the doped regions of polysilicon layer is different.It is existing
Have in technology, generally the polysilicon layer is patterned by one of light shield, obtains corresponding to different thin film transistor (TFT)s
Different length doped regions.But the processing procedure can increase by one of light shield, to increase being manufactured into for the array substrate
This.
Invention content
A kind of array substrate manufacturing method of present invention offer and array substrate, and include the display surface of the array substrate
Plate need not increase light shield while the doped regions for obtaining different length, to reduce being manufactured into for the array substrate
This.
The array substrate manufacturing method includes step：
One substrate is provided, forms polysilicon material layer on the substrate, the polysilicon material layer is patterned,
Obtain poly-silicon pattern layer；The poly-silicon pattern layer includes the first poly-silicon pattern and the second poly-silicon pattern；
Gate insulating layer and gate material layers are sequentially formed on the poly-silicon pattern layer, pass through second mask pattern
Change the gate material layers, obtains gate pattern layer；The gate pattern layer includes first grid pattern, second grid pattern,
And the spaced auxiliary patterns of one or more positioned at at least side of the second grid pattern, the first grid
Pattern and the second grid pattern include first part and the second part positioned at the first part both sides；Described first
Gate pattern is laminated on first poly-silicon pattern, and is partly being covered more than described first on the orientation substrate
Crystal silicon pattern；The second grid pattern and the auxiliary patterns are laminated on second poly-silicon pattern, and perpendicular to
Second poly-silicon pattern is partly covered on the orientation substrate；
Heavy doping is carried out to the poly-silicon pattern layer from gate pattern layer side, first poly-silicon pattern is not
High-doped zone is formed by the region doping of the first grid pattern covers；The second poly-silicon pattern layer is not by described second
Gate pattern and the region doping of auxiliary patterns covering form high-doped zone；
The gate pattern layer is performed etching, to etch away the auxiliary patterns, and by the first grid pattern
Second part is etched away to obtain first grid, and the second part of the second grid pattern is etched away to obtain second gate
Pole, the first grid and the second grid are respectively positioned on grid layer；
The poly-silicon pattern layer is lightly doped from the grid layer side, by the of the first grid pattern
The corresponding region in two parts forms the doped regions of first poly-silicon pattern, by the second part of the second grid pattern
Corresponding region and the region of auxiliary patterns covering form the doped regions of second poly-silicon pattern；The first grid
Extremely corresponding region forms the channel region of first poly-silicon pattern, and the corresponding region of the second grid forms described second
The channel region of poly-silicon pattern.
Wherein, it obtains after the first poly-silicon pattern and the second poly-silicon pattern further including step：
In the grid layer and flatness layer is not formed on the gate insulating layer of grid layer covering, and on the flatness layer
Pixel electrode and signal lead are formed, the pixel electrode is passed through into the channel region side of via and first poly-silicon pattern
High-doped zone electrical connection, and by the highly doped of the signal lead and the first poly-silicon pattern for not being electrically connected the pixel electrode
The high-doped zone electrical connection of miscellaneous area and the channel region both sides of second polysilicon layer far from the channel region.
Wherein, further include step before forming polysilicon material layer on the substrate：
Buffer layer is formed on the substrate, and the buffer layer is between the substrate and polysilicon material layer.
Wherein, further include step before forming buffer layer on the substrate：
Light-shielding material layers are formed on the substrate, are patterned the light-shielding material layers and are obtained light shield layer, the light shield layer
Include the shading region of multiple spaced arrays setting, orthographic projection of each shading region on the polysilicon material layer covers institute
State the channel region of the first poly-silicon pattern.
Wherein, by GE self-aligned technologies and ion doping technique to carry out the heavy doping and it is described be lightly doped, with
To the high-doped zone and doped regions.
The array substrate includes the first film crystal and the second thin film transistor (TFT)；The first film transistor includes the
One polysilicon layer, second thin film transistor (TFT) include the second polysilicon layer；First polysilicon layer and second polycrystalline
Silicon layer is located at same layer；First polysilicon layer and the second polysilicon layer include channel region, doped regions and high-doped zone,
The both sides of the channel region are equipped with the doped regions and the high-doped zone；The two of the channel region of first polysilicon layer
Side includes a doped regions and a high-doped zone, and the doped regions are between the channel region and the high-doped zone；
At least side of the channel region of second polysilicon layer includes at least two doped regions and at least two high-doped zones,
The high-doped zone is arranged alternately with the doped regions, and the relatively described high-doped zone in the doped regions is close to the raceway groove
Area；Described at least two of the length of the doped regions of first polysilicon layer and second polysilicon layer are low-doped
The length of the doped regions in area close to the channel region is identical.
Wherein, first grid insulating layer, first grid are sequentially laminated on first polysilicon layer；Second polycrystalline
Second grid insulating layer, second grid are sequentially laminated on silicon layer；The first grid insulating layer and second grid insulating layer position
In same layer and connect；The first grid is located at same layer and is spaced setting with the second grid；The first grid exists
The projection perpendicular to first polysilicon layer on first polysilicon layer covers the first grid；The second grid
The projection perpendicular to second polysilicon layer on second polysilicon layer covers the second grid.
Wherein, first polysilicon layer and/or second polysilicon layer are U-shaped polysilicon layer or box-shaped polycrystalline
Silicon layer.
Wherein, the doped regions of the channel region both sides of the first film transistor and second thin film transistor (TFT)
And the high-doped zone is symmetrical arranged.
The display panel includes the array substrate.
The present invention obtains grid layer by carrying out etching twice to the gate material layers, and to the polysilicon material layer
Ion doping twice is carried out, in the case where not increasing light shield, to obtain the different length corresponding to different thin film transistor (TFT)s
Doped regions the polysilicon layer.Specifically, due in the present invention, the doped regions of second polysilicon layer are wrapped
It includes the corresponding region of the auxiliary patterns and part that the second grid pattern forms the second grid and etches away is right
The region answered；And the doped regions of first polysilicon layer only form the first grid including the first grid pattern and
The corresponding region in part etched away.Also, when being etched due to carrying out second, to the first grid pattern and described second
The etching period of grid is identical, to the size for the part that the first grid pattern and the second grid pattern are etched
Identical, therefore, the length of the doped regions of second polysilicon layer of the invention is more than first polysilicon layer
The doped regions length.To realize in the case where not increasing light shield, obtain corresponding to different thin film transistor (TFT)s
Different length doped regions.
Description of the drawings
For more clearly illustrate the present invention construction feature and effect, come below in conjunction with the accompanying drawings with specific embodiment to its into
Row is described in detail.
Fig. 1 is the schematic cross-section of the array substrate of the embodiment of the present invention；
Fig. 2 is the production flow diagram of the array substrate of the embodiment of the present invention；
Fig. 3-Fig. 7 is the sectional view of each step of the production process of the array substrate of the embodiment of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.Wherein, the drawings are for illustrative purposes only and are merely schematic diagrams, should not be understood as the limitation to this patent.
The present invention provides a kind of display panel, is shown for carrying out picture.The display panel can be LCD display
Plate (LCD display panel) or LED display panel (OLED display panel).The display panel includes array substrate.
Also, when the display panel is liquid crystal display panel, the display panel further includes the coloured silk opposite with the array substrate
Ilm substrate, and the liquid crystal layer between the array substrate and color membrane substrates；When the display panel is light emitting diode
When display panel, the display panel further includes the luminescent layer and cathode layer being set in array substrate.
The array substrate includes viewing area and the non-display area around the viewing area.The array substrate includes a variety of
Different foamed film transistors.For example, a variety of different thin film transistor (TFT)s include being located at viewing area for control picture
The luminous thin film transistor (TFT) of plain unit divides positioned at the non-display electrostatic protection thin film transistor (TFT) (ESD TFT) for showing area and polygamy
Solve device thin film transistor (TFT) (demux TFT) etc..Wherein, since the size and function of the different thin film transistor (TFT)s are different, because
And the length of the doped regions (LDD) of the different thin film transistor (TFT)s is different, with the reduction of the adaptability film crystal
The hot carrier's effect of pipe, to improve the reliability of the thin film transistor (TFT).The display panel is avoided crosstalk occur
(crosstalk), the bad problem of optics such as flicker (flicker).The present invention obtains different in the case where not increasing light shield
The doped regions (LDD) of the corresponding different length of the thin film transistor (TFT).For example, the electrostatic protection thin film transistor (TFT) is low
The length of doped region is generally 2-3 times of the length of the doped regions of the thin film transistor (TFT) positioned at viewing area.Below to be located at
That states viewing area is used to control the luminous thin film transistor (TFT) of pixel unit and positioned at the non-display electrostatic protection film crystalline substance for showing area
It is illustrated for body pipe.
Referring to Fig. 1, the application provides a kind of array substrate 100.The array substrate 100 includes the first film crystal 10
And second thin film transistor (TFT) 20.In the present embodiment, the first film pipe is the thin film transistor (TFT) in viewing area；Described
Two thin film transistor (TFT)s 20 are the electrostatic protection thin film transistor (TFT) in non-display area.The first film transistor 10 include according to
The first polysilicon layer 11, first grid insulating layer 12 and the first grid 13 of secondary stacking.Second thin film transistor (TFT) 20 includes
The second polysilicon layer 21, second grid insulating layer 22 and the second grid 23 stacked gradually.First polysilicon layer 11 and institute
It states the second polysilicon layer 21 to be located at same layer and be spaced setting, first polysilicon layer 11 and second polysilicon layer, 21 institute
It is polysilicon layer in layer；The first grid insulating layer 12 is located at same layer with the second grid insulating layer 22 and connect, institute
It is gate insulating layer that first grid insulating layer 12, which is stated, with the layer where the second grid insulating layer 22；The first grid 13 with
The second grid 23 is located at same layer and spacer insulator setting.First polysilicon layer 11 and second polysilicon layer 21
Can be U-shaped polysilicon layer, square polysilicon layer or other shapes of polysilicon layer.Wherein, the U-shaped polysilicon layer can
The square polysilicon layer is bent to obtain to be equivalent to.The present invention is with first polysilicon layer 11 and second polycrystalline
Silicon layer 21 be square polysilicon layer for illustrate.
First polysilicon layer 11 includes channel region 111, doped regions 112 and high-doped zone 113.First polycrystalline
The both sides of the channel region 111 of silicon layer 11 include the doped regions 112 and a high-doped zone 113, and institute
Doped regions 112 are stated between the channel region 111 and the high-doped zone 113.The first grid 13 is described first
The projection perpendicular to first polysilicon layer 11 on polysilicon layer 11 covers the channel region 111.Second crystal silicon layer
Including channel region 211, doped regions 212 and high-doped zone 213.At least side of the channel region 211 includes at least two institutes
Doped regions 212 and at least two high-doped zones 213 are stated, the high-doped zone 213 replaces with the doped regions 212 to be set
It sets, and the high-doped zone 213 relatively of the doped regions 212 is close to the channel region 211.The second grid 23 is described
The projection perpendicular to second polysilicon layer 21 on second polysilicon layer 21 covers the channel region 211.In the present embodiment,
The both sides of the channel region 211 are all provided with there are two doped regions 212 and two high-doped zones 213, and two low-mixs
Miscellaneous area 212 is arranged alternately with two high-doped zones 213.In the present embodiment, the channel region 111 and the channel region 211
The doped regions of both sides and high-doped zone are symmetrical.In the present embodiment, two of the both sides of the channel region 211 are low-doped
Area 212 is respectively the first doped regions 2121 and the second doped regions 2122；Two of the both sides of the channel region 211 are highly doped
Area 213 is respectively the first high-doped zone 2131 and the second high-doped zone 2132.First doped regions 2121, first are highly doped
Area 2131, the second doped regions 2122, the second high-doped zone 2132 are from the channel region 211 to away from the channel region 211
Direction extends, i.e., described first doped regions 2121 are near the channel region 211, and the second high-doped zone 2132 is farthest away from described
Channel region 211.In the present invention, the doped regions 112 of first polysilicon layer 11 and second polysilicon layer 21
Length at least two doped regions 212 close to the doped regions 212 of the channel region 211 is identical.This implementation
In example, described the first of the doped regions 112 of first polysilicon layer 11 and second polysilicon layer 21 is low-doped
The length in area 2121 is identical.Wherein, the direction of the length refers to the direction extended from channel region to doped region.The present invention is another
In embodiment, two doped regions and two high-doped zones that the side of the channel region has, there are one low-mixs for other side tool
Za Qu and high-doped zone.
In the present invention, due to the doped regions 112 and second polysilicon layer 21 of first polysilicon layer 11
First doped regions 2121 length it is identical, and the doped regions 212 of second polysilicon layer 21 further include second
Doped regions 2122, therefore, the total length of the doped regions 212 of second thin film transistor (TFT) 2021 of the application is compared with institute
The total length for stating the doped regions 112 of first film transistor 1011 is long, meets the needs of actual use.
Further, the second of the first grid 13 of the first film transistor 10 and second thin film transistor (TFT) 20
Flatness layer 60 is laminated on grid 23.The flatness layer is equipped with the signal lead (SD cablings) 70 of a plurality of spacer insulator setting
And pixel electrode 80.Wherein, the pixel electrode 80 is located at the viewing area, and with the ditch of the first film transistor 10
One high-doped zone 113 of channel layer side is electrically connected by via.Being not connected with for the first film transistor 10 is described
One high-doped zone 113 of pixel electrode 80 is electrically connected by via and a signal lead 70.Second film
The high-doped zone of the transistor 20 far from the channel region 211 is electrically connected with a signal lead 70.The present embodiment
In, second high-doped zone 2132 of second thin film transistor (TFT) 20 is electrically connected with a signal lead 70.Pass through institute
It is 20 transmission data signal of the first film transistor 10 and the second thin film transistor (TFT) to state signal lead 70.
Further, the array substrate 100 in the present invention further includes substrate 30, the first film transistor 10 and
Second thin film transistor (TFT) 20 is formed on the substrate 30.The substrate 30 can be rigid substrates or flexible base board.
For example, when needing to obtain rigid LCD display panel or OLED display panel, the substrate 30 is the glass base of rigidity
Plate；When display panel flexible (such as AMOLED panel) for needing to obtain, the substrate 30 can be flexible plastic substrates.This
In embodiment, the substrate 30 is glass substrate.
Further, in some embodiments of the invention, light shield layer 40 and buffer layer are also sequentially laminated on the substrate 30
50.The light shield layer 40 is located at the viewing area, includes the shading region of multiple spaced arrays setting.Each shading region is in institute
The channel region that the orthographic projection on the first polysilicon layer 11 covers first polysilicon layer 11 is stated, for avoiding light from exposing to institute
The channel region 111 for stating the first polysilicon layer 11, avoids the channel region 111 from being damaged due to illumination.The buffer layer 50
Positioned at the light shield layer 40 and the first film transistor 10 and the first polysilicon layer 11 of second thin film transistor (TFT) 20
Between second polysilicon layer 21, to ensure that first polysilicon layer 11 and second polysilicon layer 21 can be with
The substrate 30 is by preferably combining.
Referring to Fig. 2, the present invention also provides a kind of 100 production method of array substrate, the array base is obtained for making
Plate 100.Patterning of the present invention includes each processing step such as being exposed, developing, etching by a light shield.Specifically, this
100 production method of the array substrate of application includes step：
Step 110, referring to Fig. 3, providing a substrate 30, polysilicon material layer is formed on the substrate 30, to described
Polysilicon material layer is patterned, and poly-silicon pattern layer is obtained.The poly-silicon pattern layer includes the first poly-silicon pattern 11a
And the second poly-silicon pattern 21a.
In the present embodiment, the first poly-silicon pattern 11a include first part 111a and be located at the first part
The second part 112a of the both sides 111a and the third for deviating from the sides the first part 111a positioned at the second part 112a
Part 113a.The second poly-silicon pattern 21a include first part 211a and positioned at the both sides the first part 211a
Two part 212a, and deviate from the Part III that the sides the first part 211a are set gradually from the second part 212a
213a, Part IV 214a and Part V 215a.
In some embodiments of the invention, on the substrate 30 formed polysilicon material layer before further include step 111：Institute
State formation buffer layer 50 on substrate 30.The buffer layer 50 is between the substrate 30 and polysilicon material layer.In the present invention
Further include step 112 before forming buffer layer 50 on the substrate 30 in other embodiments：It is formed and is hidden on the substrate 30
Optical material layer patterns the light-shielding material layers and obtains light shield layer 40, and the light shield layer 40 includes the setting of multiple spaced arrays
Shading region.The buffer layer 50 covers the light shield layer 40.
Step 120, referring to Fig. 4, sequentially forming gate insulating layer and gate material layers on the poly-silicon pattern layer.
The gate material layers are patterned, gate pattern layer is obtained.
The gate insulating layer includes first grid insulating layer 12 and second grid insulating layer 22.The first grid insulation
Layer 21 is laminated in the top of the first poly-silicon pattern 11a；The first grid insulating layer 22 is laminated in first polycrystalline
The top of silicon pattern 21a.The gate pattern layer includes first grid pattern 13a, second grid pattern 23a and one or more
A spaced auxiliary patterns 24a, one or more of auxiliary patterns 24a are located at the second gate pole figure towards case 23a
At least side.The first grid pattern 13a, second grid pattern 23a and the auxiliary patterns 24a are spaced setting.Institute
First grid pattern 13a and the second grid pattern 23a are stated including first part and positioned at the first part both sides
Second part.The first grid pattern 13a is laminated on the first poly-silicon pattern 21a, and perpendicular to the substrate
The first poly-silicon pattern 21a is partly covered on 30 direction.In the present embodiment, the first grid pattern 13a is vertical
In the first part 111a and second part 112a that cover first poly-silicon pattern on 30 direction of the substrate.Specifically,
The first part of the first grid pattern 13a is corresponding with the first part 111a of the first poly-silicon pattern, second part with
The second part 112a of first poly-silicon pattern is corresponding.The second grid pattern and the auxiliary patterns are laminated in described
On two poly-silicon patterns, and second poly-silicon pattern is partly being covered on the orientation substrate.In the present embodiment,
The second grid pattern 23a is in the first part for covering second poly-silicon pattern on 30 direction of the substrate
211a and second part 212a.The auxiliary patterns 24a covers the Part IV 214a of second poly-silicon pattern.Tool
Body, the first part of the second grid pattern is corresponding with the first part 211 of the second poly-silicon pattern, and described
The second part of two gate patterns is corresponding with the second part second part 212a of the second poly-silicon pattern.
Step 130, referring to Fig. 5, carrying out heavy doping to the polysilicon material layer from the gate pattern layer, described the
Region dopings of the one poly-silicon pattern 11a not by first grid pattern 13a coverings forms high-doped zone；Second polycrystalline
Silicon pattern 21a does not form high-doped zone by the region doping of the second grid pattern 23a and auxiliary patterns 24a coverings.
In the present invention, by grid self-aligned technology (GE self-aligned technologies) and ion heavy doping technology from the grid
Pattern layer carries out heavy doping to the polysilicon material layer.In the present embodiment, it is N to carry out heavy doping in the polysilicon material layer
Type ion.Specifically, the N-type ion of the present embodiment is phosphonium ion.Specifically, from the gate pattern layer to the polycrystalline
When silicon material layer carries out heavy doping, the N-type ion cannot pass through the gate pattern layer and diffuse to the polycrystalline silicon material
Layer, therefore, the position of gate pattern layer covering are undoped, and not by the position of gate pattern layer covering then by
Doping forms heavily doped region.In the present embodiment, the Part III 113a of the first poly-silicon pattern 11a carries out ion weight
It is doped to form the heavily doped region.The heavily doped region of the first poly-silicon pattern 11a is described in the present embodiment
The high-doped zone 113 of first polysilicon layer 11；The Part III 213a and Part V of the second poly-silicon pattern 21a
It is to form the heavily doped region that 215a, which carries out ion heavy doping, and the heavily doped region that the Part III 213a heavy doping obtains is
First high-doped zone 2131 of second polysilicon layer 21 of the present embodiment, the Part V 215a carry out ion heavy doping
Obtained high-doped zone is second high-doped zone 2132 of second polysilicon layer 21 of the present embodiment.
Step 140, referring to Fig. 6, further etching obtains grid layer to the gate pattern layer, the grid layer includes
First grid 13 and second grid 23.When etching the gate pattern layer and obtaining the grid layer, the auxiliary patterns 24a is carved
Eating away etches the first grid pattern 13a to obtain first grid 13, and the second grid pattern 23a is etched to obtain
Two grids 23.
Specifically, by carrying out wet etching or dry etching to the gate pattern layer, it is described auxiliary to remove simultaneously
Pattern 24a is helped, and by the first grid pattern 13a partial etchings to obtain the first grid 13, by the second grid
Pattern 23a partial etchings are to obtain second grid 23.When etching, due to the first grid pattern 13a and the second gate
It is etched while pole figure case 23a, so that the portion that the first grid pattern 13a is etched away with the gate pattern
Divide size identical.The first grid 13 and the second grid 23 obtained after being performed etching to the gate pattern layer is compared
Reduce in the size of the first grid pattern 13a and the second grid pattern 23a so that original is by the first grid pattern
The region of first poly-silicon pattern of 13a coverings is different all to be covered by the first grid 13, and original is by described second
The region of second poly-silicon pattern of gate pattern 23a coverings is not covered by the second grid 23 all, and original is by institute
The region for stating the second poly-silicon pattern of auxiliary patterns 24a coverings is also uncovered.In the present embodiment, the first electrode covering
The first part 111a of first poly-silicon pattern.The second electrode covers second poly-silicon pattern first part
211a。
Step 150, referring to Fig. 7, first poly-silicon pattern and the second poly-silicon pattern are lightly doped, with
To the first polysilicon layer 11 and the second polysilicon layer 21.
First poly-silicon pattern is not covered by the first grid 13 and the region doping in addition to the high-doped zone
The doped regions 112 of first polysilicon layer 11 are formed, the region that the first grid 13 covers forms first polycrystalline
The channel region 111 of silicon layer 11.In the present embodiment, the second part 112a of the first poly-silicon pattern 21a is lightly doped to obtain institute
State the doped regions 112 of the first polysilicon layer 21.The region not covered by the second grid 23 and the auxiliary patterns
Adulterate the doped regions to form second polysilicon layer 21, the region shape that the second grid 23 covers in position where 24a
At the channel region 211 of second polysilicon layer 21.In the present embodiment, the second part 212a of second poly-silicon pattern and
Part IV 214a is lightly doped to obtain the doped regions 2121 of the present embodiment and doped regions 2122.
Further, further include step 160, please again refering to fig. 1, the grid not covered in the grid layer and by grid layer
Flatness layer 60 is formed on the insulating layer of pole, and forms pixel electrode 80 and signal lead 70 on the flatness layer 60, by the picture
Plain electrode 80 is electrically connected by via with the high-doped zone 113 of 111 side of channel region of first polysilicon layer 11, and by institute
State the high-doped zone 113 and described more than second of signal lead 70 and the first polysilicon layer for not being electrically connected the pixel electrode
High-doped zone 2132 of 211 both sides of channel region of crystal silicon layer 21 far from the channel region 211 is electrically connected.
Specifically, in the grid layer and not sequentially formed flatness layer 60 and picture on the gate insulating layer of grid layer covering
Plain electrode material layer；It patterns the pixel electrode material layer and obtains pixel electrode layer.The pixel electrode layer includes multiple
Every the pixel electrode 80 of setting, the pixel electrode 80 is connected by the high-doped zone 113 of via and first polysilicon layer 11
It connects.Further, signal lead layer is formed on the flatness layer 60, and it is a plurality of to obtain to pattern the signal lead layer
Signal lead 70, the signal lead 70 are not electrically connected with pixel electrode 80 by via and first polysilicon layer 11
The high-doped zone of high-doped zone 113 and 211 both sides of channel region of the second polysilicon layer 21 far from the channel region 211
2132 electrical connections.
The production method of the array substrate 100 of the present invention, by being etched twice to the gate material layers
Ion doping twice is carried out to grid layer, and to the polysilicon material layer, in the case where not increasing light shield, to be corresponded to
The polysilicon layer in the doped regions of the different length of different thin film transistor (TFT)s.Specifically, due in the present invention, it is described
The doped regions of second polysilicon layer 21 include the corresponding doped regions 2122 the auxiliary patterns 24a and described
Two gate patterns form the second grid 23 and the corresponding doped regions in the part that etches away 2123；And first polysilicon
The part that the doped regions of layer 11 only form the first grid 13 and etch away including the first grid pattern is corresponding low
Doped region 112.Also, when being etched due to carrying out second, by passing through to the first grid pattern and the second grid
Method of the same race etches simultaneously, and etching period is identical, to which the first grid pattern and the second grid pattern are etched
The size for the part fallen is identical, i.e., the described doped regions 2123 are identical as the length of doped regions 112.Therefore, institute of the invention
State the total length (the sum of the length of doped regions 2123 and doped regions 2122) of the doped regions of the second polysilicon layer 23
More than the total length of the doped regions 112 of first polysilicon layer.It can realize in the case where not increasing light shield,
Obtain the doped regions of the different length corresponding to different thin film transistor (TFT)s.Further, since the application by losing simultaneously
Carve the first grid pattern, by the present processes, can obtain simultaneously doped regions total length it is different described first
Polysilicon layer 11 and the second polysilicon layer 21.Also, the length by adjusting the auxiliary patterns 24a can adjust described second
The doped regions total length of polysilicon layer 21, need not increase additional operation, compared to the prior art for, the behaviour of the application
It is simple to make mode, saves Production Time.Also, in the present invention, by logical to the first grid pattern and the second grid
It crosses method of the same race while etching, first polysilicon layer, 11 and second polysilicon layer 21 of the present invention is being obtained by doping
Low doped layer, compared with the existing technology in such a way that light shield obtains high-doped zone and doped regions, the prior art is due to light shield
There is a certain distance between polysilicon layer, when carrying out ion doping, it is difficult to really realize the highly doped of the channel layer both sides
Area and doped regions are symmetrical.And the application is enable to preferably realize the ditch due to that need not use light shield
The high-doped zone and doped regions of channel layer both sides are symmetrical.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (10)
1. a kind of array substrate manufacturing method, which is characterized in that including step：
One substrate is provided, forms polysilicon material layer on the substrate, the polysilicon material layer is patterned, is obtained
Poly-silicon pattern layer；The poly-silicon pattern layer includes the first poly-silicon pattern and the second poly-silicon pattern；
Gate insulating layer and gate material layers are sequentially formed on the poly-silicon pattern layer, pass through the mask patterning institute of second
Gate material layers are stated, gate pattern layer is obtained；The gate pattern layer includes first grid pattern, second grid pattern, and
The spaced auxiliary patterns of one or more positioned at at least side of the second grid pattern, the first grid pattern
And the second grid pattern includes first part and the second part positioned at the first part both sides；The first grid
Pattern is laminated on first poly-silicon pattern, and first polysilicon is partly being covered on the orientation substrate
Pattern；The second grid pattern and the auxiliary patterns are laminated on second poly-silicon pattern, and perpendicular to described
Second poly-silicon pattern is partly covered on orientation substrate；
Heavy doping is carried out to the poly-silicon pattern layer from gate pattern layer side, first poly-silicon pattern is not by institute
The region doping for stating first grid pattern covers forms high-doped zone；The second poly-silicon pattern layer is not by the second grid
Pattern and the region doping of auxiliary patterns covering form high-doped zone；
The gate pattern layer is performed etching, to etch away the auxiliary patterns, and by the second of the first grid pattern
Partial etching falls to obtain first grid, the second part of the second grid pattern is etched away to obtain second grid, institute
It states first grid and the second grid is respectively positioned on grid layer；
The poly-silicon pattern layer is lightly doped from the grid layer side, by second of the first grid pattern
The doped regions for dividing corresponding region to form first poly-silicon pattern correspond to the second part of the second grid pattern
Region and the region of auxiliary patterns covering form the doped regions of second poly-silicon pattern；The first grid pair
The region answered forms the channel region of first poly-silicon pattern, and the corresponding region of the second grid forms second polycrystalline
The channel region of silicon pattern.
2. array substrate manufacturing method as claimed in claim 1, which is characterized in that obtain the first poly-silicon pattern and the second polysilicon
It further include step after pattern：
In the grid layer and flatness layer is not formed on the gate insulating layer of grid layer covering, and is formed on the flatness layer
The pixel electrode is passed through the height of via and the channel region side of first poly-silicon pattern by pixel electrode and signal lead
Doped region is electrically connected, and by the highly doped of the signal lead and the first poly-silicon pattern for not being electrically connected the pixel electrode
The high-doped zone electrical connection of area and the channel region both sides of second polysilicon layer far from the channel region.
3. array substrate manufacturing method as claimed in claim 1, which is characterized in that form polysilicon material layer on the substrate
Before, further include step：
Buffer layer is formed on the substrate, and the buffer layer is between the substrate and polysilicon material layer.
4. array substrate manufacturing method as claimed in claim 3, which is characterized in that before forming buffer layer on the substrate, also wrap
Include step：
Light-shielding material layers are formed on the substrate, are patterned the light-shielding material layers and are obtained light shield layer, the light shield layer includes
The shading region of multiple spaced arrays setting, orthographic projection covering of each shading region on the polysilicon material layer described the
The channel region of one poly-silicon pattern.
5. array substrate manufacturing method as claimed in claim 1, which is characterized in that pass through GE self-aligned technologies and ion doping technique
To carry out the heavy doping and it is described be lightly doped, to obtain the high-doped zone and doped regions.
6. a kind of array substrate, which is characterized in that including the first film crystal and the second thin film transistor (TFT)；The first film is brilliant
Body pipe includes the first polysilicon layer, and second thin film transistor (TFT) includes the second polysilicon layer；First polysilicon layer and institute
It states the second polysilicon layer and is located at same layer；First polysilicon layer and the second polysilicon layer include channel region, doped regions
And high-doped zone, the both sides of the channel region are equipped with the doped regions and the high-doped zone；First polysilicon layer
Channel region both sides include a doped regions and a high-doped zone, the doped regions are located at the channel region and the height
Between doped region；At least side of the channel region of second polysilicon layer includes at least two doped regions and at least two
A high-doped zone, the high-doped zone are arranged alternately with the doped regions, and the relatively described high-doped zone in the doped regions
Close to the channel region；The length of the doped regions of first polysilicon layer and second polysilicon layer it is described extremely
Length in few two doped regions close to the doped regions of the channel region is identical.
7. array substrate as claimed in claim 6, which is characterized in that be sequentially laminated with the first grid on first polysilicon layer
Pole insulating layer, first grid；It is sequentially laminated with second grid insulating layer, second grid on second polysilicon layer；Described
One gate insulating layer is located at same layer with second grid insulating layer and connect；The first grid is located at same with the second grid
One layer and it is spaced setting；Projection perpendicular to first polysilicon layer of the first grid on first polysilicon layer
Cover the first grid；Throwing perpendicular to second polysilicon layer of the second grid on second polysilicon layer
Shadow covers the second grid.
8. array substrate as claimed in claims 6 or 7, which is characterized in that first polysilicon layer and/or described more than second
Crystal silicon layer is U-shaped polysilicon layer or box-shaped polysilicon layer.
9. array substrate as claimed in claim 6, which is characterized in that the first film transistor and second film are brilliant
The doped regions and the high-doped zone of the channel region both sides of body pipe are symmetrical arranged.
10. a kind of display panel, which is characterized in that include the array substrate such as any one of claim 6-9.
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