CN103227150B

CN103227150B - Display panel and manufacturing method thereof

Info

Publication number: CN103227150B
Application number: CN201310178656.8A
Authority: CN
Inventors: 周政伟; 胡晋玮
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2013-03-22
Filing date: 2013-05-15
Publication date: 2015-05-13
Anticipated expiration: 2033-05-15
Also published as: CN103227150A; TWI495111B; TW201438251A

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel of the present invention includes a connection electrode. The connection electrode and the gate of the thin film transistor are formed by the same mask, and the drain of the thin film transistor is electrically connected to the pixel electrode through the connection electrode. Therefore, the connection electrode is not required to be manufactured by an additional process, and the connection electrode can prevent the pixel electrode from being damaged when the dielectric layer is etched. The source doped region and the drain doped region of the thin film transistor, the lower electrode of the storage capacitor and the pixel electrode of the display panel can be formed by using the same gray scale mask.

Description

Display floater and preparation method thereof

[technical field]

System of the present invention about a kind of display floater and preparation method thereof, espespecially a kind of have aim at voluntarily doped region, use doping semiconductor layer as storage capacitors bottom electrode and the display floater and preparation method thereof of drain electrode using switching Electrode connection pixel electrode and thin-film transistor.

[background technology]

Generally speaking, display floater comprises multiple image element structure, and each image element structure comprises the elements such as thin-film transistor, storage capacitors and pixel electrode.In existing display floater, source doping region in the semiconductor layer of thin-film transistor uses different light shields to be defined from drain doping region and grid system, therefore the position of source doping region and drain doping region easily with the position deviation to some extent by grid, and cause the problem of the element characteristic instability of thin-film transistor.In addition, in existing display floater, pixel electrode is easily impaired when the opening of etching dielectric layer, and affects the display quality of display floater.Moreover the method for existing making display floater must use eight road photoetching and etch process, its processing procedure is complicated and cause cost of manufacture significantly to promote.

[summary of the invention]

One of object of the present invention is to provide a kind of display floater and preparation method thereof, to promote element characteristic and the display quality of the thin-film transistor of display floater.

One embodiment of the invention provide a kind of method making display floater, comprise the following steps.There is provided a substrate, substrate has a picture element region and a first film transistor area.On substrate, form a patterned semiconductor layer, patterned semiconductor layer comprises one the one the first semiconductor pattern, is arranged in the first film transistor area.An insulating barrier is formed, wherein insulating barrier coverage diagram patterning semiconductor layer on substrate.On insulating barrier, form one first patterned conductive layer, the first patterned conductive layer comprises a pixel electrode, is arranged in picture element region.On insulating barrier, form one second patterned conductive layer, the second patterned conductive layer comprises a first grid and a switching electrode.First grid is arranged in the first film transistor area, and wherein on a upright projection direction, first grid system partly overlaps the first semiconductor pattern.Switching electrode is arranged in picture element region, wherein the switching electrode of a part contacts with pixel electrode and at this pixel electrode of upright projection direction upper part overlap, and the switching electrode of another part is positioned at the surface of insulating barrier and not overlapping with pixel electrode on upright projection direction.In the first semiconductor pattern underlapped with first grid on upright projection direction, form one first doped region and one second doped region, wherein the first doped region and this second doped region have one first doping type.Form a dielectric layer and cover insulating barrier, pixel electrode and the second patterned conductive layer, and in dielectric layer and insulating barrier, form one first opening expose the first doped region and one second opening exposes the second doped region, and in dielectric layer, form one the 3rd opening expose switching electrode.On dielectric layer, form one the 3rd patterned conductive layer, the 3rd patterned conductive layer comprises one first source electrode and one first drain electrode.First source electrode is inserted the first opening and is electrically connected with the first doped region.First drain electrode is inserted the second opening and is electrically connected and inserts the 3rd opening with the second doped region and is electrically connected with switching electrode.

Another embodiment of the present invention provides a kind of display floater, comprises a substrate, one first semiconductor pattern, an insulating barrier, a pixel electrode, a first grid, a switching electrode, a dielectric layer, one first source electrode and one first drain electrode.Substrate has a picture element region and a first film transistor area.First semiconductor pattern to be arranged on substrate and to be positioned at the first film transistor area, and wherein the first semiconductor pattern has one first doped region and one second doped region, and the first doped region and the second doped region have one first doping type.Insulating barrier to be positioned on substrate and to cover the first semiconductor pattern.Pixel electrode to be arranged on insulating barrier and to be positioned at picture element region.First grid to be arranged on insulating barrier and to be positioned at the first film transistor area, wherein underlapped first doped region of first grid and the second doped region on a upright projection direction.Switching electrode is arranged in picture element region, wherein the switching electrode of a part contacts with pixel electrode and at upright projection direction upper part overlap pixel electrode, and the switching electrode of another part is positioned at the surface of insulating barrier and not overlapping with pixel electrode on upright projection direction.Dielectric layer covers insulating barrier, pixel electrode and first grid, its dielectric layer and insulating barrier have one first opening portion and expose the first doped region and one second opening portion and expose the second doped region, and dielectric layer has one the 3rd opening portion and exposes switching electrode.First source electrode is inserted the first opening and is electrically connected with the first doped region.First drain electrode is inserted the second opening and is electrically connected and inserts the 3rd opening with the second doped region and is electrically connected with switching electrode.

Display floater of the present invention and preparation method thereof has following advantages.The source doping region of the thin-film transistor of display floater can utilize with drain doping region, storage capacitors bottom electrode and pixel electrode and be formed with gray-level mask.The bottom electrode of the storage capacitors of display floater and top electrode can respectively with the semiconductor layer of thin-film transistor and the process integration of grid, therefore do not need to increase additional process.In addition, the lower electrode of storage capacitors is doped semiconductor electrode, therefore can have preferably capacitance.Display floater has the connecting electrode jointly formed with the grid of thin-film transistor, and the drain electrode system of thin-film transistor is electrically connected via connecting electrode and pixel electrode, therefore connecting electrode does not need to utilize additional process to be made, and this practice can avoid pixel electrode to sustain damage when etching dielectric layer.

[accompanying drawing explanation]

Fig. 1 to Figure 10 depicts the method schematic diagram of the making display floater of the first embodiment of the present invention.

Figure 11 depicts the method schematic diagram of the making display floater of the alternate embodiment of the first embodiment of the present invention.

Figure 12 to Figure 20 depicts the method schematic diagram of the making display floater of the second embodiment of the present invention.

Figure 21 depicts the method schematic diagram of the making display floater of the alternate embodiment of the second embodiment of the present invention.

Figure 22 to Figure 25 depicts the method schematic diagram of the making display floater of the third embodiment of the present invention.

Figure 26 depicts the method schematic diagram of the making display floater of the alternate embodiment of the third embodiment of the present invention.

[symbol description]

10 substrates

10P picture element region

101 the first film transistor area

102 second thin film transistor regions

10C storage capacitors district

12 patterned semiconductor layer

121 first semiconductor patterns

122 second semiconductor patterns

12B storage capacitors bottom electrode

14 insulating barriers

16 ' first conductive layer

18 patterning photoresist layers

181 first photoresist layers

182 second photoresist layers

183 the 3rd photoresist layers

16 first patterned conductive layers

16P pixel electrode

161 first barrier pattern

162 second barrier pattern

203 the 3rd doped regions

204 the 4th doped regions

122C second channel district

22 second patterned conductive layers

221 first grids

222 second grids

22C transfers electrode

22T storage capacitors top electrode

201 first doped regions

202 second doped regions

241 first light doping sections

242 second light doping sections

121C first passage district

26 dielectric layers

141 first openings

142 second openings

145 the 5th openings

146 the 6th openings

143 the 3rd openings

28 the 3rd patterned conductive layers

281S first source electrode

281D first drains

282S second source electrode

282D second drains

29 protective layers

144 the 4th openings

30 array base paltes

32 luminescent layers

34 counter electrodes

38 frame glue

50 upper cover substrate

1 display floater

LC liquid crystal layer

40 subtend substrates

42 substrates

CF colored filter

BM black matrix"

44 common electrodes

1 ' display floater

16G second grid

2 display floaters

2 ' display floater

22G the 3rd grid

3 display floaters

3 ' display floater

[embodiment]

For making the general those skilled in the art haveing the knack of the technical field of the invention further can understand the present invention, hereafter spy enumerates preferred embodiment of the present invention, and coordinates institute's accompanying drawings, describe in detail constitution content of the present invention and the effect for reaching.

Please refer to Fig. 1 to Figure 10.Fig. 1 to Figure 10 depicts the method schematic diagram of the making display floater of the first embodiment of the present invention.It is example that the present embodiment system discloses the method making electric exciting light emitting display panel such as organic LED display panel.As shown in Figure 1, substrate 10 is provided.Substrate 10 has picture element region 10P, thin film transistor region 102, the first film transistor area 101, second and storage capacitors district 10C, wherein picture element region 10P is mainly that to arrange the pixel electrode of follow-up formation, the first film transistor area 101 and the second thin film transistor region 102 be the first film transistor AND gate second thin-film transistor being used for arranging follow-up formation respectively, and 10C system of storage capacitors district is used for arranging the storage capacitors of follow-up formation.Substrate 10 can be various rigid or soft transparency carrier such as glass substrate, quartz base plate or plastic substrate etc., but not as limit.Then, on substrate 10, patterned semiconductor layer 12 is formed.Patterned semiconductor layer 12 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.Patterned semiconductor layer 12 comprises that the first semiconductor pattern 121 is arranged in the first film transistor area 101, the second semiconductor pattern 122 is arranged in the second thin film transistor region 102, and storage capacitors bottom electrode 12B is arranged in storage capacitors district 10C.Patterned semiconductor layer 12 can comprise silicon such as amorphous silicon layer, polysilicon layer, microcrystal silicon layer or nanocrystalline silicon layer, or oxide semiconductor layer such as indium oxide gallium zinc (indium gallium zinc oxide, IGZO), indium zinc oxide (indium zinc oxide, IZO), tin indium oxide (indium tin oxide, ITO), titanium oxide (titanium oxide, TiO), zinc oxide (zinc oxide, ZnO), indium oxide (indium oxide, InO), gallium oxide (gallium oxide, GaO), or other various applicable semiconductor layer.Then on substrate 10, insulating barrier 14 is formed.Insulating barrier 14 coverage diagram patterning semiconductor layer 12.Insulating barrier 14 is the use as gate insulator, and its material can be various insulating material such as silica, silicon nitride or silicon oxynitride etc., but not as limit.

Subsequently, form the first patterned conductive layer on insulating barrier 14, wherein the first patterned conductive layer comprises pixel electrode, is arranged in the 10P of picture element region.In the present embodiment, the first pattern conductive series of strata utilize the method shown in Fig. 2 to Fig. 6 to be formed.As shown in Figure 2, on insulating barrier 14, form the first conductive layer 16 ', then form patterning photoresist layer 18 in the first conductive layer 16 ' is upper.Patterning photoresist layer 18 has that the first photoresist layer 181 is positioned at picture element region 10P, the second photoresist layer 182 is positioned at the first film transistor area 101, and the 3rd photoresist layer 183 is positioned at the second thin film transistor region 102.Patterning photoresist layer 18 can utilize such as lithographic process and gray-level mask of arranging in pairs or groups is formed, but not as limit.In addition, the thickness of the first photoresist layer 181 is greater than the thickness of the second photoresist layer 182 and the thickness of the 3rd photoresist layer 183, and the thickness of the second photoresist layer 182 substantially can be equal with the thickness of the 3rd photoresist layer 183, but not as limit.

As shown in Figure 3, then remove not by the first conductive layer 16 ' that the first photoresist layer 181, second photoresist layer 182 and the 3rd photoresist layer 183 cover, to form the first patterned conductive layer 16.First patterned conductive layer 16 comprises that pixel electrode 16P is positioned at picture element region 10P, the first barrier pattern 161 is positioned at the first film transistor area 101, and second barrier pattern 162 be positioned at the second thin film transistor region 102, wherein the first barrier pattern 161 covers the first semiconductor pattern 121 on upright projection direction, and the second barrier pattern 162 cover part second semiconductor pattern 122 on upright projection direction.First patterned conductive layer 16 can comprise transparent print patterning conductive layer or opaque patterned conductive layer.If the first patterned conductive layer 16 selects transparent print patterning conductive layer, its material can be such as tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material be applicable to.If the first patterned conductive layer 16 selects opaque patterned conductive layer, its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Then, in the second semiconductor pattern 122 (that is unlapped second semiconductor pattern 122 of the second barrier pattern 162) underlapped with the second barrier pattern 162 on upright projection direction, form the 3rd doped region 203 and the 4th doped region 204, and storage capacitors bottom electrode 12B is adulterated.In addition, the second semiconductor pattern 122 between the 3rd doped region 203 and the 4th doped region 204 can form second channel district 122C.3rd doped region 203 and the 4th doped region 204 have the second doping type, such as P type doping, but not as limit.3rd doped region 203, the 4th doped region 204 and storage capacitors bottom electrode 12B can utilize such as ion implantation process to be formed, but not as limit.

As shown in Figure 4, subsequently, ashing processes is carried out to remove the second photoresist layer 182 and the 3rd photoresist layer 183.As shown in Figure 5, the first barrier pattern 161 and the second barrier pattern 162 is removed.As shown in Figure 6, then, the first photoresist layer 181 is removed, to expose pixel electrode 16P.

As shown in Figure 6, on insulating barrier 14, the second patterned conductive layer 22 is formed subsequently.Second patterned conductive layer 22 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.Second patterned conductive layer 22 can comprise opaque patterned conductive layer or transparent print patterning conductive layer.If the second patterned conductive layer 22 selects opaque patterned conductive layer, its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.If the second patterned conductive layer 22 selects transparent print patterning conductive layer, its material can be such as tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material be applicable to.Second patterned conductive layer 22 comprises first grid 221, second grid 222, switching electrode 22C and storage capacitors top electrode 22T.First grid 221 to be arranged on insulating barrier 14 and to be positioned at the first film transistor area 101, and wherein on upright projection direction, first grid 221 is first semiconductor pattern 121 that partly overlaps.Second grid 222 to be arranged on insulating barrier 14 and to be positioned at the second thin film transistor region 102.In the present embodiment, first grid 221 and second grid 222 are opaque electrode.Switching electrode 22C is arranged in the 10P of picture element region, wherein the switching electrode 22C of a part contacts with pixel electrode 16P and at upright projection direction upper part overlap pixel electrode 16P, and the switching electrode 22C of another part is positioned at the surface of insulating barrier 14 and not overlapping with pixel electrode 16P on upright projection direction.Speak by the book, switching electrode 22C covers the portion of upper surface of pixel electrode 16P.Storage capacitors top electrode 22T to be arranged on insulating barrier 14 and to be positioned at storage capacitors district 10C, and storage capacitors top electrode 22T, storage capacitors bottom electrode 12B and the insulating barrier 14 between storage capacitors top electrode 22T and storage capacitors bottom electrode 12B form storage capacitors.

Then, the first doped region 201 and the second doped region 202 is formed in the first semiconductor pattern 121 underlapped with first grid 221 on upright projection direction, wherein the first doped region 201 has first doping type different with the second doping type from the second doped region 202, such as N-type doping, but not as limit.First doped region 201 and the second doped region 202 can utilize such as ion implantation process to be formed, but not as limit.As shown in Figure 7, in order to avoid short-channel effect, the method for the present embodiment optionally forms the first light doping section 241 and the second light doping section 242, as lightly doped drain (lightlydoped drain in the first semiconductor pattern 121, LDD), to reduce leakage current.First light doping section 241 and the second light doping section 242 have the first doping type, and the doping content of the first light doping section 241 and the second light doping section 242 is less than the doping content of the first doped region 201 and the second doped region 202.In addition, the first semiconductor pattern 121 between the first light doping section 241 and the second light doping section 242 can form first passage district 121C.In the present invention, the processing procedure forming the first doped region, doped region 202, first, doped region 201, second 201 and the second doped region 202 can be as described below, but not as limit.Remove the first grid 221 of part, make the first semiconductor pattern 121 of part not overlapping with first grid 221 on upright projection direction further to reduce the size of first grid 221.Subsequently, in the first semiconductor pattern 121 underlapped with the first grid 221 of reduction on upright projection direction, the first light doping section 241 and the second light doping section 242 is formed.Speak by the book, in the present embodiment, after forming first grid 221, the photoresistance pattern (not shown) defining first grid 221 can be retained, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, carry out an isotropic etch process such as wet etching processing procedure and remove the partial sidewall of first grid 221 to reduce the size of first grid 221.Remove photoresistance pattern subsequently, the first grid 221 of recycling reduction utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.In an alternate embodiment, after forming first grid 221, such as ion implantation process is then utilized to form the first doped region 201 and the second doped region 202.Carry out ashing (ashing) processing procedure subsequently, reduce the size of the photoresistance pattern (not shown) defining first grid 221.Then, carry out an anisotropic etching processing procedure such as dry ecthing procedure and remove the first grid 221 that covers of photoresistance pattern after not being ashed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In above-mentioned two embodiments, first light doping section 241 and the second light doping section 242 do not need to use extra light shield and can be formed by self-aligned fashion, and the first light doping section 241 and the position of the second light doping section 242 and the position of first grid 221 can not produce relativity shift by this.In another alternate embodiment, after forming first grid 221, remove the photoresistance pattern defining first grid 221, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, on first grid 221, form another photoresistance pattern (not shown), wherein the size of photoresistance pattern is less than the size of first grid 221.Then first grid 221 that photoresistance pattern exposes is removed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In another alternate embodiment, photoresistance pattern (not shown) can be utilized to form first grid 221.Then utilize shade such as shadow mask (shadow mask) or light shield (photo mask) to cover the region of wish formation the first light doping section 241 and the second light doping section 242, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Remove shade subsequently, recycling first grid 221 utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.

As shown in Figure 8, form dielectric layer 26 subsequently and cover insulating barrier 14, pixel electrode 16P and the second patterned conductive layer 22, and in dielectric layer 26 with insulating barrier 14, form the first opening 141 expose that the first doped region 201, second opening 142 exposes the second doped region 202, the 5th opening 145 exposes the 3rd doped region 203 and the 6th opening 146 exposes the 4th doped region 204, and in dielectric layer 26, form the 3rd opening 143 expose switching electrode 22C.First opening 141, second opening 142, the 3rd opening 143, the 5th opening 145 and the 6th opening 146 can utilize such as photoetching and etching technique to be formed, but not as limit.The material of dielectric layer 26 can be Inorganic Dielectric Material such as silica, silicon nitride or silicon oxynitride etc., or organic dielectric materials such as acryl, or organic/inorganic composite material, but not as limit.In addition, in the present embodiment, dielectric layer 26 also can be used as the use of flatness layer, and it has and has smooth surface substantially, but not as limit.

As shown in Figure 9, then on dielectric layer 26, the 3rd patterned conductive layer 28 is formed.3rd patterned conductive layer 28 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.3rd patterned conductive layer 28 can comprise opaque patterned conductive layer or transparent print patterning conductive layer.If the 3rd patterned conductive layer 28 selects opaque patterned conductive layer, its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.If the 3rd patterned conductive layer 28 selects transparent print patterning conductive layer, its material can be such as tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material be applicable to.3rd patterned conductive layer 28 comprises the first source electrode 281S, the first drain electrode 281D, the second source electrode 282S and second drain electrode 282D.First source electrode 281S inserts the first opening 141 and is electrically connected with the first doped region 201; First drain electrode 281D inserts the second opening 142 and is electrically connected and inserts the 3rd opening 143 with the second doped region 202 and is electrically connected with switching electrode 22C; Second source electrode 282S inserts the 5th opening 145 and is electrically connected with the 3rd doped region 203; Second drain electrode 282D inserts the 6th opening 146 and is electrically connected with the 4th doped region 204.In the present embodiment, the first drain electrode 281D system contacts with switching electrode 22C via the 3rd opening 143, and the first drain electrode 281D is electrically connected through switching electrode 22C and pixel electrode 16P by this.Because the 3rd opening 143 is the position exposing switching electrode 22C, instead of expose pixel electrode 16P, therefore when etching dielectric layer 26 forms the 3rd opening 143, the damage of pixel electrode 16P can not be caused.In the present embodiment, in dielectric layer 26 with insulating barrier 14, form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, and formation the 3rd opening 143 can utilize and reached with photoetching and etch process in dielectric layer 26.For example, first can carry out dry ecthing procedure etching dielectric layer 26 until expose switching electrode 22C to form the 3rd opening 143, and etch away the dielectric layer 26 of position of predetermined formation first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146; Then insulating barrier 14 that wet etching processing procedure etching dielectric layer 26 exposes is carried out again to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, the electrode 22C that now transfers can be used as the use of etching stopping layer, to avoid pixel electrode 16P impaired.In other embodiments, also only can use dry ecthing procedure or only use wet etching processing procedure to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146 in dielectric layer 26 with insulating barrier 14, and form the 3rd opening 143 in dielectric layer 26.In the present embodiment, first grid 221, first semiconductor pattern 121, first source electrode 281S and first drain electrode 281D constitutes the first film transistor as driving thin-film transistor; Second grid 222, first semiconductor pattern 122, second source electrode 282S and second drain electrode 282D constitutes the second thin-film transistor as switching thin-film transistor.

As shown in Figure 10, form protective layer 29 subsequently on dielectric layer 26, wherein protective layer 29 covers the first source electrode 281S, the first drain electrode 281D, the second source electrode 282S and second drain electrode 282D.Then in protective layer 29 with dielectric layer 26, form the 4th opening 144, expose pixel electrode 16P, to form array base palte 30.4th opening 144 can utilize such as photoetching and etching technique to be formed, but not as limit.The material of protective layer 29 can be Inorganic Dielectric Material such as silica, silicon nitride or silicon oxynitride etc., or organic dielectric materials such as acryl, or organic/inorganic composite material, but not as limit.In the present embodiment, the material system of patterned semiconductor layer 12 selects amorphous silicon, but not as limit.In addition, the method for the present embodiment separately can comprise and carries out activation process such as Rapid Thermal processing procedure and hydrogenation processing procedure such as plasma hydrogenation processing procedure.Activation process can activate Doped ions, to reduce the contact resistance of transistor drain and source metal and semiconductor interface, makes thin-film transistor have preferably element characteristic; Hydrogenation processing procedure can promote the electron mobility of thin-film transistor.Activation process can carry out any time after ion doping, and hydrogenation processing procedure can need carry out after dielectric layer 26 is formed, and associated hot processing procedure will be different because of each material temperature capability, and collocation selects right times to carry out.

As shown in Figure 10, on pixel electrode 16P, luminescent layer 32 and counter electrode 34 is formed subsequently.Luminescent layer 32 can comprise organic luminous layer, such as ruddiness organic luminous layer, green glow organic luminous layer, blue light organic emissive layer or white-light organic light-emitting layer, but not as limit.Luminescent layer 32 also can be other organic luminous layer that can send the light of required color or inorganic light emitting layers.The material of counter electrode 34 can be transparent conductive material such as tin indium oxide, indium zinc oxide or other transparent conductive material be applicable to, or opaque electric conducting material such as metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Pixel electrode 16P and counter electrode 34 are respectively as anode and negative electrode, in order to drive luminescent layer 32 luminous.Pixel electrode 16P, counter electrode 34 can be formed with OLED with luminescent layer 32.In addition, provide upper cover substrate 50, and utilize frame glue 38 engaged arrays substrate 30 and upper cover substrate 50 to form the display floater 1 of the present embodiment.

Please refer to Figure 11, and in the lump referring to figs. 1 to Fig. 9.Figure 11 depicts the method schematic diagram of the making display floater of the alternate embodiment of the first embodiment of the present invention.It is example that this alternate embodiment system discloses the method making display panels, and the step that wherein Fig. 1 to Fig. 9 illustrates is the common step of this alternate embodiment and the first embodiment, and therefore the method for this alternate embodiment can be carried out after the step of hookup 9.As shown in figure 11, after formation protective layer 29, then on pixel electrode 16P, liquid crystal layer LC is formed.In addition, provide subtend substrate 40, and utilize frame glue 38 engaged arrays substrate 30 and subtend substrate 40 to form the display floater 1 ' of the present embodiment.Subtend substrate 40 can comprise the elements such as another substrate 42, colored filter CF, black matrix" BM and common electrode 44, its position with act as this field tool and usually know and know known to the knowledgeable, do not repeat them here.In the present embodiment, the first film transistor can be used as the use of the switching thin-film transistor of the viewing area of display panels, and the second thin-film transistor then can be used as the use of the driving thin-film transistor of the periphery circuit region of display panels, but not as limit.

Display floater of the present invention and preparation method thereof is not limited with above-described embodiment.Hereafter will sequentially introduce display floater of other preferred embodiment of the present invention and alternate embodiment and preparation method thereof, and for the ease of the deviation of more each embodiment and simplified illustration, identical symbol is used to mark identical element in the following embodiments, and be described mainly for the deviation of each embodiment, and no longer repeating part is repeated.

Please refer to Figure 12 to Figure 20.Figure 12 to Figure 20 depicts the method schematic diagram of the making display floater of the second embodiment of the present invention.It is example that the present embodiment system discloses the method making electric exciting light emitting display panel such as organic LED display panel.As shown in figure 12, substrate 10 is provided.Substrate 10 has picture element region 10P, thin film transistor region 102, the first film transistor area 101, second and storage capacitors district 10C, wherein picture element region 10P is mainly that to arrange the pixel electrode of follow-up formation, the first film transistor area 101 and the second thin film transistor region 102 be the first film transistor AND gate second thin-film transistor being used for arranging follow-up formation respectively, and 10C system of storage capacitors district is used for arranging the storage capacitors of follow-up formation.Substrate 10 can be various rigid or soft transparency carrier such as glass substrate, quartz base plate or plastic substrate etc., but not as limit.Then, on substrate 10, a patterned semiconductor layer 12 and insulating barrier 14 is sequentially formed.Patterned semiconductor layer 12 comprises that the first semiconductor pattern 121 is arranged in the first film transistor area 101, the second semiconductor pattern 122 is arranged in the second thin film transistor region 102, and storage capacitors bottom electrode 12B is arranged in storage capacitors district 10C.Patterned semiconductor layer 12 can comprise silicon such as amorphous silicon layer, polysilicon layer, microcrystal silicon layer or nanocrystalline silicon layer, or oxide semiconductor layer such as indium oxide gallium zinc (indium gallium zinc oxide, IGZO), indium zinc oxide (indium zinc oxide, IZO), tin indium oxide (indium tin oxide, ITO), titanium oxide (titanium oxide, TiO), zinc oxide (zinc oxide, ZnO), indium oxide (indiumoxide, InO), gallium oxide (gallium oxide, GaO), or other various applicable semiconductor layer.Insulating barrier 14 is the use as gate insulator, and its material can be various insulating material such as silica, silicon nitride or silicon oxynitride etc., but not as limit.

Subsequently, form the first patterned conductive layer 16 on insulating barrier 14, wherein the first patterned conductive layer 16 comprises pixel electrode and establishes 16P to be placed in the 10P of picture element region, and second grid 16G is arranged in the second thin film transistor region 102.In the present embodiment, the first patterned conductive layer 16 is utilize the method shown in Figure 13 to 17 figure to be formed.As shown in figure 13, on insulating barrier 14, form the first conductive layer 16 ', then form patterning photoresist layer 18 in the first conductive layer 16 ' is upper.Patterning photoresist layer 18 has that the first photoresist layer 181 is positioned at picture element region 10P, the second photoresist layer 182 is positioned at the first film transistor area 121, and the 3rd photoresist layer 183 is positioned at the second thin film transistor region 120.Patterning photoresist layer 18 can utilize such as lithographic process and gray-level mask of arranging in pairs or groups is formed, but not as limit.In addition, the thickness of the second photoresist layer 182 is less than the thickness of the first photoresist layer 181 and the thickness of the 3rd photoresist layer 183, and the thickness of the first photoresist layer 181 substantially can be equal with the thickness of the 3rd photoresist layer 183, but not as limit.

As shown in figure 14, then remove not by the first conductive layer 16 ' that the first photoresist layer 181, second photoresist layer 182 and the 3rd photoresist layer 183 cover, to form the first patterned conductive layer 16.First patterned conductive layer 16 comprises that pixel electrode 16P is positioned at picture element region 10P, the first barrier pattern 161 is positioned at the first film transistor area 101, and second grid 16G is positioned at the second thin film transistor region 102, wherein the first barrier pattern 161 covers the first semiconductor pattern 121 on upright projection direction, and second grid 16G covers the second semiconductor pattern 122 in upright projection direction upper part.First patterned conductive layer 16 can comprise transparent print patterning conductive layer or opaque patterned conductive layer.If the first patterned conductive layer 16 selects transparent print patterning conductive layer, its material can be such as tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material be applicable to.If the first patterned conductive layer 16 selects opaque patterned conductive layer, its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Then, in the second semiconductor pattern 122 underlapped with second grid 16G on upright projection direction, form the 3rd doped region 203 and the 4th doped region 204, and storage capacitors bottom electrode 12B is adulterated.In addition, the second semiconductor pattern 122 between the 3rd doped region 203 and the 4th doped region 204 can form second channel district 122C.3rd doped region 203 and the 4th doped region 204 have the second doping type, such as P type doping, but not as limit.3rd doped region 203, the 4th doped region 204 and storage capacitors bottom electrode 12B can utilize such as ion implantation process to be formed, but not as limit.As shown in figure 15, subsequently, ashing processes is carried out to remove the second photoresist layer 182.As shown in figure 16, the first barrier pattern 161 is removed.As shown in figure 17, then, remove the first photoresist layer 181 to expose pixel electrode 16P, and remove the 3rd photoresistance pattern 183 to expose second grid 16G.In the present embodiment, second grid 16G is transparency electrode.

As shown in figure 17, on insulating barrier 14, the second patterned conductive layer 22 is formed subsequently.Second patterned conductive layer 22 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.Second patterned conductive layer 22 can comprise opaque patterned conductive layer or transparent print patterning conductive layer.If the second patterned conductive layer 22 selects opaque patterned conductive layer, its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.If the second patterned conductive layer 22 selects transparent print patterning conductive layer, its material can be such as tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material be applicable to.Second patterned conductive layer 22 comprises first grid 221, switching electrode 22C and storage capacitors top electrode 22T.First grid 221 to be arranged on insulating barrier 14 and to be positioned at the first film transistor area 101, and wherein on upright projection direction, first grid 221 is first semiconductor pattern 121 that partly overlaps.First grid 221 is opaque electrode.Switching electrode 22C is arranged in the 10P of picture element region, wherein the switching electrode 22C of a part contacts with pixel electrode 16P and at upright projection direction upper part overlap pixel electrode 16P, and the switching electrode 22C of another part is positioned at the surface of insulating barrier 14 and not overlapping with pixel electrode 16P on upright projection direction.Speak by the book, switching electrode 22C covers the portion of upper surface of pixel electrode 16P.Storage capacitors top electrode 22T to be arranged on insulating barrier 14 and to be positioned at storage capacitors district 10C, and storage capacitors top electrode 22T, storage capacitors bottom electrode 12B and the insulating barrier 14 between storage capacitors top electrode 22T and storage capacitors bottom electrode 12B form storage capacitors.

Then, the first doped region 201 and the second doped region 202 is formed in the first semiconductor pattern 121 underlapped with first grid 221 on upright projection direction, wherein the first doped region 201 has first doping type different with the second doping type from the second doped region 202, such as N-type doping, but not as limit.First doped region 201 and the second doped region 202 can utilize such as ion implantation process to be formed, but not as limit.In addition, as shown in figure 18, in order to avoid short-channel effect, the method of the present embodiment optionally forms the first light doping section 241 and the second light doping section 242 in the first semiconductor pattern 121, as lightly doped drain (lightly doped drain, LDD), to reduce leakage current.First light doping section 241 and the second light doping section 242 have the first doping type, and the doping content of the first light doping section 241 and the second light doping section 242 is less than the doping content of the first doped region 201 and the second doped region 202.In addition, the first semiconductor pattern 121 between the first light doping section 241 and the second light doping section 242 can form first passage district 121C.In the present invention, the processing procedure forming the first doped region, doped region 202, first, doped region 201, second 201 and the second doped region 202 can be as described below, but not as limit.Remove the first grid 221 of part, make the first semiconductor pattern 121 of part not overlapping with first grid 221 on upright projection direction further to reduce the size of first grid 221.Subsequently, in the first semiconductor pattern 121 underlapped with the first grid 221 of reduction on upright projection direction, the first light doping section 241 and the second light doping section 242 is formed.Speak by the book, in the present embodiment, after forming first grid 221, the photoresistance pattern (not shown) defining first grid 221 can be retained, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, carry out an isotropic etch process such as wet etching processing procedure and remove the partial sidewall of first grid 221 to reduce the size of first grid 221.Remove photoresistance pattern subsequently, the first grid 221 of recycling reduction utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.In an alternate embodiment, after forming first grid 221, such as ion implantation process is then utilized to form the first doped region 201 and the second doped region 202.Carry out ashing (ashing) processing procedure subsequently, reduce the size of the photoresistance pattern (not shown) defining first grid 221.Then, carry out an anisotropic etching processing procedure such as dry ecthing procedure and remove the first grid 221 that covers of photoresistance pattern after not being ashed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In above-mentioned two embodiments, first light doping section 241 and the second light doping section 242 do not need to use extra light shield and can be formed by self-aligned fashion, and the first light doping section 241 and the position of the second light doping section 242 and the position of first grid 221 can not produce relativity shift by this.In another alternate embodiment, after forming first grid 221, remove the photoresistance pattern defining first grid 221, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, on first grid 221, form another photoresistance pattern (not shown), wherein the size of photoresistance pattern is less than the size of first grid 221.Then first grid 221 that photoresistance pattern exposes is removed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In another alternate embodiment, photoresistance pattern (not shown) can be utilized to form first grid 221.Then utilize shade such as shadow mask (shadow mask) or light shield (photo mask) to cover the region of wish formation the first light doping section 241 and the second light doping section 242, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Remove shade subsequently, recycling first grid 221 utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.

As shown in figure 19, form dielectric layer 26 subsequently and cover insulating barrier 14, pixel electrode 16P and the second patterned conductive layer 22, and in dielectric layer 26 with insulating barrier 14, form the first opening 141 expose that the first doped region 201, second opening 142 exposes the second doped region 202, the 5th opening 145 exposes the 3rd doped region 203 and the 6th opening 146 exposes the 4th doped region 204, and in dielectric layer 26, form the 3rd opening 143 expose switching electrode 22C.First opening 141, second opening 142, the 3rd opening 143, the 5th opening 145 and the 6th opening 146 can utilize such as photoetching and etching technique to be formed, but not as limit.The material of dielectric layer 26 can be Inorganic Dielectric Material such as silica, silicon nitride or silicon oxynitride etc., or organic dielectric materials such as acryl, or organic/inorganic composite material, but not as limit.In addition, in the present embodiment, dielectric layer 26 also can be used as the use of flatness layer, and it has and has smooth surface substantially, but not as limit.Then on dielectric layer 26, the 3rd patterned conductive layer 28 is formed.3rd patterned conductive layer 28 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.3rd patterned conductive layer 28 comprises opaque conductive layer, and its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.3rd patterned conductive layer 28 comprises the first source electrode 281S, the first drain electrode 281D, the second source electrode 282S and second drain electrode 282D.First source electrode 281S inserts the first opening 141 and is electrically connected with the first doped region 201; First drain electrode 281D inserts the second opening 142 and is electrically connected and inserts the 3rd opening 143 with the second doped region 202 and is electrically connected with switching electrode 22C; Second source electrode 282S inserts the 5th opening 145 and is electrically connected with the 3rd doped region 203; Second drain electrode 282D inserts the 6th opening 146 and is electrically connected with the 4th doped region 204.In the present embodiment, the first drain electrode 281D system contacts with switching electrode 22C via the 3rd opening 143, and the first drain electrode 281D is electrically connected through switching electrode 22C and pixel electrode 16P by this.Because the 3rd opening 143 is the position exposing switching electrode 22C, instead of expose pixel electrode 16P, therefore when etching dielectric layer 26 forms the 3rd opening 143, the damage of pixel electrode 16P can not be caused.In the present embodiment, in dielectric layer 26 with insulating barrier 14, form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, and formation the 3rd opening 143 can utilize and reached with photoetching and etch process in dielectric layer 26.For example, first can carry out dry ecthing procedure etching dielectric layer 26 until expose switching electrode 22C to form the 3rd opening 143, and etch away the dielectric layer 26 of position of predetermined formation first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146; Then insulating barrier 14 that wet etching processing procedure etching dielectric layer 26 exposes is carried out again to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, the electrode 22C that now transfers can be used as the use of etching stopping layer, to avoid pixel electrode 16P impaired.In other embodiments, also only can use dry ecthing procedure or only use wet etching processing procedure to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146 in dielectric layer 26 with insulating barrier 14, and form the 3rd opening 143 in dielectric layer 26.In the present embodiment, first grid 221, first semiconductor pattern 121, first source electrode 281S and first drain electrode 281D constitutes the first film transistor as driving thin-film transistor; Second grid 16G, the first semiconductor pattern 122, second source electrode 282S and the second drain electrode 282D constitute the second thin-film transistor as switching thin-film transistor.

Subsequently, form protective layer 29 on dielectric layer 26, wherein protective layer 29 covers the first source electrode 281S, the first drain electrode 281D, the second source electrode 282S and second drain electrode 282D.Then in protective layer 29 with dielectric layer 26, form the 4th opening 144, expose pixel electrode 16P, to form array base palte 30.4th opening 144 can utilize such as photoetching and etching technique to be formed, but not as limit.The material of protective layer 29 can be Inorganic Dielectric Material such as silica, silicon nitride or silicon oxynitride etc., or organic dielectric materials such as acryl, or organic/inorganic composite material, but not as limit.In the present embodiment, the material system of patterned semiconductor layer 12 selects amorphous silicon, but not as limit.In addition, the method for the present embodiment separately can comprise and carries out activation process such as Rapid Thermal processing procedure and hydrogenation processing procedure such as plasma hydrogenation processing procedure.Activation process can activate Doped ions, to reduce the contact resistance of transistor drain and source metal and semiconductor interface, makes thin-film transistor have preferably element characteristic; Hydrogenation processing procedure can promote the electron mobility of thin-film transistor.Activation process can carry out any time after ion doping, and hydrogenation processing procedure can need carry out after dielectric layer 26 is formed, and associated hot processing procedure will be different because of each material temperature capability, and collocation selects right times to carry out.

As shown in figure 20, on pixel electrode 16P, luminescent layer 32 and counter electrode 34 is formed subsequently.Luminescent layer 32 can comprise organic luminous layer, such as ruddiness organic luminous layer, green glow organic luminous layer, blue light organic emissive layer or white-light organic light-emitting layer, but not as limit.Luminescent layer 32 also can be other organic luminous layer that can send the light of required color or inorganic light emitting layers.The material of counter electrode 34 can be transparent conductive material such as tin indium oxide, indium zinc oxide or other transparent conductive material be applicable to, or opaque electric conducting material such as metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Pixel electrode 16P and counter electrode 34 are respectively as anode and negative electrode, in order to drive luminescent layer 32 luminous.Pixel electrode 16P, counter electrode 34 can be formed with OLED with luminescent layer 32.In addition, provide upper cover substrate 50, and utilize frame glue 38 engaged arrays substrate 30 and upper cover substrate 50 to form the display floater 2 of the present embodiment.

Please refer to Figure 21, and in the lump referring to figs 12 to Figure 19.Figure 21 depicts the method schematic diagram of the making display floater of the alternate embodiment of the second embodiment of the present invention.This alternate embodiment system discloses and makes the method for display panels is example, and the step that wherein Figure 12 to Figure 19 illustrates is this alternate embodiment and the common step of the second embodiment, therefore the method for this alternate embodiment can continue Figure 19 step after carry out.As shown in figure 21, after formation protective layer 29, then on pixel electrode 16P, liquid crystal layer LC is formed.In addition, provide subtend substrate 40, and utilize frame glue 38 engaged arrays substrate 30 and subtend substrate 40 to form the display floater 2 ' of the present embodiment.Subtend substrate 40 can comprise the elements such as another substrate 42, colored filter CF, black matrix" BM and common electrode 44, its position with act as this field tool and usually know and know known to the knowledgeable, do not repeat them here.In the present embodiment, the first film transistor can be used as the use of the switching thin-film transistor of the viewing area of display panels, and the second thin-film transistor then can be used as the use of the driving thin-film transistor of the periphery circuit region of display panels, but not as limit.

Please refer to Figure 22 to Figure 25.Figure 22 to Figure 25 depicts the method schematic diagram of the making display floater of the third embodiment of the present invention.It is example that the present embodiment system discloses the method making electric exciting light emitting display panel such as organic LED display panel, the step that wherein Figure 12 to Figure 16 illustrates is the common step of the second embodiment and the 3rd embodiment, therefore the method for the 3rd embodiment can continue Figure 16 step after carry out.As shown in figure 22, on insulating barrier 14, the second patterned conductive layer 22 is formed subsequently.Second patterned conductive layer 22 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.Second patterned conductive layer 22 comprises opaque conductive layer, and its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Second patterned conductive layer 22 comprises first grid 221, the 3rd grid 22G, switching electrode 22C and storage capacitors top electrode 22T.First grid 221 to be arranged on insulating barrier 14 and to be positioned at the first film transistor area 101, and wherein on upright projection direction, first grid 221 is first semiconductor pattern 121 that partly overlaps.3rd grid 22G is arranged in the second thin film transistor region 102, and the 3rd grid 22G system to be formed on second grid 16G and to contact with second grid 16G.3rd grid 22G is opaque electrode, and second grid 16G is transparency electrode.In the present embodiment, the size that the size of the 3rd grid 22G is less than second grid 16G is substantially identical substantially, but not as limit.In other embodiments, the size of the 3rd grid 22G can be more than or equal to the size of second grid 16G.Switching electrode 22C is arranged in the 10P of picture element region, wherein the switching electrode 22C of a part contacts with pixel electrode 16P and at upright projection direction upper part overlap pixel electrode 16P, and the switching electrode 22C of another part is positioned at the surface of insulating barrier 14 and not overlapping with pixel electrode 16P on upright projection direction.Speak by the book, switching electrode 22C covers the portion of upper surface of pixel electrode 16P.Storage capacitors top electrode 22T to be arranged on insulating barrier 14 and to be positioned at storage capacitors district 10C, and storage capacitors top electrode 22T, storage capacitors bottom electrode 12B and the insulating barrier 14 between storage capacitors top electrode 22T and storage capacitors bottom electrode 12B form storage capacitors.

Then, the first doped region 201 and the second doped region 202 is formed in the first semiconductor pattern 121 underlapped with first grid 221 on upright projection direction, wherein the first doped region 201 has first doping type different with the second doping type from the second doped region 202, such as N-type doping, but not as limit.First doped region 201 and the second doped region 202 can utilize such as ion implantation process to be formed, but not as limit.As shown in figure 23, in order to avoid short-channel effect, the method for the present embodiment optionally forms the first light doping section 241 and the second light doping section 242, as lightly doped drain (lightlydoped drain in the first semiconductor pattern 121, LDD), to reduce leakage current.First light doping section 241 and the second light doping section 242 have the first doping type, and the doping content of the first light doping section 241 and the second light doping section 242 is less than the doping content of the first doped region 201 and the second doped region 202.In addition, the first semiconductor pattern 121 between the first light doping section 241 and the second light doping section 242 can form first passage district 121C.In the present invention, the processing procedure forming the first doped region, doped region 202, first, doped region 201, second 201 and the second doped region 202 can be as described below, but not as limit.Remove the first grid 221 of part, make the first semiconductor pattern 121 of part not overlapping with first grid 221 on upright projection direction further to reduce the size of first grid 221.Subsequently, in the first semiconductor pattern 121 underlapped with the first grid 221 of reduction on upright projection direction, the first light doping section 241 and the second light doping section 242 is formed.Speak by the book, in the present embodiment, after forming first grid 221, the photoresistance pattern (not shown) defining first grid 221 can be retained, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, carry out an isotropic etch process such as wet etching processing procedure and remove the partial sidewall of first grid 221 to reduce the size of first grid 221.Remove photoresistance pattern subsequently, the first grid 221 of recycling reduction utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.In an alternate embodiment, after forming first grid 221, such as ion implantation process is then utilized to form the first doped region 201 and the second doped region 202.Carry out ashing (ashing) processing procedure subsequently, reduce the size of the photoresistance pattern (not shown) defining first grid 221.Then, carry out an anisotropic etching processing procedure such as dry ecthing procedure and remove the first grid 221 that covers of photoresistance pattern after not being ashed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In above-mentioned two embodiments, first light doping section 241 and the second light doping section 242 do not need to use extra light shield and can be formed by self-aligned fashion, and the first light doping section 241 and the position of the second light doping section 242 and the position of first grid 221 can not produce relativity shift by this.In another alternate embodiment, after forming first grid 221, remove the photoresistance pattern defining first grid 221, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Then, on first grid 221, form another photoresistance pattern (not shown), wherein the size of photoresistance pattern is less than the size of first grid 221.Then first grid 221 that photoresistance pattern exposes is removed to reduce the size of first grid 221.The first grid 221 recycling reduction is subsequently as shade and utilize such as ion implantation process to form the first light doping section 241 and the second light doping section 242, and removes photoresistance pattern.In another alternate embodiment, photoresistance pattern (not shown) can be utilized to form first grid 221.Then utilize shade such as shadow mask (shadow mask) or light shield (photo mask) to cover the region of wish formation the first light doping section 241 and the second light doping section 242, and utilize such as ion implantation process to form the first doped region 201 and the second doped region 202.Remove shade subsequently, recycling first grid 221 utilizes such as ion implantation process to form the first light doping section 241 and the second light doping section 242 as shade.

As shown in figure 24, form dielectric layer 26 subsequently and cover insulating barrier 14, pixel electrode 16P and the second patterned conductive layer 22, and in dielectric layer 26 with insulating barrier 14, form the first opening 141 expose that the first doped region 201, second opening 142 exposes the second doped region 202, the 5th opening 145 exposes the 3rd doped region 203 and the 6th opening 146 exposes the 4th doped region 204, and in dielectric layer 26, form the 3rd opening 143 expose switching electrode 22C.First opening 141, second opening 142, the 3rd opening 143, the 5th opening 145 and the 6th opening 146 can utilize such as photoetching and etching technique to be formed, but not as limit.The material of dielectric layer 26 can be Inorganic Dielectric Material such as silica, silicon nitride or silicon oxynitride etc., or organic dielectric materials such as acryl, or organic/inorganic composite material, but not as limit.In addition, in the present embodiment, dielectric layer 26 also can be used as the use of flatness layer, and it has and has smooth surface substantially, but not as limit.Then on dielectric layer 26, the 3rd patterned conductive layer 28 is formed.3rd patterned conductive layer 28 can utilize such as deposition, photoetching and etching technique to be formed, but not as limit.3rd patterned conductive layer 28 comprises opaque conductive layer, and its material can be metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.3rd patterned conductive layer 28 comprises the first source electrode 281S, the first drain electrode 281D, the second source electrode 282S and second drain electrode 282D.First source electrode 281S inserts the first opening 141 and is electrically connected with the first doped region 201; First drain electrode 281D inserts the second opening 142 and is electrically connected and inserts the 3rd opening 143 with the second doped region 202 and is electrically connected with switching electrode 22C; Second source electrode 282S inserts the 5th opening 145 and is electrically connected with the 3rd doped region 203; Second drain electrode 282D inserts the 6th opening 146 and is electrically connected with the 4th doped region 204.In the present embodiment, the first drain electrode 281D system contacts with switching electrode 22C via the 3rd opening 143, and the first drain electrode 281D is electrically connected through switching electrode 22C and pixel electrode 16P by this.Because the 3rd opening 143 is the position exposing switching electrode 22C, instead of expose pixel electrode 16P, therefore when etching dielectric layer 26 forms the 3rd opening 143, the damage of pixel electrode 16P can not be caused.In the present embodiment, in dielectric layer 26 with insulating barrier 14, form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, and formation the 3rd opening 143 can utilize and reached with photoetching and etch process in dielectric layer 26.For example, first can carry out dry ecthing procedure etching dielectric layer 26 until expose switching electrode 22C to form the 3rd opening 143, and etch away the dielectric layer 26 of position of predetermined formation first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146; Then insulating barrier 14 that wet etching processing procedure etching dielectric layer 26 exposes is carried out again to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146, the electrode 22C that now transfers can be used as the use of etching stopping layer, to avoid pixel electrode 16P impaired.In other embodiments, also only can use dry ecthing procedure or only use wet etching processing procedure to form the first opening 141, second opening 142, the 5th opening 145 and the 6th opening 146 in dielectric layer 26 with insulating barrier 14, and form the 3rd opening 143 in dielectric layer 26.In the present embodiment, first grid 221, first semiconductor pattern 121, first source electrode 281S and first drain electrode 281D constitutes the first film transistor as driving thin-film transistor; Second grid 16G, the first semiconductor pattern 122, second source electrode 282S and the second drain electrode 282D constitute the second thin-film transistor as switching thin-film transistor.

As shown in figure 25, on pixel electrode 16P, luminescent layer 32 and counter electrode 34 is formed subsequently.Luminescent layer 32 can comprise organic luminous layer, such as ruddiness organic luminous layer, green glow organic luminous layer, blue light organic emissive layer or white-light organic light-emitting layer, but not as limit.Luminescent layer 32 also can be other organic luminous layer that can send the light of required color or inorganic light emitting layers.The material of counter electrode 34 can be transparent conductive material such as tin indium oxide, indium zinc oxide or other transparent conductive material be applicable to, or opaque electric conducting material such as metal or alloy, metal or its alloys such as such as gold, silver, copper, aluminium, titanium, molybdenum, but not as limit.Pixel electrode 16P and counter electrode 34 are respectively as anode and negative electrode, in order to drive luminescent layer 32 luminous.Pixel electrode 16P, counter electrode 34 can be formed with OLED with luminescent layer 32.In addition, provide upper cover substrate 50, and utilize frame glue 38 engaged arrays substrate 30 and upper cover substrate 50 to form the display floater 3 of the present embodiment.

Please refer to Figure 26, and in the lump with reference to Figure 22 to Figure 24.Figure 26 depicts the method schematic diagram of the making display floater of the alternate embodiment of the third embodiment of the present invention.This alternate embodiment system discloses and makes the method for display panels is example, and the step that wherein Figure 22 to Figure 24 illustrates is this alternate embodiment and the common step of the 3rd embodiment, therefore the method for this alternate embodiment can continue Figure 24 step after carry out.As shown in figure 26, after formation protective layer 29, then on pixel electrode 16P, liquid crystal layer LC is formed.In addition, provide subtend substrate 40, and utilize frame glue 38 engaged arrays substrate 30 and subtend substrate 40 to form the display floater 3 ' of the present embodiment.Subtend substrate 40 can comprise the elements such as another substrate 42, colored filter CF, black matrix" BM and common electrode 44, its position with act as this field tool and usually know and know known to the knowledgeable, do not repeat them here.In the present embodiment, the first film transistor can be used as the use of the switching thin-film transistor of the viewing area of display panels, and the second thin-film transistor then can be used as the use of the driving thin-film transistor of the periphery circuit region of display panels, but not as limit.

In sum, display floater of the present invention and preparation method thereof has following advantages.The source doping region of the thin-film transistor of display floater can utilize with drain doping region, storage capacitors bottom electrode and pixel electrode and be formed with gray-level mask.The bottom electrode of the storage capacitors of display floater and top electrode are respectively doped semiconductor electrode and opaque electrode, its respectively can with the process integration of the semiconductor layer of thin-film transistor with grid, therefore do not need increase additional process and there is preferably capacitance.Display floater has the connecting electrode jointly formed with the grid of thin-film transistor, and the drain electrode system of thin-film transistor is electrically connected via connecting electrode and pixel electrode, therefore connecting electrode does not need to utilize additional process to be made, and this practice can avoid pixel electrode to sustain damage when etching dielectric layer.Moreover the source doping region of thin-film transistor and drain implants fauna utilize grid to carry out ion implantation as shade, therefore do not need use extra light shield and can be formed by self-aligned fashion.In addition, the pixel electrode be made up of patterned transparent conductive layer is formed after lying in the switching electrode be made up of the first patterning opaque conductive layer, therefore can not cause the crystallization of patterned transparent conductive layer in time depositing opaque conductive layer.In addition, because pixel electrode only has the overlapping of small size with switching electrode, therefore problem can not be peeling when high temperature process.

The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.

Claims

1. make a method for display floater, comprising:

There is provided a substrate, this substrate has a picture element region and a first film transistor area;

On this substrate, form a patterned semiconductor layer, this patterned semiconductor layer comprises one first semiconductor pattern, is arranged in this first film transistor area;

On this substrate, form an insulating barrier, wherein this insulating barrier covers this patterned semiconductor layer;

On this insulating barrier, form one first patterned conductive layer, this first patterned conductive layer comprises a pixel electrode, is arranged in this picture element region;

On this insulating barrier, form one second patterned conductive layer, this second patterned conductive layer comprises:

One first grid, is arranged in this first film transistor area, and wherein on a upright projection direction, this first grid partly overlaps this first semiconductor pattern; And

One switching electrode, be arranged in this picture element region, wherein this switching electrode of a part contacts with this pixel electrode and at this pixel electrode of this upright projection direction upper part overlap, and this switching electrode of another part is positioned at the surface of this insulating barrier and not overlapping with this pixel electrode on this upright projection direction;

In this first semiconductor pattern underlapped with this first grid on this upright projection direction, form one first doped region and one second doped region, wherein this first doped region and this second doped region have one first doping type;

Form a dielectric layer and cover this insulating barrier, this pixel electrode and this second patterned conductive layer, and in this dielectric layer and this insulating barrier, form one first opening expose this first doped region and one second opening exposes this second doped region, and in this dielectric layer, form one the 3rd opening expose this switching electrode; And

On this dielectric layer, form one the 3rd patterned conductive layer, the 3rd patterned conductive layer comprises:

One first source electrode, inserts this first opening and is electrically connected with this first doped region; And

One first drain electrode, inserts this second opening and is electrically connected and inserts the 3rd opening with this second doped region and this switching electrode is electrically connected.

2. the method for making display floater according to claim 1, it is characterized in that, this patterned semiconductor layer comprises a polysilicon semiconductor layer, this first patterned conductive layer comprises a transparency conducting layer, this second patterned conductive layer comprises an opaque conductive layer, and the 3rd patterned conductive layer comprises an opaque conductive layer.

3. the method for making display floater according to claim 1; it is characterized in that, be separately included on this dielectric layer and form a protective layer, to cover this first source electrode and this first drains; and in this protective layer and this dielectric layer, form one the 4th opening, expose this pixel electrode.

4. the method for making display floater according to claim 3, is characterized in that, this substrate has more one second thin film transistor region and a storage capacitors district,

This patterned semiconductor layer more comprises:

One second semiconductor pattern, to be arranged on this substrate and to be positioned at this second thin film transistor region, wherein this second semiconductor pattern has one the 3rd doped region and one the 4th doped region, and the 3rd doped region and the 4th doped region have the second doping type that is different from this first doping type; And

One storage capacitors bottom electrode, to be arranged on this substrate and to be positioned at this storage capacitors district;

This second patterned conductive layer more comprises:

One second grid, to be arranged on this insulating barrier and to be positioned at this second thin film transistor region; And

One storage capacitors top electrode, to be arranged on this insulating barrier and to be positioned at this storage capacitors district;

This dielectric layer and this insulating barrier have more:

One the 5th opening, exposes the 3rd doped region; And

One the 6th opening, exposes the 4th doped region; And

3rd patterned conductive layer more comprises:

One second source electrode, is positioned at this second thin film transistor region, and this second source electrode is inserted the 5th opening and is electrically connected with the 3rd doped region; And

One second drain electrode, is positioned at this second thin film transistor region, and this second drain electrode is inserted the 6th opening and is electrically connected with the 4th doped region.

5. the method for making display floater according to claim 4, is characterized in that, the step forming this first patterned conductive layer comprises:

One first conductive layer is formed on this insulating barrier;

On this first conductive layer, form a patterning photoresist layer, this patterning photoresist layer has:

One first photoresist layer, is positioned at this picture element region;

One second photoresist layer, is positioned at this first film transistor area; And

One the 3rd photoresist layer, is positioned at this second thin film transistor region, and wherein the thickness of this first photoresist layer is greater than the thickness of this second photoresist layer and the thickness of the 3rd photoresist layer;

Remove not by this first conductive layer that this first photoresist layer, this second photoresist layer and the 3rd photoresist layer cover, one first barrier pattern is formed to form this pixel electrode in this picture element region, in this first film transistor area, and one second barrier pattern is formed in this second thin film transistor region, wherein this first barrier pattern covers this first semiconductor pattern on this upright projection direction, and this second barrier pattern covers this second semiconductor pattern in this upright projection direction upper part;

In this second semiconductor pattern underlapped with this second barrier pattern on this upright projection direction, form the 3rd doped region and the 4th doped region, and this storage capacitors bottom electrode is adulterated;

Carry out an ashing processes to remove this second photoresist layer and the 3rd photoresist layer;

Remove this first barrier pattern and this second barrier pattern; And

Remove this first photoresist layer.

6. the method for making display floater according to claim 3, is characterized in that, this substrate has more one second thin film transistor region and a storage capacitors district,

This patterned semiconductor layer more comprises:

This second patterned conductive layer more comprises:

This dielectric layer and this insulating barrier have more:

One the 5th opening, exposes the 3rd doped region; And

One the 6th opening, exposes the 4th doped region; And

3rd patterned conductive layer more comprises:

7. the method for making display floater according to claim 6, is characterized in that, the step forming this first patterned conductive layer comprises:

One first conductive layer is formed on this insulating barrier;

One first photoresist layer, is positioned at this picture element region;

One the 3rd photoresist layer, is positioned at this second thin film transistor region, and wherein the thickness of this second photoresist layer is less than the thickness of this first photoresist layer and the thickness of the 3rd photoresist layer;

Remove not by this first conductive layer that this first photoresist layer, this second photoresist layer and the 3rd photoresist layer cover, one first barrier pattern is formed to form this pixel electrode in this picture element region, in this first film transistor area, and a second grid is formed in this second thin film transistor region, wherein this first barrier pattern covers this first semiconductor pattern on this upright projection direction, and this second grid covers this second semiconductor pattern in this upright projection direction upper part;

In this second semiconductor pattern underlapped with this second grid on this upright projection direction, form the 3rd doped region and the 4th doped region, and this storage capacitors bottom electrode is adulterated;

Carry out an ashing processes to remove this second photoresist layer;

Remove this first barrier pattern; And

Remove this first photoresist layer and the 3rd photoresist layer.

8. the method for making display floater according to claim 7, it is characterized in that, this second patterned conductive layer more comprises one the 3rd grid, is arranged in this second thin film transistor region, and the 3rd grid to be formed on this second grid and to contact with this second grid.

9. the method for making display floater according to claim 1, is characterized in that, separately comprise:

This first grid of removal part exposes this first semiconductor pattern partly further to reduce the size of this first grid; And

One first light doping section and one second light doping section is formed in this first semiconductor pattern underlapped with this first grid of reduction on this upright projection direction, wherein this first light doping section and this second light doping section have this first doping type, and the doping content of this first light doping section and this second light doping section is less than the doping content of this first doped region and this second doped region.

10. the method for making display floater according to claim 1, is characterized in that, separately comprise:

A luminescent layer is formed on this pixel electrode; And

A counter electrode is formed on this luminescent layer.

The method of 11. making display floaters according to claim 1, is characterized in that, is separately included on this pixel electrode and forms a liquid crystal layer.

12. 1 kinds of display floaters, comprising:

One substrate, this substrate has a picture element region and a first film transistor area;

One first semiconductor pattern, being arranged on this substrate and being positioned at this first film transistor area, wherein this first semiconductor pattern has one first doped region and one second doped region, and this first doped region and this second doped region have one first doping type;

One insulating barrier, to be positioned on this substrate and to cover this first semiconductor pattern;

One pixel electrode, to be arranged on this insulating barrier and to be positioned at this picture element region;

One first grid, to be arranged on this insulating barrier and to be positioned at this first film transistor area, wherein this first grid this first doped region underlapped and this second doped region on a upright projection direction;

One dielectric layer, cover this insulating barrier, this pixel electrode and this first grid, wherein this dielectric layer and this insulating barrier have one first opening portion and expose this first doped region and one second opening portion and expose this second doped region, and this dielectric layer has one the 3rd opening portion and exposes this switching electrode;

13. display floaters according to claim 12, is characterized in that, this pixel electrode comprises a transparency electrode, and this switching electrode comprises an opaque electrode.

14. display floaters according to claim 12, is characterized in that, separately comprise a protective layer and are arranged on this dielectric layer, and cover this first source electrode and this first drains, and wherein this protective layer and this dielectric layer have one the 4th opening, expose this pixel electrode.

15. display floaters according to claim 14, is characterized in that, this substrate has more one second thin film transistor region and a storage capacitors district, and this display floater more comprises:

One second semiconductor pattern, to be arranged on this substrate and to be positioned at this second thin film transistor region, wherein this second semiconductor pattern has one the 3rd doped region and one the 4th doped region, and the 3rd doped region and the 4th doped region have the second doping type that is different from this first doping type;

One second source electrode, being arranged on this dielectric layer and being positioned at this second thin film transistor region, this second source electrode and the 3rd doped region are electrically connected; And

One second drain electrode, to be arranged on this dielectric layer and to be positioned at this second thin film transistor region, and this second drain electrode is electrically connected with the 4th doped region.

16. display floaters according to claim 15, is characterized in that, separately comprise a second grid, to be arranged on this insulating barrier and to be positioned at this second thin film transistor region.

17. display floaters according to claim 16, is characterized in that, this second grid comprises an opaque electrode.

18. display floaters according to claim 16, is characterized in that, this second grid comprises a transparency electrode.

19. display floaters according to claim 15, it is characterized in that, separately comprise a second grid and one the 3rd grid, to be arranged on this insulating barrier and to be positioned at this second thin film transistor region, wherein this second grid comprises a transparency electrode, 3rd grid comprises an opaque electrode, and the 3rd grid to be arranged on this second grid and to contact with this second grid.

20. display floaters according to claim 12, it is characterized in that, this first semiconductor pattern has more one first light doping section and one second light doping section, this first light doping section and this second light doping section are not overlapping with this first grid on this upright projection direction, this first light doping section and this second light doping section have this first doping type, and the doping content of this first light doping section and this second light doping section is less than the doping content of this first doped region and this second doped region.

21. display floaters according to claim 12, is characterized in that, separately comprise:

One luminescent layer, is arranged on this pixel electrode; And

One counter electrode, is arranged on this luminescent layer.

22. display floaters according to claim 12, is characterized in that, separately comprise a liquid crystal layer, are arranged on this pixel electrode.