CN111415963A

CN111415963A - Display panel and preparation method thereof

Info

Publication number: CN111415963A
Application number: CN202010260744.2A
Authority: CN
Inventors: 贺晖
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2020-07-14
Anticipated expiration: 2040-04-03
Also published as: CN111415963B

Abstract

The invention provides a display panel and a preparation method thereof. The display panel comprises an array substrate, a light absorption layer, a filter layer and a light emitting layer. The array substrate is provided with a plurality of metal wiring areas and a display area surrounding the metal wiring areas. The light absorption layer is arranged on the array substrate and corresponds to the metal wiring area. The filter layer is arranged on the array substrate, is positioned in the display area and is positioned on the same layer as the light absorption layer.

Description

Display panel and preparation method thereof

Technical Field

The invention relates to the field of display devices, in particular to a display panel and a preparation method thereof.

Background

Among them, the Organic light Emitting Diode (Organic L light-Emitting Diode, O L ED) display technology is a flat panel display technology with great development prospect, it has very excellent display performance, especially self-luminescence, simple structure, ultra-Thin and light, fast response speed, wide viewing angle, low power consumption and can realize flexible display, so it is known as "dream display", and its production equipment investment is far less than that of Thin Film Transistor liquid crystal display (Thin Film Transistor-L ideal crystal display, TFT-L CD), so it has gained favor of various large display manufacturers, and has become the main power of the third generation display device in the field of display technology.

In order to realize full Color of the O L ED display, one mode is realized By a Side-By-Side structure in which red, green and blue (RGB) sub-pixels respectively emit light, and the other mode is realized By a series structure in which white organic light Emitting diodes (WO L ED) and Color Filter (CF) layers are stacked.

The COA type WO L ED is a combination of COA (CF on Array, color filter attached to Array substrate) technology and WO L ED technology, the COA technology is utilized to make a CF layer on the Array substrate, then white light emitted by an O L ED white light material passes through an RGB light resistance in the CF layer to obtain light of three primary colors of RGB, compared with a traditional bottom-emitting O L ED structure, the technology is not limited by an organic evaporation mask in the manufacture of a large-size panel, and therefore, the technology has wide application in the aspect of large-size O L ED.

When the COA type WO L ED with bottom emission emits light, light needs to pass through the P L N layer (flat layer) and the RGB photoresist, and since the bottom emission P L N is generally a highly transparent organic material, the light is multi-directional in light propagation, and the light is reflected by the cathode and the metal wiring to illuminate the opening edge of the adjacent pixel defining layer, so that the sub-pixel which does not need to emit light emits light due to the light emission of the adjacent sub-pixel, and the light leakage phenomenon occurs, which affects the display of the picture.

Disclosure of Invention

The invention aims to provide a display panel and a preparation method thereof, and aims to solve the problem that in the prior art, light is reflected by a cathode and a metal wire to illuminate the edge of an opening of an adjacent pixel limiting layer, so that sub-pixels which do not need to emit light often emit light due to light leakage.

In order to achieve the above object, the present invention provides a display panel, which includes an array substrate, a light absorbing layer, a filter layer, and a light emitting layer. The array substrate is provided with a plurality of metal wiring areas and a display area surrounding the metal wiring areas. The light absorption layer is arranged on the array substrate and corresponds to the metal wiring area. The filter layer is arranged on the array substrate, is positioned in the display area and is positioned on the same layer as the light absorption layer. The light emitting layer is arranged on the filter layer.

Furthermore, the light absorption layer comprises a first color resistance layer and a second color resistance layer, and the second color resistance layer is arranged on the first color resistance layer. The color of the first color resistance layer is one of red, green and blue. The color of the second color resistance layer is one of red, green and blue. The color of the first color resistance layer is different from that of the second color resistance layer.

Furthermore, the array substrate comprises a substrate, an active layer, a gate insulating layer, a gate layer, a dielectric layer and a source drain. The active layer is arranged on the substrate, the grid electrode insulating layer is arranged on one surface, far away from the substrate, of the active layer, the grid electrode layer is arranged on one surface, far away from the active layer, of the grid electrode insulating layer, the dielectric layer covers the active layer, the grid electrode insulating layer and the grid electrode layer, and the source electrode and the drain electrode are arranged on one surface, far away from the grid electrode layer, of the dielectric layer and correspond to the metal wiring area.

Further, the width of the metal routing area is smaller than that of the light absorption layer.

Further, the color of the filter layer is at least one of red, green and blue.

Further, the display panel further comprises a flat layer, a pixel electrode layer and a pixel defining layer. The flat layer covers the array substrate, the light absorbing layer and the filter layer. The pixel electrode layer is arranged on one surface, far away from the array substrate, of the flat layer and penetrates through the light absorption layer to be connected with the array substrate. The pixel defining layer overlies the planarization layer and the pixel electrode layer. The pixel limiting layer is provided with an opening, the through hole corresponds to the pixel electrode layer, and the light emitting layer is arranged in the through hole and connected with the pixel electrode.

Further, the thickness of the light absorbing layer is less than or equal to the thickness of the flat layer.

The invention also provides a preparation method of the display panel, which comprises the following steps:

preparing an array substrate, wherein the array substrate is provided with a plurality of metal wiring areas and a display area surrounding the metal wiring areas. And forming a filter layer and a light absorption layer on the array substrate, wherein the light absorption layer corresponds to the metal wiring area, and the filter layer is positioned in the display area. And forming a light emitting layer on the filter layer.

Further, the step of forming a light absorbing layer on the array substrate includes: and forming the filter layer and the light absorption layer on the substrate by adopting three sections of differential photomasks, and forming a through hole in the light absorption layer. In the three sections of differential photomasks, the light transmittance corresponding to the display area is 100%, the light transmittance corresponding to the metal wiring area is 20-50%, and the light transmittance corresponding to the via hole is 0%.

Further, the step of forming the filter layer and the step of forming the light emitting layer include the following steps:

forming a planarization layer on the array substrate, the light absorbing layer, and the filter layer. And forming a pixel electrode layer on the flat layer.

The invention has the advantages that: according to the display panel and the preparation method thereof, the light absorption layer is added on the source and drain electrodes, and light reflected by the source and drain electrodes is absorbed and filtered through the light absorption layer, so that the problem of light leakage caused by reflection of metal wiring is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a layer structure of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the layered structure of the display panel in step S10 according to the embodiment of the present invention;

FIG. 4 is a schematic diagram of the layered structure of the display panel in step S20 according to the embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating the layered structure of the display panel in step S30 according to an embodiment of the present invention;

fig. 6 is a schematic diagram of the layered structure of the display panel in step S40 according to the embodiment of the present invention.

A display panel 100;

a metal routing area 101; a display area 102;

an array substrate 110; a substrate 111;

a light-shielding layer 112; a buffer layer 113;

an active layer 114; a gate insulating layer 115;

a gate layer 116; a dielectric layer 117;

source and drain electrodes 118; a passivation layer 119;

a filter layer 120; a light absorbing layer 130;

a first color resist layer 131; a second resist layer 132;

a via 133; a planarization layer 140;

a pixel electrode layer 150; a pixel defining layer 160;

an opening 161; a light emitting layer 170.

Detailed Description

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, which are included to demonstrate that the invention can be practiced, and to provide those skilled in the art with a complete description of the invention so that the technical content thereof will be more clear and readily understood. The present invention may be embodied in many different forms of embodiments and should not be construed as limited to the embodiments set forth herein.

In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.

Furthermore, the following description of the various embodiments of the invention refers to the accompanying drawings that illustrate specific embodiments of the invention, by which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

When certain components are described as being "on" another component, the components can be directly on the other component; there may also be an intermediate member disposed on the intermediate member and the intermediate member disposed on the other member. When an element is referred to as being "mounted to" or "connected to" another element, they may be directly "mounted to" or "connected to" the other element or indirectly "mounted to" or "connected to" the other element through an intermediate element.

The embodiment of the invention provides a display device, which is a WO L ED (White Organic L light-Emitting Diode) display device, and the display device is provided with a display panel 100, wherein the display panel 100 provides a display picture for the display device, and the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer and the like.

As shown in fig. 1, the display panel 100 includes an array substrate 110, a light-absorbing layer 130, a filter layer 120, and a light-emitting layer 170.

The array substrate 110 has a plurality of metal routing areas 101 and a display area 102 surrounding the metal routing areas 101. The array substrate 110 further includes a substrate 111, a light-shielding layer 112, a buffer layer 113, an active layer 114, a gate insulating layer 115, a gate layer 116, a dielectric layer 117, a source/drain electrode 118, a passivation layer 119, and a planarization layer 140.

The substrate 111 may be an insulating substrate such as a glass substrate or a quartz substrate, and is used to protect the entire mechanism of the display panel 100.

The light-shielding layer 112 is provided on the substrate 111, and is made of a light-shielding material having conductivity, for example, a metal material such as aluminum, silver, molybdenum, or copper. Since the active layer 114 is very sensitive to light, after the active layer 114 is irradiated by light, the threshold voltage in the display panel 100 can be shifted significantly negatively, and therefore, by disposing the light shielding layer 112 under the active layer 114, the light entering from the substrate 111 side is shielded by the active layer 114, so that the phenomenon of the negative drift of the threshold voltage in the display panel 100 caused by light is solved.

The buffer layer 113 covers the light-shielding layer 112 and the substrate 111, and includes one or more inorganic materials such as silicon oxide and silicon nitride. The buffer layer 113 serves to insulate the light-shielding layer 112 from the active layer 114, and also has a buffer function to prevent devices in the display panel 100 from being damaged by impact.

The active layer 114 is disposed on a surface of the buffer layer 113 away from the light-shielding layer 112, and corresponds to the light-shielding layer 112. the active layer 114 may be one of semiconductor materials such as amorphous silicon (a-Si), low temperature polysilicon (L TPS), and metal oxide (IGZO).

The gate insulating layer 115 is disposed on a surface of the active layer 114 away from the buffer layer 113, and includes one or more inorganic materials such as silicon oxide and silicon nitride. The gate insulating layer 115 serves to insulate the active layer 114 from the gate layer 116, thereby preventing a short circuit from occurring.

The gate layer 116 is disposed on a surface of the gate insulating layer 115 away from the active layer 114, and the material thereof includes a material with high conductivity, such as a metal material, e.g., aluminum, silver, copper, etc.

The dielectric layer 117 covers the buffer layer 113, the active layer 114, the gate insulating layer 115 and the gate electrode layer 116, and the material thereof includes one or more of inorganic materials such as silicon oxide and silicon nitride. The dielectric layer 117 protects the gate layer 116 with insulation.

The source/drain electrode 118 is disposed on a surface of the dielectric layer 117 away from the gate layer 116, and corresponds to the metal routing area 101 of the array substrate 110. Meanwhile, the source and drain electrodes 118 are connected to both ends of the active layer 114 through the dielectric layer 117. The source and drain 118 is made of metal with excellent conductivity.

The passivation layer 119 covers the source and drain electrodes 118 and the dielectric layer 117, and the planarization layer 140 covers a surface of the passivation layer 119 away from the source and drain electrodes 118. The passivation layer 119 and the planarization layer 140 both include inorganic materials such as silicon oxide and silicon nitride. The passivation layer 119 is used for passivating the surface of the source and drain electrode 118 and insulating and protecting the source and drain electrode 118. The planarization layer 140 is used to planarize the surface of the real substrate 111.

The pixel electrode layer 150 is disposed on a surface of the planarization layer 140 away from the passivation layer 119, and is electrically connected to the source/drain electrode 118 through the planarization layer 140, the light absorbing layer 130, and the passivation layer 119. The pixel electrode layer 150 is made of a transparent conductive material, such as ITO (Indium Tin Oxide).

The pixel defining layer 160 is formed of a photosensitive organic photoresist material, and covers the pixel electrode layer 150 and the passivation layer 119. An opening 161 is provided in the pixel defining layer 160, and the opening 161 penetrates the pixel defining layer 160 onto the surface of the pixel electrode layer 150. The pixel defining layer 160 is used to define a light emitting region, and the opening 161 is the light emitting region.

The light-Emitting layer 170 is disposed on the pixel electrode layer 150 in the opening 161, and is WO L ED (white organic light-Emitting Diode) for providing a display light source.

When the gate electrode is energized with a current and a voltage, an electric field is generated, and the electric field can promote the surface of the active layer 114 to generate induced charges, so that the width of a conductive channel in the active layer 114 is changed, and the purpose of controlling the current of the source/drain electrode 118 is achieved. The pixel electrode layer 150 is electrically connected to the source and drain electrodes 118, and the active layer 114 controls the brightness of the light-emitting layer 170 connected to the pixel electrode layer 150 by controlling the current of the source and drain electrodes 118.

The filter layer 120 is disposed between the passivation layer 119 and the planarization layer 140, and is located in the display area 102 of the array substrate 110 and corresponds to the light emitting layer 170. The filter layer 120 is at least one of a red photoresist, a green photoresist, or a blue photoresist, and is configured to filter white light emitted from the light emitting layer 170, filter the white light into one of red light, green light, and blue light, and implement color display by using the principle of three primary colors.

The light absorbing layer 130 is also disposed between the passivation layer 119 and the planarization layer 140, and is located at the same layer as the filter layer 120. The light absorbing layer 130 corresponds to the metal routing area 101 of the array substrate 110, i.e., corresponds to the source/drain 118. The light absorbing layer 130 includes a first color resist layer 131 and a second color resist layer 132. The first color resist layer 131 is disposed on the passivation layer 119, and has one of red, green, and blue colors. The second color resist layer 132 is disposed on a surface of the first color resist layer 131 away from the passivation layer 119, and has a color of one of red, green, and blue. The colors of the first color resist layer 131 and the second color resist layer 132 are different, the thickness of the light absorbing layer 130 is less than or equal to the thickness of the planarization layer 140, and the width of the metal routing area 101 is less than the width of the light absorbing layer 130.

Specifically, in the embodiment of the present invention, the color of the filter layer 120 is red photoresist, the color of the first photoresist layer 131 is red, and the color of the second photoresist layer 132 is green. The white light emitted from the light emitting layer 170 passes through the filter layer 120 and becomes red light. A portion of the red light is emitted onto the source and drain electrodes 118, and is reflected because the source and drain electrodes 118 are metal. The light absorption layer 130 is disposed on the source/drain 118, the second color resist layer 132 is green, and the red light cannot penetrate through the green second color resist layer 132, so that the light reflected by the source/drain 118 in the metal routing area 101 is absorbed and filtered by the light absorption layer 130, thereby preventing light leakage.

The embodiment of the present invention provides a method for manufacturing the display panel 100, wherein the flow of the method is shown in fig. 2, and the method includes the following specific steps:

step S10) as shown in fig. 3, an array substrate 110 is prepared:

a substrate 111 is provided, and the substrate is an insulating substrate.

A light-shielding material and an inorganic material are sequentially deposited on the substrate 111, respectively, to form the light-shielding layer 112 and the buffer layer 113.

A layer of amorphous silicon or metal oxide material is deposited on a surface of the buffer layer 113 away from the light-shielding layer 112, and then exposed through a mask and patterned by etching, forming the active layer 114.

The gate insulating layer 115 is formed by depositing a layer of an inorganic material on the active layer 114.

A layer of conductive metal material is formed on the gate insulating layer 115 to form the gate layer 116.

The buffer layer 113, the active layer 114, the gate insulating layer 115 and the gate electrode layer 116 are deposited with a layer of inorganic material to form the dielectric layer 117.

Forming a through hole in the dielectric layer 117 by using a photolithography technique, depositing a layer of conductive metal material again corresponding to the two ends of the active layer 114, and patterning the conductive metal material to form the source/drain electrode 118, wherein the source/drain electrode 118 is located in the metal routing area 101 of the array substrate 110. Wherein the source and drain electrodes 118 fill the via holes and are connected to the active layer 114.

A layer of inorganic material is deposited over the source and drain electrodes 118 and the dielectric layer 117 to form the passivation layer 119.

Step S20) as shown in fig. 4, the filter layer 120 and the light absorbing layer 130 are formed: a photoresist is coated on the array substrate 110, and then the filter layer 120 and the light absorbing layer 130 are formed on the substrate 111 through a three-step-difference mask, and a via hole 133 is formed in the light absorbing layer 130. In the three-step difference photomask, the light transmittance corresponding to the display region 102 is 100%, the light transmittance corresponding to the metal wiring region 101 is 20-50%, and the light transmittance corresponding to the via hole 133 is 0%.

Step S30) as shown in fig. 5, the planarization layer 140 is formed: a layer of inorganic material is coated on the array substrate 110, the light absorbing layer 130 and the filter layer 120, and patterned by photolithography, and the inorganic material corresponding to the via hole 133 is etched away to form the planarization layer 140.

Step S40) as shown in fig. 6, the pixel electrode layer 150 and the pixel defining layer 160 are formed:

forming and preparing a layer of ITO material on the flat layer 140, filling the via hole 133 with the ITO material to connect with the source/drain electrode 118, and patterning the ITO material by an etching technique to form the pixel electrode layer 150.

A layer of inorganic material is deposited on the pixel electrode layer 150 and the planarization layer 140, and patterned, and an opening 161 is formed at a position corresponding to the pixel electrode layer 150 to form the pixel defining layer 160.

Step S50) of forming the light emitting layer 170, the light emitting layer 170 is prepared in the opening 161 by the WO L ED process, and finally the display panel 100 shown in fig. 1 is formed.

The embodiment of the present invention provides a display panel 100, wherein a light absorption layer 130 is prepared on a source/drain electrode 118, and at least one of a first color resist layer 131 and a second color resist layer 132 in the light absorption layer 130 has a color different from that of light filtered by the filter layer 120, so that light reflected by the source/drain electrode 118 can be filtered and absorbed again, thereby preventing light leakage. Moreover, the preparation method of the display panel 100 is simple, the process is short, and no new preparation equipment is required to be added.

In other embodiments, the filter layer 120 may also be a green photoresist or a blue photoresist, and the first color resist layer 131 and the second color resist layer 132 may also be a combination of green and blue or a combination of red and blue, which have similar structures to those disclosed in the embodiments of the present invention, and therefore, will not be described herein in detail. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. A display panel, comprising:

the array substrate is provided with a plurality of metal wiring areas and a display area surrounding the metal wiring areas;

the light absorption layer is arranged on the array substrate and corresponds to the metal wiring area;

the filter layer is arranged on the array substrate, is positioned in the display area and is positioned on the same layer as the light absorption layer;

and the light emitting layer is arranged on the filter layer.

2. The display panel of claim 1, wherein the light absorbing layer comprises a first color-resist layer and a second color-resist layer, and the second color-resist layer is disposed on the first color-resist layer; the color of the first color resistance layer is one of red, green and blue; the color of the second color resistance layer is one of red, green and blue; the color of the first color resistance layer is different from that of the second color resistance layer.

3. The display panel of claim 1, wherein the array substrate comprises:

a substrate;

an active layer disposed on the substrate;

the grid insulation layer is arranged on one surface of the active layer, which is far away from the substrate;

the grid electrode layer is arranged on one surface of the grid electrode insulating layer far away from the active layer;

a dielectric layer overlying the active layer, the gate insulating layer and the gate layer;

and the source and drain electrodes are arranged on one surface of the dielectric layer, which is far away from the grid layer, and correspond to the metal wiring area.

4. The display panel of claim 1, wherein the width of the metal routing area is less than the width of the light absorbing layer.

5. The display panel according to claim 1, wherein a color of the filter layer is at least one of red, green, and blue.

6. The display panel of claim 1, further comprising:

a flat layer overlying the array substrate, the light absorbing layer and the filter layer;

the pixel electrode layer is arranged on one surface of the flat layer, which is far away from the array substrate, and penetrates through the light absorption layer to be connected with the array substrate;

a pixel defining layer overlying the planarization layer and the pixel electrode layer;

the pixel defining layer is provided with a through hole, and the through hole corresponds to the pixel electrode layer;

the light emitting layer is arranged in the through hole and connected with the pixel electrode.

7. The display panel of claim 6, wherein the light absorbing layer has a thickness equal to or less than a thickness of the planarization layer.

8. A preparation method of a display panel is characterized by comprising the following steps:

preparing an array substrate, wherein the array substrate is provided with a plurality of metal wiring areas and a display area surrounding the metal wiring areas;

forming a light filtering layer and a light absorbing layer on the array substrate, wherein the light absorbing layer corresponds to the metal wiring area, and the light filtering layer is positioned in the display area;

and forming a light emitting layer on the filter layer.

9. The method of manufacturing a display panel according to claim 8, wherein the step of forming a light absorbing layer on the array substrate includes: forming the filter layer and the light absorption layer on the substrate by using three sections of differential photomasks, and forming a through hole in the light absorption layer;

in the three sections of differential photomasks, the light transmittance corresponding to the display area is 100%, the light transmittance corresponding to the metal wiring area is 20-50%, and the light transmittance corresponding to the via hole is 0%.

10. The method for manufacturing a display panel according to claim 8, wherein the step of forming the filter layer and the step of forming the light emitting layer include the steps of:

forming a planarization layer on the array substrate, the light absorbing layer, and the filter layer;

and forming a pixel electrode layer on the flat layer.