CN107706098B - Method for forming doped region, thin film transistor and manufacturing method thereof - Google Patents
Method for forming doped region, thin film transistor and manufacturing method thereof Download PDFInfo
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- CN107706098B CN107706098B CN201710840415.3A CN201710840415A CN107706098B CN 107706098 B CN107706098 B CN 107706098B CN 201710840415 A CN201710840415 A CN 201710840415A CN 107706098 B CN107706098 B CN 107706098B
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000010409 thin film Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 96
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 92
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011248 coating agent Substances 0.000 claims abstract description 6
- 238000000576 coating method Methods 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The invention discloses a method for forming a doped region, a thin film transistor and a manufacturing method thereof, wherein the method for forming the doped region comprises the following steps: coating a first photoresist on a substrate; performing a photomask on the first photoresist to form a first ion doping area, and injecting ions with a first energy value into the first ion doping area; removing the second photoresist to form a third photoresist; and etching the third photoresist to form a second ion doping area, and injecting ions with a second energy value into the second ion doping area, wherein the first energy value is higher than the second energy value. By the method, the process steps are reduced, the complexity of the process is reduced, and therefore the production efficiency and the product quality can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a doped region, a thin film transistor, and a method for fabricating the thin film transistor.
Background
At present, a thin film transistor is widely used as a driving device in a liquid crystal display, and generally, the thin film transistor includes a gate insulating layer, a gate electrode, a source electrode, a drain electrode, an oxide semiconductor film layer, and a passivation layer, wherein the source electrode and the drain electrode are separated by a channel. The source and the drain can be in a conducting (on) or insulating (off) state by controlling the voltage of the grid, and the switching characteristic is utilized to drive the on-off of different pixel areas in the liquid crystal display.
Low Temperature polysilicon Thin film transistors (LTPS TFTs) have Low power consumption, Low electromagnetic interference and high mobility characteristics and are widely used in high-quality, fully integrated display panels. LTPS-TFTs, however, typically have high off-state currents due to carrier emission caused by traps and defect states at the grain-gaps and band-to-band tunneling occurring in the channel near the drain region. This off-state current causes a slight voltage change to affect the quality of the display. Therefore, in order to reduce the off-state current of the tft, an ion implantation technique using an ldd (light Doped drain) lightly Doped drain is generally used to provide a lightly Doped region in the channel near the source region and the drain region, so as to form an ion concentration buffer region, which can bear a portion of the voltage of the source region and the drain region, reduce the fringe electric field gradient of the source and the drain, and alleviate the leakage current generated by the enhancement of the electric field, thereby avoiding the hot carrier effect.
At present, in the prior art, on one hand, a MASK (photo MASK) preparation method is mainly adopted, the length of the ion buffer area is defined through twice photoresists, the method needs to use two photomasks, the process steps are relatively complicated, and the size precision of the ion buffer area is easily influenced by MASK contraposition offset. On the other hand, a GE Re-Etch (Gate Electrode Re-Etch) preparation method is mainly adopted, the length of the ion buffer area is defined through one photomask and two times of GE Etch, the method can omit one photomask, but the requirement of metal etching on equipment is high, the size precision of the ion buffer area is difficult to control, and the technical difficulty is high. However, the size of the ion buffer is related to the lateral and depth doping concentration profile of the lightly doped ions, which determines the amount of leakage current and the lifetime of the device.
Disclosure of Invention
The invention mainly solves the technical problem of providing a forming method of a doped region, a thin film transistor and a manufacturing method thereof, which reduce the process steps, reduce the process complexity and improve the production efficiency and the product quality.
In order to solve the technical problems, the first technical scheme adopted by the invention is as follows: the forming method of the doped region is applied to the process of preparing a thin film transistor and comprises the following steps: coating a first photoresist on a substrate; performing a photomask on the first photoresist to form a first ion doping area, and injecting ions with a first energy value into the first ion doping area; removing the second photoresist to form a third photoresist, wherein the second photoresist is a hardened photoresist formed by the first photoresist in the process of injecting ions with a first energy value into the first ion doping area; and etching the third photoresist to form a second ion doping area, and injecting ions with a second energy value into the second ion doping area, wherein the first energy value is higher than the second energy value.
In order to solve the above technical problems, the second technical solution adopted by the present invention is: a manufacturing method of a thin film transistor is provided, the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, and the manufacturing method of the thin film transistor comprises the following steps: ions are doped between the grid electrode and the source electrode and/or between the grid electrode and the drain electrode through the forming method of the doped region.
In order to solve the above technical problems, the second technical solution adopted by the present invention is: the invention provides a thin film transistor which is prepared by the manufacturing method of the thin film transistor.
The invention has the beneficial effects that: the invention combines the photomask technology and the etching technology to form the lightly doped region without carrying out multiple times of alignment, thereby improving the dimensional precision of the ion buffer region. Meanwhile, the doped region is not required to be defined by a metal etching technology, so that the bottleneck of a metal etching process is avoided. The invention reduces the process steps and the complexity of the process, thereby improving the production efficiency and the product quality.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for forming a doped region according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a first process structure after a first photoresist coating step has been performed on a substrate;
FIG. 3 is a cross-sectional view of a second process structure, at which the formation of a first ion-doped region into which ions having a first energy value are implanted has been completed;
FIG. 4 is a cross-sectional view of a third process in which the second photoresist has been removed to form a third photoresist;
FIG. 5 is a cross-sectional view of a fourth process, wherein the third photoresist is etched to form a second ion-doped region, and ions with a second energy value are implanted into the second ion-doped region;
FIG. 6 is a flow chart illustrating a method for fabricating a thin film transistor according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
Detailed Description
The present invention provides a method for forming a doped region, a thin film transistor and a method for fabricating the same, and in order to make the objects, technical solutions and effects of the present invention more clear and clearer, the present invention will be described in further detail below, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for forming a doped region according to an embodiment of the present invention. The method for forming the doped region of the present embodiment includes the steps of:
101: a first photoresist is coated on the substrate.
The substrate mainly plays a role in supporting in this embodiment, and may be a quartz substrate and a glass substrate, or may be other substrates, such as a plastic substrate, and may be designed according to specific situations, which is not limited herein.
The first photoresist is a photoresist comprising a photoresist material, and may be a positive photoresist or a negative photoresist, which may be designed according to specific situations, and is not limited herein.
In this embodiment, the first photoresist is taken as a forward photoresist for explanation. Referring to FIG. 2, FIG. 2 is a cross-sectional view of a first process structure, wherein the step of coating a first photoresist on the substrate is completed. The first photoresist 2 is coated on the substrate.
102: and carrying out photomask on the first photoresist to form a first ion doping area, and injecting ions with a first energy value into the first ion doping area.
Referring to fig. 3 and fig. 2, fig. 3 is a cross-sectional view of a second process structure, in which a step of forming a first ion-doped region and implanting ions having a first energy value into the first ion-doped region is completed.
The photo mask is aligned on the first photo resist 2, part of the photo resist is aligned and exposed through the light source of the photo mask, and the exposed photo resist is removed by the developing solution to form a first ion doping area 4. The first ion doped region 4 of the present embodiment is only for the purpose of more intuitively explaining the method of the present embodiment, and the position, shape or size of the first ion doped region 4 cannot be limited, and a corresponding mask can be selected according to actual conditions to define a corresponding doped region.
Ions of a first energy value are implanted into the first ion doping region 4 by an ion implantation technique. The first energy value is a preset energy value of the implanted ions, and may be designed according to specific situations, which is not limited herein. The implanted ions may be one or more of phosphorus, boron and arsenic.
Since the energy of the ions implanted into the first ion doping region 4 is relatively high, the surface of the exposed and developed residual resistor of the first photoresist 2 reacts to form the second photoresist 3 (i.e., hardened photoresist).
103: and removing the second photoresist to form a third photoresist, wherein the second photoresist is a hardened photoresist formed by the first photoresist in the process of injecting ions with a first energy value into the first ion doping area.
Referring to fig. 3 and 4, fig. 4 is a cross-sectional view of a third process, in which the second photoresist is removed to form a third photoresist.
In this embodiment, the first ion-doped region 4 is obtained by the above steps. The second photoresist 3 is removed by etching techniques to form a third photoresist 5. The etching technique is a technique of removing a part of a thin film layer not masked by a resist to form a pattern identical to that of the resist film on the thin film layer. The etching technique includes dry etching and wet etching, which can be designed according to specific situations and is not limited herein.
104: and etching the third photoresist to form a second ion doping area, and injecting ions with a second energy value into the second ion doping area, wherein the first energy value is higher than the second energy value.
Referring to fig. 5 and fig. 4, fig. 5 is a schematic cross-sectional view of a fourth process, in which the third photoresist is etched to form a second ion-doped region, and ions with a second energy value are implanted into the second ion-doped region. And etching part of the third photoresist 5 by an etching technique to form a second ion-doped region 6. However, the second ion-doped region 6 of the present embodiment is only for more intuitively explaining the method of the present embodiment, and the position, shape, or size of the second ion-doped region 6 is not limited, and the corresponding doped region may be defined according to actual conditions.
Ions of a second energy value are implanted into the second ion doped region 6 by an ion implantation technique. The second energy value is an energy value of the implanted ions, which is preset, and is not limited herein, and is preferably 15Kev to 30 Kev. The implanted ions may be one or more of phosphorus, boron and arsenic.
The energy of the ions implanted into the first ion doping region 4 is higher than the energy of the ions implanted into the second ion doping region 6.
It should be emphasized that, in the present embodiment, the second photoresist 3 and the third photoresist 5 are both formed after the first photoresist 2 is completed with the corresponding steps of the method for forming the doped region. Specifically, the second photoresist 3 is a hardened photoresist formed by reacting the surface of the first photoresist 2 during the process of implanting ions into the first ion doping region 4. The third photoresist 5 is the portion remaining after the second photoresist 3 is removed (i.e., hardened photoresist).
The method and the device have the advantages that the prior art is distinguished, the doped region is formed by combining the photomask technology and the etching technology, multiple times of alignment is not needed, and the size precision of the ion buffer region is improved. Meanwhile, the doped region is not required to be defined by a metal etching technology, so that the bottleneck of a metal etching process is avoided. The invention reduces the process steps and the complexity of the process, thereby improving the production efficiency and the product quality.
In another embodiment, the method for forming the doped region according to any of the above embodiments may be applied to a process for manufacturing a thin film transistor, wherein the thin film transistor includes a gate electrode, a source electrode and a drain electrode. In one embodiment, ions are doped in the gate electrode of the thin film transistor and the source electrode of the thin film transistor and the gate electrode of the thin film transistor and the source electrode of the thin film transistor by the method for forming the doped region according to any one of the above embodiments. In another embodiment, ions are doped in the gate electrode of the thin film transistor and the source electrode of the thin film transistor or the gate electrode of the thin film transistor and the source electrode of the thin film transistor by the method for forming the doped region according to any one of the above embodiments.
The ions may be one or more of phosphorus, boron, and arsenic, and the doped ions may be selected according to different types of thin film transistors, and may be designed according to actual situations, which is not specifically limited herein.
In one embodiment, the energy of the doped ions is 15Kev to 30Kev, and the specific doping energy value can be designed according to practical situations, and is not limited herein.
To explain the method for fabricating the thin film transistor in this embodiment in detail, refer to fig. 6, and fig. 6 is a flow chart illustrating an embodiment of the method for fabricating the thin film transistor according to the present invention.
601: a gate electrode, a gate insulating layer and an oxide semiconductor film layer are sequentially formed on a first substrate.
Specifically, a metal film layer is formed on a first substrate by deposition, and is exposed through a photomask, and the metal film layer is etched into a gate.
The first substrate includes a glass substrate and a quartz substrate, and other substrates may be used in other embodiments, which are not limited herein.
The metal film layer includes at least one of aluminum Al, molybdenum Mo, copper Cu, and silver Ag, and may be other metals in other embodiments, which is not limited herein.
The deposition process generally refers to the deposition of foreign materials on the surface of a substrate to form a thin film, which is also called vapor deposition. In this embodiment, a metal film layer is formed on a surface of a first substrate using a metal substance. In other embodiments, the metal film layer may be implemented by other deposition methods, which are not limited herein.
The etching technique generally refers to a technique of removing a part of a thin film layer not masked by a resist on the thin film layer to form the same pattern as the resist on the thin film layer. The etching technique generally includes dry etching and wet etching, and the embodiment is not limited as long as the gate can be etched on the metal film layer.
After the grid is formed, a grid insulating layer and an oxide semiconductor film layer are deposited on the surface of the grid. The gate insulating layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx, and in other embodiments, the gate insulating layer may also be another insulating material, which is not limited herein.
The oxide semiconductor film layer is a transparent oxide including at least one of a zinc oxide ZnO group, a tin oxide SnO2 group, and an indium oxide In2O3 group, and In other embodiments, may be another transparent oxide as long as the function of the oxide semiconductor film layer In this embodiment can be achieved, and is not limited thereto.
602: and coating a first photoresist on the oxide semiconductor film layer.
The first photoresist is a photoresist comprising a photoresist material, and may be a positive photoresist or a negative photoresist, which may be designed according to specific situations, and is not limited herein.
In this embodiment, the first photoresist is taken as a forward photoresist for explanation. The first photoresist is coated on the oxide semiconductor film layer.
603: the first photoresist is masked to form a first ion doping area, ions with a first energy value are injected into the first ion doping area, and ions with the first energy value are injected into the first ion doping area to form a drain electrode and a source electrode.
The photomask is made to be shaded on the first photoresist, partial photoresist is shaded and exposed through the light source of the photomask, and the exposed photoresist is removed through developing solution to form a first ion doping area. And implanting ions with a first energy value into the first ion doping area by an ion implantation technology to form a drain electrode and a source electrode.
Because the energy of the ions implanted into the first ion doping area is relatively high, the exposed and developed surface of the residual resistor of the first photoresist reacts to form a second photoresist.
604: and removing the second photoresist to form a third photoresist, wherein the second photoresist is a hardened photoresist formed by the first photoresist in the process of injecting ions with a first energy value into the first ion doping area.
In an embodiment, the second photoresist is removed by an etching technique to form a third photoresist.
605: and etching the third photoresist to form a second ion doping area, and injecting ions with a second energy value into the ion doping area, wherein the first energy value is higher than the second energy value.
And etching part of the third photoresist by an etching technology to form a second ion doping area. Ions of a second energy value are implanted into the second ion doped region by an ion implantation technique. The second energy value is an energy value of the implanted ions, which is preset, and is not limited herein, and is preferably 15Kev to 30 Kev. The implanted ions may be one or more of phosphorus, boron and arsenic.
The etching technique is a technique of removing a part of a thin film layer not masked by a resist to form a pattern identical to that of the resist film on the thin film layer. The etching technique includes dry etching and wet etching, which can be designed according to specific situations and is not limited herein.
The energy of the ions implanted into the first ion doping region is higher than the energy of the ions implanted into the second ion doping region.
606: and etching to remove the residual photoresist on the oxide semiconductor film layer, and forming a channel on the oxide semiconductor film layer, wherein the channel separates the drain electrode from the source electrode.
In this embodiment mode, the residual photoresist on the oxide semiconductor film layer is etched away, and a channel is formed in the oxide semiconductor film layer, the channel separating the drain from the source.
607: an insulating passivation layer is formed and a contact electrode is disposed.
After the grid electrode, the source electrode and the drain electrode of the oxide layer thin film transistor are formed, an insulating passivation layer is deposited on the surface of the oxide layer thin film transistor, and a contact through hole is formed on the insulating passivation layer through etching of the photomask.
And forming a contact electrode in the contact through hole by using a photomask.
The insulating passivation layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx, and in other embodiments, the insulating passivation layer may also be another insulating passivation substance having the same property, which is not limited herein. The touch control electrode is an indium tin oxide ITO electrode, and in other embodiments, the ITO electrode may be replaced with another electrode according to needs, which is not limited herein.
To more intuitively describe the thin film transistor manufactured by the above embodiment, referring to fig. 7, fig. 7 is a schematic cross-sectional view of the structure of an embodiment of the thin film transistor manufactured by the manufacturing method of the thin film transistor of fig. 6.
The thin film transistor 70 includes a first substrate 701, a gate electrode 702 disposed on the first substrate 701, a gate insulating layer 703 disposed on the gate electrode 702, an oxide semiconductor film layer 704 disposed on the gate insulating layer 703, a drain electrode 705 disposed on the oxide semiconductor film layer 704, a source electrode 706, an ion-doped region 707, a channel 708, an ion-doped region 709, a passivation layer 710, and a contact electrode 711.
Different from the prior art, the light doping area is formed by combining the photomask technology and the etching technology, multiple times of alignment are not needed, and the size precision of the ion buffer area is improved. Meanwhile, the doped region is not required to be defined by a metal etching technology, so that the bottleneck of a metal etching process is avoided. The invention reduces the process steps and the complexity of the process, thereby improving the production efficiency and the product quality.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A method for forming a doped region is applied to a process for preparing a thin film transistor, and is characterized by comprising the following steps:
sequentially forming a gate electrode, a gate insulating layer and an oxide semiconductor film on a substrate;
coating a first photoresist on the oxide semiconductor film;
performing a photomask on the first photoresist, performing imagewise exposure on part of the first photoresist by using a light source of the photomask, removing the exposed part of the first photoresist to form a first ion doping area, and injecting ions with a first energy value into the first ion doping area;
removing the second photoresist through etching to form a third photoresist, wherein the second photoresist is a hardened photoresist formed by the first photoresist in the process of injecting ions with a first energy value into the first ion doping area;
etching the third photoresist to form a second ion doping area, and injecting ions with a second energy value into the second ion doping area, wherein the first energy value is higher than the second energy value; the second energy value is 15Kev-30 Kev;
depositing an insulating passivation layer on the surface of the thin film transistor, and etching the insulating passivation layer through a photomask to form a contact through hole; forming a contact electrode in the contact via using a photomask.
2. The method of claim 1, wherein the etching is dry etching.
3. The method of claim 1, wherein the etching is a wet etching.
4. The method of claim 1, wherein the ions are one or more of phosphorus, boron, and arsenic.
5. A manufacturing method of a thin film transistor, wherein the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, and the manufacturing method of the thin film transistor comprises the following steps: ions are doped between the gate and the source and/or the gate and the drain by the method of forming a doped region as claimed in any one of claims 1 to 4.
6. The method according to claim 5, wherein the ions are one or more of phosphorus, boron, and arsenic.
7. A thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 5 to 6.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060022496A (en) * | 2004-09-07 | 2006-03-10 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
| CN103021820A (en) * | 2011-09-20 | 2013-04-03 | 乐金显示有限公司 | Method of fabricating a thin film transistor and method of fabricating an organic light-emitting display device |
| CN103151388A (en) * | 2013-03-05 | 2013-06-12 | 京东方科技集团股份有限公司 | Polysilicon TFT (thin film transistor), preparation method thereof and array substrate |
| CN103227150A (en) * | 2013-03-22 | 2013-07-31 | 友达光电股份有限公司 | Display panel and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060022496A (en) * | 2004-09-07 | 2006-03-10 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
| CN103021820A (en) * | 2011-09-20 | 2013-04-03 | 乐金显示有限公司 | Method of fabricating a thin film transistor and method of fabricating an organic light-emitting display device |
| CN103151388A (en) * | 2013-03-05 | 2013-06-12 | 京东方科技集团股份有限公司 | Polysilicon TFT (thin film transistor), preparation method thereof and array substrate |
| CN103227150A (en) * | 2013-03-22 | 2013-07-31 | 友达光电股份有限公司 | Display panel and manufacturing method thereof |
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