CN1612358A - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- CN1612358A CN1612358A CN200310103325.4A CN200310103325A CN1612358A CN 1612358 A CN1612358 A CN 1612358A CN 200310103325 A CN200310103325 A CN 200310103325A CN 1612358 A CN1612358 A CN 1612358A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
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- 239000010703 silicon Substances 0.000 claims description 40
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- Thin Film Transistor (AREA)
Abstract
A thin film transistor and a manufacturing method thereof comprise: a first active layer is formed on a first thin film transistor region and comprises a channel region, a lightly doped region and a heavily doped region. A first gate insulation layer is formed on the first effective layer and comprises a central area and a shielding area, and the shielding area covers the lightly doped area of the first effective layer. A second active layer is formed on a second thin film transistor region and comprises a channel region, a lightly doped region and a heavily doped region. A second gate insulation layer is formed on the second effective layer and comprises a central area and a shielding area, and the shielding area covers the lightly doped area of the second effective layer. The lateral length of the shielding region of the first gate insulating layer is not equal to the lateral length of the shielding region of the second gate insulating layer. The lateral length of the lightly doped region of the first active layer is not equal to the lateral length of the lightly doped region of the second active layer.
Description
Technical field
The present invention is relevant for a kind of thin-film transistor (thin film transistor, TFT) technology, lightly doped drain (the lightly doped drain of relevant especially a kind of thin-film transistor, LDD) technology of structure, can be at the LDD structure of the TFT establishment of component different length of different operating voltage, also can be at the LDD structure of the asymmetric length of TFT establishment of component.
Background technology
Active matrix liquid crystal display (active matrix liquid crystal display, hereinafter to be referred as AMLCD) the picture element switch module be utilization one thin-film transistor (thin filmtransistor, TFT), generally can be divided into non-crystalline silicon tft and two kinds of patterns of multi-crystal TFT in the zone.Because the carrier transport factor integration higher, drive circuit of multi-crystal TFT is preferable, leakage current is less, so multi-crystal TFT more often is applied in the circuit of high service speed, as: static random access memory (static random access memory, SRAM).But the problem of leakage current (leakage current) easily takes place down in multi-crystal TFT in off position, and regular meeting causes LCD loss electric charge or makes the non-firm power consumption of SRAM.In order to address this problem, (lightly doped drain, LDD) structure are used for reducing the electric field of drain junction place (drainjunction), can effectively improve the phenomenon of leakage current to adopt a kind of lightly doped drain at present.Prior art is utilized the position and the size of gold-tinted program defining LDD structure mostly, but along with the reduction of TFT size of components, alignment error of gold-tinted processing procedure (photo misalignment) and considering of critical dimension skew can be more harsh.
Known a kind of method of making the LDD structure is to utilize a photoresist layer to plant processing procedure as the cover curtain to carry out a heavy doping ion cloth earlier, to form a heavily doped region in a polysilicon layer.Make a grid layer then as covering curtain to carry out a light dope ion disposing process, so that the not doped region of the exposure of polysilicon layer becomes a lightly doped region.Thus, lightly doped region is to be used as a LDD structure, and heavily doped region is to be used as one source/drain region, and the not doped region of polysilicon layer then is to be used as a channel region.Yet said method must accurately be controlled the position that the pattern of grid layer just can be guaranteed the LDD structure.And, be subject to the alignment error (photomisalignment) of exposure technique, be not easy to control the side-play amount of grid layer, then twice ion disposing process can make the problem of the offset of LDD structure can be more serious.Very and, processing procedure complexity, the production speed of said method are low, the lateral length of also wayward LDD structure.In addition, with regard to considering of circuit design, known techniques can't be at the LDD structure of different establishment of component different lengths, so can't meet the requirement on reliability and the service speed.
Summary of the invention
Automatic aligning (self-aligned) LDD structure that provides by a kind of TFT assembly and preparation method thereof just is provided purpose of the present invention, can be at the LDD structure of the TFT establishment of component different length of different operating voltage, can also be at the LDD structure of the asymmetric length of TFT establishment of component, with the requirement on Achieved Reliability and the service speed.
For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor, include a first film transistor area and one second TFT regions.One first effective layer is to be formed on this first film transistor area, and includes a channel region, a lightly doped region and a heavily doped region.One first grid insulating barrier is to be formed on this first effective layer, and includes a middle section and a shaded areas, and this middle section is the channel region that covers this first effective layer, and this shaded areas is the lightly doped region of this first effective layer of covering.One second effective layer is to be formed on this second TFT regions of this substrate, and includes a channel region, a lightly doped region and a heavily doped region.One second grid insulating barrier is to be formed on this second effective layer, and includes a middle section and a shaded areas, and this middle section is the channel region that covers this second effective layer, and this shaded areas is the lightly doped region of this second effective layer of covering.The lateral length of the shaded areas of this first grid insulating barrier is not equal to the lateral length of the shaded areas of this second grid insulating barrier.The lateral length of the lightly doped region of this first effective layer is not equal to the lateral length of the lightly doped region of this second effective layer.
For reaching above-mentioned purpose, the invention provides another kind of thin-film transistor, including an effective layer is to be formed in the substrate, and includes a channel region, a lightly doped region, one first heavily doped region and one second heavily doped region.This channel region and this lightly doped region are to be formed between this first heavily doped region and this second heavily doped region, and this lightly doped region is to be formed between this channel region and this second heavily doped region.One gate insulator is to be formed on this effective layer, and includes a middle section and a shaded areas.This middle section is to cover this effectively channel region of layer, and this shaded areas is to cover this effectively lightly doped region of layer.One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
For reaching above-mentioned purpose, the invention provides another kind of thin-film transistor, including an effective layer is to be formed in the substrate, and includes a channel region, one first lightly doped region, one second lightly doped region, one first heavily doped region and one second heavily doped region.This channel region is to be formed between this first lightly doped region and this second lightly doped region, this first lightly doped region is to be formed between this channel region and this first heavily doped region, this second lightly doped region is to be formed between this channel region and this second heavily doped region, and the lateral length of this first lightly doped region is the lateral length that is not equal to this second lightly doped region.One gate insulator is to be formed on this effective layer, and includes a middle section, one first shaded areas and one second shaded areas.This middle section is to cover this effectively channel region of layer, this first shaded areas is to cover this effectively first lightly doped region of layer, this second shaded areas is to cover this effectively second lightly doped region of layer, and the lateral length of this first shaded areas is the lateral length that is not equal to this second shaded areas.One grid layer is to be formed on this gate insulator, and covers the middle section of this gate insulator.
Description of drawings
Fig. 1 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of first embodiment of the invention;
The generalized section of the manufacture method of aiming at the LDD structure voluntarily of the TFT assembly of Fig. 2 A to Fig. 2 H demonstration first embodiment of the invention;
Fig. 3 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of second embodiment of the invention;
Fig. 4 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of third embodiment of the invention;
Fig. 5 shows the generalized section of asymmetric LDD structure of the TFT assembly of fourth embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Fig. 6 A to Fig. 6 C demonstration fourth embodiment of the invention;
Fig. 7 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of fifth embodiment of the invention;
Fig. 8 shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of sixth embodiment of the invention;
Fig. 9 shows the generalized section of asymmetric LDD structure of the TFT assembly of seventh embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Figure 10 A to Figure 10 C demonstration seventh embodiment of the invention;
Figure 11 shows the generalized section of asymmetric LDD structure of the TFT assembly of eighth embodiment of the invention;
Figure 12 shows the generalized section of asymmetric LDD structure of the TFT assembly of ninth embodiment of the invention;
The manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of Figure 13 A to Figure 13 E demonstration tenth embodiment of the invention.
Symbol description:
Substrate～10,30,50,70
The one TFT zone～I
The 2nd TFT zone～II
Resilient coating～12,32,52,72
Effective layer～14,16,34,54,74
Insulating barrier～18,36,56,76
Conductive layer～24,40,60,80
Photoresist layer～26,28,44,64,84
Grid layer～25,27,42,62,82
Gate insulator～20,22,38,58,78
Middle section～20a, 22a, 38a, 58a, 78a
Shaded areas～20b
1, 20b
2, 22b
1, 22b
2, 38b
1, 38b
2, 58b
1, 58b
2, 78b
1, 78b
2
Ion disposing process～29,46,66,86
Not doped region～14a, 16a, 34a, 54a, 74a
Lightly doped region～14b
1, 14b
2, 16b
1, 16b
2, 34b
1, 34b
2, 54b
1, 54b
2, 74b
1, 74b
2
Heavily doped region～14c
1, 14c
2, 16c
1, 16c
2, 34c
1, 34c
2, 54c
1, 54c
2, 74c
1, 74c
2
Light shield～6,87
Zone of opacity～2a, 4a, 87a
Phase transfer zone～2b, 4b, 87b
1, 87b
2
Transparent region～2c, 4c, 87c
1, 87c
2
Photoresistance pattern～26I, 26II, 85
First area～26I
a, 26II
a, 85a
Second area～26I
b, 26II
b, 85b
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
First embodiment:
First embodiment of the invention is the LDD structure at the TFT establishment of component different length of different operating voltage, the lateral length that is exposed to the grid layer both sides by gate insulator is planted processing procedure as the cover curtain and the primary ions cloth of arranging in pairs or groups, and can reach a making of aiming at LDD structure and one source/drain region voluntarily simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a picture element array zone and a peripheral drive circuit zone, below is to describe in detail to aim at LDD structure and preparation method thereof voluntarily.
See also Fig. 1, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of first embodiment of the invention.
One substrate 10 includes one the one TFT area I and one the 2nd TFT area I I, and deposits a resilient coating 12 on the surface.In a TFT area I, be manufactured with one first effective layer 14, one a first grid insulating barrier 20 and a first grid layer 25 on the resilient coating 12 in regular turn.In the 2nd TFT area I I, be manufactured with one second effective layer 16, one a second grid insulating barrier 22 and a second grid layer 27 on the resilient coating 12 in regular turn.
The preferably of substrate 10 is a transparent insulation substrate, for example: substrate of glass.The one TFT area I or the 2nd TFT area I I are a peripheral drive circuit zone or a picture element array zone.The preferably of resilient coating 12 is a dielectric materials layer, and for example: silicon oxide layer, its purpose is formed in the substrate 10 for helping first, second effective layer 14,16.The preferably of first, second effective layer 14,16 is the semiconductor silicon layer, for example: polysilicon layer.The preferably of first, second gate insulator 20,22 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.The preferably of first, second grid layer 25,27 is a metal level or a polysilicon layer.
It below is the architectural feature of explanation the one TFT area I.First effectively layer 14 include not doped region 14a, two lightly doped region 14b
1, 14b
2And two heavily doped region 14c
1, 14c
2Wherein, doped region 14a is not used as a channel region; First, second lightly doped region 14b
1, 14b
2Being to be formed at the not both sides of doped region 14a respectively, is to be used as a LDD structure; First, second heavily doped region 14c
1, 14c
2Be to be formed at first, second lightly doped region 14b respectively
1, 14b
2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 14b
1, 14b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, first, second heavily doped region 14c
1, 14c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2
First grid insulating barrier 20 includes a middle section 20a and two shaded areas 20b
1, 20b
2Wherein, middle section 20a covers not doped region 14a; The first shaded areas 20b
1Be to be positioned at middle section 20a left side, and cover the first lightly doped region 14b
1The second shaded areas 20b
2Be to be positioned at middle section 20a right side, and cover the second lightly doped region 14b
2The bottom of first grid layer 25 is to cover middle section 20a.Thus, then can utilize shaded areas 20b
1, 20b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
Shaded areas 20b
1, 20b
2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 14b
1Width be to correspond to the first shaded areas 20b
1Width W
1, and the second lightly doped region 14b
2Width be to correspond to the second shaded areas 20b
2Width W
2The preferably is the first shaded areas 20b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 20b
2Lateral length W
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W
1, W
2Length and symmetry thereof, the preferably is: W
1=W
2
It below is the architectural feature of explanation the 2nd TFT area I I.Second effectively layer 16 include not doped region 16a, two lightly doped region 16b
1, 16b
2And two heavily doped region 16c
1, 16c
2Wherein, doped region 16a is not used as a channel region; First, second lightly doped region 16b
1, 16b
2Being to be formed at the not both sides of doped region 16a respectively, is to be used as a LDD structure; First, second heavily doped region 16c
1, 16c
2Be to be formed at first, second lightly doped region 16b respectively
1, 16b
2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 16b
1, 16b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, first, second heavily doped region 16c
1, 16c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2
Second grid insulating barrier 22 includes a middle section 22a and two shaded areas 22b
1, 22b
2Wherein, middle section 22a covers not doped region 16a; The first shaded areas 22b
1Be to be positioned at middle section 22a left side, and cover the first lightly doped region 16b
1The second shaded areas 22b
2Be to be positioned at middle section 22a right side, and cover the second lightly doped region 16b
2The bottom of second grid layer 27 is to cover middle section 22a.Shaded areas 22b
1, 22b
2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 16b
1Width be to correspond to the first shaded areas 22b
1Width D
1, and the second lightly doped region 16b
2Width be to correspond to the second shaded areas 22b
2Width D
2The preferably is the first shaded areas 22b
1Lateral length D
1Be 0.1 μ m～2.0 μ m, the second shaded areas 22b
2Lateral length D
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust D
1, D
2Length and symmetry thereof, also can be: D
1=D
2In addition, can adjust W according to the reliability of circuit design, the demand of electric current
1, W
2, D
1, D
2Between relation so that W
1(or W
2) be not equal to D
1(or D
2), the preferably shown in the 1st figure is: a TFT area I is as a picture element array zone, and the 2nd TFT area I I is as a peripheral drive circuit zone, and W
1(or W
2)＞D
1(or D
2).
See also Fig. 2 A to Fig. 2 G, the generalized section of the manufacture method of aiming at the LDD structure voluntarily of the TFT assembly of its demonstration first embodiment of the invention.
At first, shown in Fig. 2 A, provide a substrate 10, it includes one the one TFT area I and one the 2nd TFT area I I.Then, deposition one resilient coating 12 in substrate 10 is again respectively at making first, second effective layer 14,16 on the resilient coating 12 of first, second TFT area I, II.The present invention does not limit thickness of first, second effective layer 14,16 and preparation method thereof, for instance, can adopt low temperature polycrystalline silicon (low temperature polycrystalline silicon, LTPS) processing procedure, prior to forming a noncrystalline silicon layer on the glass substrate, (excimer laser annealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize the annealing of heat treatment or excimer laser then.
Then, shown in Fig. 2 B, effectively deposit an insulating barrier 18 and a conductive layer 24 on the layer 14,16 in first, second in regular turn.The preferably of insulating barrier 18 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.The preferably of conductive layer 24 is a metal level or a polysilicon layer.
Thereafter, shown in Fig. 2 C, on conductive layer 24, form first photoresist layer 26 of a patterning,, and make first photoresist layer 26 cover whole the 2nd TFT area I I so that first photoresist layer 26 covers the zone of the pre-defined gate pattern of a TFT area I.Follow-up, shown in Fig. 2 D, first photoresist layer 26 that utilizes patterning is as covering curtain to carry out an etch process, pattern with 24 definition becoming of the conductive layer in a TFT area I first grid layer 25, and, follow-up first photoresist layer 26 is removed the pattern of the insulating barrier in the TFT area I 18 definition becoming a first grid insulating barrier 20.
The profile preferably of first grid layer 25 is one up-narrow and down-wide trapezoidal.First grid insulating barrier 20 includes a middle section 20a, one first shaded areas 20b
1And one second shaded areas 20b
2, middle section 20a is covered by the bottom of first grid layer 25, and first, second shaded areas 20b
1, 20b
2Be the two bottom sides that is exposed to first grid layer 25, and first grid insulating barrier 20 expose the predetermined origin/drain diffusion region of first effective layer 14.The preferably is the first shaded areas 20b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 20b
2Lateral length W
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W
1, W
2Length and symmetry thereof, also can be: W
1=W
2
The etch process preferably of this step is electric paste etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.For example: in the etching process of conductive layer 24, the flow of chlorine-containing gas can be adjusted to gradually greatly, or even only use chlorine-containing gas as etching reaction gas, aerating oxygen or strengthen oxygen flow simultaneously again when waiting to be etched to insulating barrier 18, simultaneously part first photoresist layer 26 and the grid layer 25 that exposes are once again carried out etching, the profile of first grid layer 25 can be made become one up-narrow and down-wide trapezoidally, and produces first, second shaded areas 20b of first grid insulating barrier 20
1, 20b
2
Then, shown in Fig. 2 E, provide second photoresist layer 28 of a patterning,, and make second photoresist layer 28 cover the zone of the pre-defined gate pattern of the 2nd TFT area I I so that second photoresist layer 28 covers a whole TFT area I.Follow-up, shown in Fig. 2 F, second photoresist layer 28 that utilizes patterning is as covering curtain to carry out an etch process, pattern with 24 definition becoming of the conductive layer in the 2nd a TFT area I I second grid layer 27, and, follow-up second photoresist layer 28 is removed the pattern of the insulating barrier in the 2nd TFT area I I 18 definition becoming a second grid insulating barrier 22.
The profile preferably of second grid layer 27 is one up-narrow and down-wide trapezoidal.Second grid insulating barrier 22 includes a middle section 22a, one first shaded areas 22b
1And one second shaded areas 22b
2, middle section 22a is covered by the bottom of second grid layer 27, and first, second shaded areas 22b
1, 22b
2Be the two bottom sides that is exposed to second grid layer 27, and second grid insulating barrier 22 expose the predetermined origin/drain diffusion region of second effective layer 16.The preferably is the first shaded areas 22b
1Lateral length D
1Be 0.1 μ m～2.0 μ m, the second shaded areas 22b
2Lateral length D
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust D
1, D
2Length and symmetry thereof, also can be: D
1=D
2In addition, relatively the structure of first grid insulating barrier 20 and second grid insulating barrier 22 can be adjusted W according to the reliability of circuit design, the demand of electric current
1, W
2, D
1, D
2Between relation so that W
1(or W
2) be not equal to D
1(or D
2), the preferably is: the LDD lateral length of the TFT in LDD lateral length＞peripheral drive circuit zone of the TFT in picture element array zone.
The engraving method of this step is described similar in appearance to Fig. 2 D, can use electric paste etching (plasmaetching) or reactive ion etching method, maybe can use a mist with oxygen-containing gas and chlorine-containing gas as etching gas, and according to the flow or the etching period that need to adjust individual gases in good time.
At last, shown in Fig. 2 G, carry out an ion disposing process 29, utilize the shaded areas 20b of first grid layer 25, first grid insulating barrier 20
1, 20b
2As cover curtain, then can effectively form not doped region 14a, two lightly doped region 14b in the layer 14 in first
1, 14b
2And two heavily doped region 14c
1, 14c
2Wherein, doped region 14a is not the corresponding below that is formed at middle section 20a, is to be used as a channel region; First, second lightly doped region 14b
1, 14b
2Be corresponding first, second shaded areas 20b that is formed at
1, 20b
2The below, be to be used as a LDD structure; First, second heavily doped region 14c
1, 14c
2Being the two bottom sides that is exposed to first grid insulating barrier 20, is to be used as one source/drain diffusion region.Because the shaded areas 20b of first grid insulating barrier 20
1, 20b
2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 14b
1Width be to correspond to the first shaded areas 20b
1Width W
1, and the second lightly doped region 14b
2Width be to correspond to the second shaded areas 20b
2Width W
2
When carrying out ion disposing process 29, can utilize the shaded areas 22b of second grid layer 27 and second grid insulating barrier 22
1, 22b
2As cover curtain, then can effectively form not doped region 16a, two lightly doped region 16b in the layer 16 in second
1, 16b
2And two heavily doped region 16c
1, 16c
2Wherein, doped region 16a is not the corresponding below that is formed at middle section 22a, is to be used as a channel region; First, second lightly doped region 16b
1, 16b
2Be corresponding first, second shaded areas 22b that is formed at
1, 22b
2The below, be to be used as a LDD structure; First, second heavily doped region 16c
1, 16c
2Being the two bottom sides that is exposed to second grid insulating barrier 22, is to be used as one source/drain diffusion region.Because the shaded areas 22b of second grid insulating barrier 22
1, 22b
2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 16b
1Width be to correspond to the first shaded areas 22b
1Width D
1, and the second lightly doped region 16b
2Width be to correspond to the second shaded areas 22b
2Width D
2
For a TFT area I, the preferably is first, second lightly doped region 14b
1, 14b
2Transverse width W
1, W
2Be 0.1～2.0 μ m, it is 10～100keV that cloth is planted energy, first, second lightly doped region 14b
1, 14b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, the doping content of heavily doped region 14c is 1 * 10
14～1 * 10
16Atom/cm
2
For the 2nd TFT area I I, the preferably is first, second lightly doped region 16b
1, 16b
2Transverse width D
1, D
2Be 0.1～2.0 μ m, it is 10～100keV that cloth is planted energy, first, second lightly doped region 16b
1, 16b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, the doping content of heavily doped region 16c is 1 * 10
14～1 * 10
16Atom/cm
2
The inventive method can be applicable to a P type silicon base, and then the LDD structure is a N
-Doped region, and source/drain diffusion region is a N
+Doped region.The inventive method also can be applicable to a N type silicon base, and then the LDD structure is a P
-Doped region, and source/drain region is a P
+Doped region.
The follow-up interconnect processing procedure that carries out includes the making of interconnect dielectric layer, contact hole and interconnect, and the execution mode of this step can materially affect feature of the present invention and effect, so do not write in detail.
From the above, TFT assembly of first embodiment of the invention and preparation method thereof has the following advantages:
The first, by the shaded areas 20b that adjusts first, second gate insulator 20,22 of etching condition may command
1, 20b
2, 22b
1, 22b
2Lateral length W
1, W
2, D
1, D
2Therefore, can accurately control the position of LDD structure, to meet the electrical demand of TFT assembly.
The second, do not need additionally to provide light shield or make sidewall to define the pattern of LDD structure, so can avoid the problem of alignment error (photo misalignment) offset that causes of exposure technique, then can further accurately control the position of LDD structure.
The 3rd, reduce by a light dope cloth and plant processing procedure, thus have advantages such as the fabrication steps of simplification, reduction processing procedure cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.
The 4th, the inventive method can be simultaneously carried out dopping process adjusting its component characteristic to a TFT area I and the 2nd TFT area I I, and the shaded areas 20b of first, second gate insulator 20,22 of may command
1, 20b
2, 22b
1, 22b
2Lateral length W
1, W
2, D
1, D
2So, can be at the LDD structure of the establishment of component different length of different operating voltage, with the requirement on Achieved Reliability and the service speed.
In addition, see also Fig. 2 H, the manufacture method of first embodiment of the invention, also can utilize a decrescendo phase transfer light shield (attenuated phase shifting mask) and collocation to carry out micro-photographing process one time, then the grid layer that can define a TFT area I and the 2nd TFT area I I simultaneously by convex character shape optical pattern resistances layer and etch process with the pattern of gate insulator.
After finishing the step shown in Fig. 2 A and Fig. 2 B, provide a decrescendo phase transfer (attenuatedphase shifting) light shield 6 so that first photoresist layer 26 is carried out the exposure imaging processing procedure, can make first photoresist layer 26 of a TFT area I become the photoresistance pattern 26I of a convex character shape, and make first photoresist layer 26 of the 2nd TFT area I I become the photoresistance pattern 26II of a convex character shape simultaneously.For example, decrescendo phase transfer light shield 6 includes a first exposure area 2 and one second exposure area 4.First exposure area 2 is to be positioned at a TFT area I, and includes: a light tight regional 2a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; The regional 2b of a pair of phase transfer (phase-shifting) is the both sides that are positioned at light tight regional 2a, and its position and size are with respect to a predetermined lightly doped region; Pair of light-transmissive zone 2c is the both sides that are positioned at phase transfer zone 2b, and its position and size are with respect to a predetermined heavy and light doped region.Generally speaking, phase transfer zone 2b and transmission region 2c have different light transmittances, and its light transmittance difference can be done suitable design according to product and processing procedure.Similarly, second portion exposure area 4 is to be positioned at the 2nd TFT area I I, and includes: a light tight regional 4a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; A pair of phase transfer zone 4b is the both sides that are positioned at light tight regional 4a, and its position and size are with respect to a predetermined lightly doped region; Pair of light-transmissive zone 4c is the both sides that are positioned at phase transfer zone 4b, and its position and size are with respect to a predetermined heavy and light doped region.Generally speaking, phase transfer zone 4b and transmission region 4c have different light transmittances, and its light transmittance difference can be done suitable design according to product and processing procedure.
Thus, utilize the decrescendo light shield eurymeric resistance material of arranging in pairs or groups to carry out after the micro-photographing process, different light transmittances by each zone, can make each opposite position of first photoresist layer 26 accept the exposure effect of varying strength, so that the etched degree of depth difference of each opposite position, just can make the first area 26I of the photoresistance pattern 26I of convex character shape
aThickness greater than second area 26I
bThickness.In the same manner, the first area 26II of the photoresistance pattern 26II of convex character shape
aThickness greater than second area 26II
bThickness.As for second area 26I
b, 26II
bLateral length then depend on the lateral length design of LDD structure.
Thereafter, utilize the photoresistance pattern 26I of convex character shape, 26II is as covering curtain to carry out etch process, with photoresistance pattern 26I, conductive layer 24 beyond the 26II and insulating barrier 18 are removed, continue etching again with photoresistance pattern 26I, the 26II thinning is until removing second area 26Ib fully, the conductive layer 24 of 26IIb and below thereof, then conductive layer 24 definition can be become first grid layer 25, the pattern of second grid layer 27, and insulating barrier 18 definition can be become first grid insulating barrier 20, the pattern of second grid insulating barrier 22, follow-up with after 26 removals of first photoresist layer, the result is as shown in Fig. 2 F.Follow-up ion disposing process 29 and the result thereof of carrying out is as shown in Fig. 2 G, so book in detail.
Second embodiment:
See also Fig. 3, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of second embodiment of the invention.
The TFT assembly of second embodiment is roughly described identical with first embodiment with architectural feature, and something in common no longer repeats book.
In a TFT area I, first grid insulating barrier 20 includes one first elongated area 20c in addition
1And one second elongated area 20c
2The first elongated area 20c
1Be to be positioned at the first shaded areas 20b
1The left side, and cover the first heavily doped region 14b
1The second elongated area 20c
2Be to be positioned at the second shaded areas 20b
2The right side, and cover the second heavily doped region 14b
2Particularly, the first elongated area 20c
1Thickness T
1Less than the first shaded areas 20b
1Thickness T
2, also can make the first elongated area 20c
1Thickness T
1Near a minimum.In the same manner, the second elongated area 20c
2Thickness T
1Less than the second shaded areas 20b
2Thickness T
2, also can make the second elongated area 20c
2Thickness T
1Near a minimum.The feature of second embodiment is the elongated area that keeps gate insulator in the TFT zone, can protect the polysilicon material of the grid layer of below, and can not influence the ion concentration of heavily doped region.Thus, then can utilize the bigger shaded areas 20b of thickness
1, 20b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
In the same manner, in the 2nd TFT area I I, second grid insulating barrier 22 includes one first elongated area 22c in addition
1And one second elongated area 22c
2The first elongated area 22c
1Be to be positioned at the first shaded areas 22b
1The left side, and cover the first heavily doped region 16b
1The second elongated area 22c
2Be to be positioned at the second shaded areas 22b
2The right side, and cover the second heavily doped region 16b
2Particularly, the first elongated area 22c
1Thickness t
1Less than the first shaded areas 22b
1Thickness t
2, also can make the first elongated area 22c
1Thickness t
1Near a minimum.In the same manner, the second elongated area 22c
2Thickness t
1Less than the second shaded areas 22b
2Thickness t
2, also can make the second elongated area 22c
2Thickness t
1Near a minimum.Thus, then can utilize the bigger shaded areas 22b of thickness
1, 22b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
Manufacture method as for second embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is etching isolation layer 18 with in the process of finishing first grid insulating barrier 20 and second grid insulating barrier 22, needs suitably control etch depth, so that elongated area 20c
1, 20c
2Thickness T
1And elongated area 22c
1, 22c
2Thickness t
1Reach a preferred values.
The 3rd embodiment:
See also Fig. 4, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of third embodiment of the invention.
The TFT assembly of the 3rd embodiment is roughly described identical with second embodiment with architectural feature, and something in common no longer repeats book.
In a TFT area I, first grid insulating barrier 20 is to be formed by one first insulating barrier 20I and one second insulating barrier 20II institute storehouse.The preferably of the first insulating barrier 20I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 20II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 20a, the double-decker of the first insulating barrier 20I and the second insulating barrier 20II is to cover channel region 14a.Be positioned at shaded areas 20b
1, 20b
2In, the double-decker of the first insulating barrier 20I and the second insulating barrier 20II is to cover the LDD structure.Be positioned at elongated area 20c
1, 20c
2In, the single layer structure of the first insulating barrier 20I is covering source/drain region.Therefore, in comparison, elongated area 20c
1, 20c
2The thickness T of interior first grid insulating barrier 20
1Less, and shaded areas 20b
1, 20b
2The thickness T of interior first grid insulating barrier 20
2Bigger.Thus, then can utilize the bigger shaded areas 20b of thickness
1, 20b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
In the same manner, in the 2nd TFT area I I, second grid insulating barrier 22 is to be formed by one first insulating barrier 22I and one second insulating barrier 22II institute storehouse.The preferably of the first insulating barrier 22I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 22II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 22a, the double-decker of the first insulating barrier 22I and the second insulating barrier 22II is to cover channel region 16a.Be positioned at shaded areas 22b
1, 22b
2In, the double-decker of the first insulating barrier 22I and the second insulating barrier 22II is to cover the LDD structure.Be positioned at elongated area 22c
1, 22c
2In, the single layer structure of the first insulating barrier 22I is covering source/drain region.Therefore, in comparison, elongated area 22c
1, 22c
2The thickness t of interior second grid insulating barrier 22
1Less, and shaded areas 22b
1, 22b
2The thickness t of interior second grid insulating barrier 22
2Bigger.Thus, then can utilize the bigger shaded areas 22b of thickness
1, 22b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
Manufacture method as for the 3rd embodiment is roughly described identical with first embodiment, and something in common no longer repeats book.Difference is etching isolation layer 18 with in the process of finishing first grid insulating barrier 20 and second grid insulating barrier 22, needs suitably control etch depth, so that elongated area 20c
1, 20c
2Thickness T
1And elongated area 22c
1, 22c
2Thickness t
1Reach a preferred values.
The 4th embodiment:
Fourth embodiment of the invention is at an one-sided LDD structure of TFT establishment of component, the one-sided shaded areas of grid layer that is exposed to by gate insulator is planted processing procedure as the cover curtain and the primary ions cloth of arranging in pairs or groups, and can finish an one-sided LDD structure and a pair of source territory simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is to describe asymmetric LDD structure and preparation method thereof in detail.
See also Fig. 5, the generalized section of the asymmetric LDD structure of the TFT assembly of demonstration fourth embodiment of the invention.
Be manufactured with a resilient coating 32, one effective layer 34, one gate insulator 38 and a grid layer 42 on one substrate, 30 surfaces in regular turn.The preferably of substrate 30 is a transparent insulation substrate or a substrate of glass, the preferably of resilient coating 32 is a dielectric materials layer or one silica layer, effectively the preferably of layer 34 is a semiconductor silicon layer or a polysilicon layer, the preferably of gate insulator 38 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of grid layer 42 is a metal level or a polysilicon layer.
Effectively layer 34 includes not doped region 34a, a lightly doped region 34b and two heavily doped region 34c
1, 34c
2Doped region 34a is not used as a channel region.Lightly doped region 34b is formed at the not right side of doped region 34a, is to be used as a LDD structure; The first heavily doped region 34c
1Be to be formed at the not left side of doped region 14a, and the second heavily doped region 34c
2Being the right side that is formed at lightly doped region 14b, is to be used as one source/drain diffusion region.The doping content of lightly doped region 34b is 1 * 10
12～1 * 10
14Atom/cm
2, heavily doped region 34c
1, 34c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2
See also Fig. 6 A to Fig. 6 C, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration fourth embodiment of the invention.
At first, as shown in Figure 6A, deposition one resilient coating 32 in a substrate 30 is made an effective layer 34 again on the presumptive area of resilient coating 32, deposit an insulating barrier 36 and a conductive layer 40 more in regular turn, follow-up definition one patterned light blockage layer 44 on conductive layer 40 again.The preferably of insulating barrier 36 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 40 is a metal level or a polysilicon layer.
The layout plane graph of Fig. 6 B display light resistance layer 44 and effective layer 34, and Fig. 6 A is along the tangent line 6-6 display light resistance layer 44 of Fig. 6 B and the generalized section of effective layer 34.Patterned light blockage layer 44 is to correspond to a pre-defined gate layer pattern.
Thereafter, shown in Fig. 6 C, utilize patterned light blockage layer 44 as covering curtain to carry out an etch process, can be with the pattern of conductive layer 40 definition a becoming grid layer 42, and can be with the pattern of insulating barrier 36 definition a becoming gate insulator 38, follow-up photoresist layer 44 is removed.Gate insulator 38 includes a middle section 38a and a shaded areas 38b, middle section 38a is covered by the bottom of grid layer 42, shaded areas 38b is bottom one side that is positioned at the side of middle section 38a and is exposed to grid layer 42, and gate insulator 38 exposes the effectively predetermined origin/drain diffusion region of layer 34.The preferably is that the lateral length W of shaded areas 38b is 0.1 μ m～2.0 μ m.The etch process preferably of this step is electric paste etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, carry out an ion disposing process 46, the shaded areas 38b that utilizes grid layer 42 and gate insulator 38 is as the cover curtain, then can form not doped region 34a, a lightly doped region 34b and two heavily doped region 34c in effective layer 34
1, 34c
2Wherein, doped region 34a is not the corresponding below that is formed at middle section 38a, is to be used as a channel region; Lightly doped region 34b correspondingly is formed at the below of shaded areas 38b and is formed at the one-sided of channel region 34a, is to be used as a LDD structure; Two heavily doped region 34c
1, 34c
2Being the two bottom sides that is exposed to gate insulator 38 respectively, is to be used as one source/drain diffusion region.Because the shaded areas 38b of gate insulator 38 is the cover curtains that are used as the LDD structure, so the width of lightly doped region 34b is the width W that corresponds to shaded areas 38b.
The preferably is, the transverse width W of lightly doped region 34b is 0.1～2.0 μ m, and it is 10～100keV that cloth is planted energy, and the doping content of lightly doped region 34b is 1 * 10
12～1 * 10
14Atom/cm
2, heavily doped region 34c
1, 34c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N
-Doped region, and source/drain diffusion region is a N
+Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P
-Doped region, and source/drain region is a P
+Doped region.
The follow-up interconnect processing procedure that carries out includes the making of interconnect dielectric layer, contact hole and interconnect, and the execution mode of this step can materially affect feature of the present invention and effect, so do not write in detail.
From the above, TFT assembly of fourth embodiment of the invention and preparation method thereof has the following advantages:
The first, by adjusting the just lateral length W of the shaded areas 38b of may command gate insulator 38 of etching condition, therefore can accurately control the position of LDD structure, to meet the electrical demand of TFT assembly.
The second, do not need additionally to provide light shield or make sidewall to define the pattern of LDD structure, so can avoid the problem of alignment error (photo misalignment) offset that causes of exposure technique, then can further accurately control the position of LDD structure.
The 3rd, reduce and use a light shield, thus have advantages such as the fabrication steps of simplification, reduction processing procedure cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.
The 4th, the inventive method is by the one-sided shaded areas 38b of the gate insulator 38 cover curtain as the ion disposing process of LDD structure, therefore can be in LDD structure of one-sided formation of the channel region 34a of effective layer 34, with the reliability that meets special operational voltage assembly and the requirement on the service speed.
The 5th embodiment:
See also Fig. 7, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of fifth embodiment of the invention.
The TFT assembly of the 5th embodiment is roughly described identical with the 4th embodiment with architectural feature, and something in common no longer repeats book.
Manufacture method as for the 5th embodiment is roughly described identical with the 4th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 36 with in the process of finishing gate insulator 38, needs suitably control etch depth, so that the thickness T of elongated area 38c
1Reach a preferred values.
The 6th embodiment:
See also Fig. 8, it shows the generalized section of aiming at the LDD structure voluntarily of the TFT assembly of sixth embodiment of the invention.
The TFT assembly of the 6th embodiment is roughly described identical with the 5th embodiment with architectural feature, and something in common no longer repeats book.
Manufacture method as for the 6th embodiment is roughly described identical with the 5th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 36 with in the process of finishing gate insulator 38, needs suitably to control the etch depth of the first insulating barrier 38I and the second insulating barrier 38II, so that the thickness T of elongated area 38c
1Reach a preferred values.
The 7th embodiment:
Seventh embodiment of the invention is the LDD structure at the asymmetric length of TFT establishment of component bilateral, the asymmetric length that is exposed to the grid layer both sides by gate insulator is planted processing procedure as the cover curtain and the primary ions cloth of arranging in pairs or groups, and can finish the LDD structure and the pair of source territory of two asymmetric length simultaneously.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is to describe asymmetric LDD structure and preparation method thereof in detail.
See also Fig. 9, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration seventh embodiment of the invention.
One substrate 50 includes a resilient coating 52, one effective layer 54, one gate insulator 58 and a grid layer 62.The preferably of resilient coating 52 is a dielectric materials layer or one silica layer, effectively the preferably of layer 54 is a semiconductor silicon layer or a polysilicon layer, the preferably of two gate insulators 58 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of grid layer 62 is a metal level or a polysilicon layer.
Effectively layer 54 includes not doped region 54a, two lightly doped region 54b
1, 54b
2And two heavily doped region 54c
1, 54c
2Wherein, doped region 54a is not used as a channel region; First, second lightly doped region 54b
1, 54b
2Being to be formed at the not both sides of doped region 54a respectively, is to be used as a LDD structure; First, second heavily doped region 54c
1, 54c
2Be to be formed at first, second lightly doped region 54b respectively
1, 54b
2The outside, be to be used as one source/drain diffusion region.First, second lightly doped region 54b
1, 54b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, heavily doped region 54c
1, 54c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2
Shaded areas 58b
1, 58b
2Be the cover curtain that is used as the LDD structure, so the first lightly doped region 54b
1Width be to correspond to the first shaded areas 58b
1Width W
1, and the second lightly doped region 54b
2Width be to correspond to the second shaded areas 58b
2Width W
2The preferably is the first shaded areas 58b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 58b
2Lateral length W
2Be 0.1 μ m～2.0 μ m.According to the circuit design demand, can suitably adjust W
1, W
2Length and asymmetry thereof so that W
1Be not equal to W
2, the preferably is W
1＜W
2
See also Figure 10 A to Figure 10 C, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration seventh embodiment of the invention.
At first, shown in Figure 10 A, deposition one resilient coating 52 in a substrate 50 is made an effective layer 54 again on the presumptive area of resilient coating 52, deposit an insulating barrier 56 and a conductive layer 60 more in regular turn, follow-up definition one patterned light blockage layer 64 on conductive layer 60 again.The preferably of insulating barrier 56 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 60 is a metal level or a polysilicon layer.
The layout plane graph of Figure 10 B display light resistance layer 64 and effective layer 54, and 10A figure is along the tangent line 10-10 display light resistance layer 64 of 10B figure and the generalized section of effective layer 54.Patterned light blockage layer 64 is to correspond to a pre-defined gate layer pattern.
Thereafter, shown in Figure 10 C, utilize patterned light blockage layer 64 as covering curtain to carry out an etch process, can be with the pattern of conductive layer 60 definition a becoming grid layer 62, and can be with the pattern of insulating barrier 56 definition a becoming gate insulator 58, follow-up photoresist layer 64 is removed.Gate insulator 58 includes a middle section 58a, one first shaded areas 58b
1And one second shaded areas 58b
2, middle section 58a is covered by the bottom of grid layer 62, the first shaded areas 58b
1Be the bottom left that is positioned at the left side of middle section 58a and is exposed to grid layer 62, the second shaded areas 58b
2Be the right side, bottom that is positioned at the right side of middle section 58a and is exposed to grid layer 62, and gate insulator 58 expose the effectively predetermined origin/drain diffusion region of layer 54.The preferably is the first shaded areas 58b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 58b
2Lateral length W
2Be 0.1 μ m～2.0 μ m, and W
1Be not equal to W
2The graphic demonstration W of second embodiment
1＜W
2The etch process preferably of this step is electric paste etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, carry out an ion disposing process 66, utilize grid layer 62 with the shaded areas 58b of gate insulator 58
1, 58b
2As cover curtain, then can in effective layer 54, form not doped region 54a, two lightly doped region 54b
1, 54b
2And two heavily doped region 54c
1, 54c
2Wherein, doped region 54a is not the corresponding below that is formed at middle section 58a, is to be used as a channel region; The first lightly doped region 54b
1Be the corresponding first shaded areas 58b that is formed at
1The below, the second lightly doped region 54b
2Be the corresponding second shaded areas 58b that is formed at
2The below, be to be used as a LDD structure; Heavily doped region 54c
1, 54c
2Being the two bottom sides that is exposed to gate insulator 58, is to be used as one source/drain diffusion region.Because the shaded areas 58b of gate insulator 58
1, 58b
2Be the cover curtain that is used as the LDD structure, so lightly doped region 54b
1, 54b
2Width be to correspond to shaded areas 58b
1, 58b
2Width W
1, W
2
The preferably is the first lightly doped region 54b
1Transverse width W
1Be 0.1～2.0 μ m, the second lightly doped region 54b
2Transverse width W
2Be 0.1～2.0 μ m, and W
1Be not equal to W
2It is 10～100keV that cloth is planted energy, lightly doped region 54b
1, 54b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, heavily doped region 54c
1, 54c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N
-Doped region, and source/drain diffusion region is a N
+Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P
-Doped region, and source/drain region is a P
+Doped region.
The follow-up interconnect processing procedure that carries out includes the making of interconnect dielectric layer, contact hole and interconnect, and the execution mode of this step can materially affect feature of the present invention and effect, so do not write in detail.
From the above, TFT assembly of seventh embodiment of the invention and preparation method thereof is same as the described advantage of the 4th embodiment except having, still can be by the shaded areas 58b of the asymmetric length of bilateral of gate insulator 58
1, 58b
2As the cover curtain of the ion disposing process of LDD structure, therefore can form two asymmetric LDD structures of length, with the reliability that meets special operational voltage assembly and the requirement on the service speed in the bilateral of the channel region 54a of effective layer 54.
The 8th embodiment:
See also Figure 11, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration eighth embodiment of the invention.
The TFT assembly of the 8th embodiment is roughly described identical with the 7th embodiment with architectural feature, and something in common no longer repeats book.
Manufacture method as for the 8th embodiment is roughly described identical with the 7th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 56 with in the process of finishing gate insulator 58, needs suitably control etch depth, so that elongated area 58c
1, 58c
2Thickness T
1Reach a preferred values.
The 9th embodiment:
See also Figure 12, the generalized section of the asymmetric LDD structure of the TFT assembly of its demonstration ninth embodiment of the invention.
The TFT assembly of the 9th embodiment is roughly described identical with the 8th embodiment with architectural feature, and something in common no longer repeats book.
Gate insulator 58 is to be formed by one first insulating barrier 58I and one second insulating barrier 58II institute storehouse.The preferably of the first insulating barrier 58I is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of the second insulating barrier 58II is one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.Be positioned at middle section 58a, the double-decker of the first insulating barrier 58I and the second insulating barrier 58II is to cover channel region 54a.Be positioned at shaded areas 58b
1, 58b
2In, the double-decker of the first insulating barrier 58I and the second insulating barrier 58II is to cover the LDD structure.Be positioned at elongated area 58c
1, 58c
2In, the single layer structure of the first insulating barrier 58I is covering source/drain region.Therefore, in comparison, elongated area 58c
1, 58c
2The thickness T of interior gate insulator 58
1Less, and shaded areas 58b
1, 58b
2The thickness T of interior gate insulator 58
2Bigger.Thus, then can utilize the bigger shaded areas 58b of thickness
1, 58b
2As the cover curtain of the ion disposing process of LDD structure, and the cloth that ion disposing process is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure and source/drain region simultaneously via ion disposing process once.
Manufacture method as for the 9th embodiment is roughly described identical with the 7th embodiment, and something in common no longer repeats book.Difference is etching isolation layer 56 with in the process of finishing gate insulator 58, needs suitably to control the etch depth of the first insulating barrier 58I and the second insulating barrier 58II, so that elongated area 58c
1, 58c
2Thickness T
1Reach a preferred values.
The tenth embodiment:
Tenth embodiment of the invention is to utilize a decrescendo phase transfer light shield (attenuated phaseshifting mask) and collocation to carry out a micro-photographing process, shaded areas and elongated area with the definition gate insulator, then plant processing procedure as the cover curtain and the primary ions cloth of arranging in pairs or groups, can finish the LDD structure and the pair of source territory of two asymmetric length simultaneously by the shaded areas of the asymmetric length of gate insulator.TFT modular construction of the present invention and preparation method thereof can be applicable to a P type TFT assembly or a N type TFT assembly, and can be applicable to the TFT assembly in a peripheral drive circuit zone, below is the manufacture method that describes asymmetric LDD structure in detail.
See also Figure 13 A to Figure 13 E, the manufacture method schematic diagram of the asymmetric LDD structure of the TFT assembly of its demonstration tenth embodiment of the invention.
At first, as shown in FIG. 13A, deposition one resilient coating 72 in a substrate 70 is made an effective layer 74 again on the presumptive area of resilient coating 72, deposit an insulating barrier 76, a conductive layer 80 and a photoresist layer 84 more in regular turn.The preferably of substrate 70 is a transparent insulation substrate or a substrate of glass, the preferably of resilient coating 72 is a dielectric materials layer or one silica layer, effectively the preferably of layer 74 is semiconductor silicon layer, a polysilicon layer or a low-temperature polycrystalline silicon layer, the preferably of insulating barrier 76 is the stack layer of one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, and the preferably of conductive layer 80 is a metal level or a polysilicon layer.
Shown in Figure 13 B, provide a decrescendo phase transfer (attenuated phase shifting) light shield 87 so that photoresist layer 84 is carried out the exposure imaging processing procedure, so that photoresist layer 84 becomes the photoresistance pattern 85 of a convex character shape.For example, light shield 87 includes: a light tight regional 87a, and its light transmittance is almost 0%, and its position and size are with respect to a pre-defined gate layer pattern; The regional 87b of one first phase transfer (phase-shifting)
1Be the left side that is positioned at light tight regional 87a, its position and size are with respect to predetermined first lightly doped region; One second phase transfer zone 87b
2Be the right side that is positioned at light tight regional 87a, its position and size are with respect to predetermined second lightly doped region; One first transmission region 87c
1Be to be positioned at first phase transfer zone 87b
1The left side, its position and size are with respect to predetermined first a heavy and light doped region; And one second transmission region 87c
2Be to be positioned at second phase transfer zone 87b
2The right side, its position and size are with respect to predetermined second heavily doped region.Generally speaking, phase transfer zone 87b
1, 87b
2And transmission region 87c
1, 87c
2Have different light transmittances, its light transmittance difference can be according to product and processing procedure and is done suitable design.Thus, utilize 87 pairs one eurymeric resistance materials of decrescendo light shield to carry out after the micro-photographing process, different light transmittances by each zone, can make each opposite position of photoresist layer 84 accept the exposure effect of varying strength, so that the etched degree of depth difference of each opposite position, the thickness of first area 85a of photoresistance pattern 85 that just can make convex character shape is greater than second area 85b
1, 85b
2Thickness.Certainly, decrescendo light shield 87 also can be applied to the minus resistance material, as long as by each the regional position relation that changes on the decrescendo light shield 87, just can form identical convex character shape profile on the minus resistance material.
Thereafter, shown in Figure 13 C, the photoresistance pattern 85 that utilizes convex character shape is removed conductive layer 80 beyond the photoresistance pattern 85 and insulating barrier 76, and is kept a part of insulating barrier 76 to cover effective layer 74 and resilient coating 72 as covering curtain to carry out one first etch process.Then, shown in Figure 13 D, carry out one second etch process, with 85 thinnings of photoresistance pattern until removing second area 85b fully
1, 85b
2And the conductive layer 80 of below, then conductive layer 80 can be defined the pattern that becomes a grid layer 82, and can be with the pattern of insulating barrier 76 definition a becoming gate insulator 78.
Gate insulator 78 includes a middle section 78a, one first shaded areas 78b
1, one second shaded areas 78b
2, one first elongated area 78c
1And one second elongated area 78c
2Middle section 78a is covered by the bottom of grid layer 82, the first shaded areas 78b
1Be the bottom left that is positioned at the left side of middle section 78a and is exposed to grid layer 82, the second shaded areas 78b
2Be the right side, bottom that is positioned at the right side of middle section 78a and is exposed to grid layer 82, the first elongated area 78c
1Be to be positioned at the first shaded areas 78b
1The left side, the second elongated area 78c
2Be to be positioned at the second shaded areas 78b
2The right side.The first shaded areas 78b
1Lateral length W
1Be 0.1 μ m～2.0 μ m, the second shaded areas 78b
2Lateral length W
2Be 0.1 μ m～2.0 μ m, and W
1Be not equal to W
2The graphic demonstration W of second embodiment
1＜W
2Particularly, elongated area 78c
1, 78c
2Thickness T
1Less than shaded areas 78b
1, 78b
2Thickness T
2, also can make elongated area 78c
1, 78c
2Thickness T
1Near a minimum.The etch process preferably of this step is electric paste etching (plasma etching) or reactive ion etching method.Perhaps, the reacting gas of etch process can use one to have the mist of oxygen-containing gas and chlorine-containing gas, and can adjust the flow of individual gases according to needs in good time.
At last, shown in Figure 13 E, after photoresistance pattern 85 removed, carry out an ion disposing process 86, utilize grid layer 82 with the shaded areas 78b of gate insulator 78
1, 78b
2As cover curtain, then can in effective layer 74, form not doped region 74a, two lightly doped region 74b
1, 74b
2And two heavily doped region 74c
1, 74c
2Wherein, doped region 74a is not the corresponding below that is formed at middle section 78a, is to be used as a channel region; The first lightly doped region 74b
1Be the corresponding first shaded areas 78b that is formed at
1The below, the second lightly doped region 74b
2Be the corresponding second shaded areas 78b that is formed at
2The below, be to be used as a LDD structure; Heavily doped region 74c
1, 74c
2Being the two bottom sides that is exposed to gate insulator 78, is to be used as one source/drain diffusion region.Because the shaded areas 78b of gate insulator 78
1, 78b
2Be the cover curtain that is used as the LDD structure, so lightly doped region 74b
1, 74b
2Width be to correspond to shaded areas 78b
1, 78b
2Width W
1, W
2
The preferably is the first lightly doped region 74b
1Transverse width W
1Be 0.1～2.0 μ m, the second lightly doped region 74b
2Transverse width W
2Be 0.1～2.0 μ m, and W
1Be not equal to W
2It is 10～100keV that cloth is planted energy, lightly doped region 74b
1, 74b
2Doping content be 1 * 10
12～1 * 10
14Atom/cm
2, heavily doped region 74c
1, 74c
2Doping content be 1 * 10
14～1 * 10
16Atom/cm
2TFT assembly of the present invention and method thereof can be applicable to a P type silicon base, and then the LDD structure is a N
-Doped region, and source/drain diffusion region is a N
+Doped region.TFT structure of the present invention and method thereof also can be applicable to a N type silicon base, and then the LDD structure is a P
-Doped region, and source/drain region is a P
+Doped region.
The follow-up interconnect processing procedure that carries out includes the making of interconnect dielectric layer, contact hole and interconnect, and the execution mode of this step can materially affect feature of the present invention and effect, so do not write in detail.In addition, the method for the tenth embodiment also can be applicable to the processing procedure of Fig. 9 and the described TFT assembly of Figure 12.
Claims (29)
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| CNB2003101033254A CN100358157C (en) | 2003-10-28 | 2003-10-28 | Thin film transistor and its manufacturing method |
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