CN102544095B - MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof. The manufacturing method of the MOS transistor comprises the following steps of: providing a semiconductor substrate on which a gate dielectric layer, a pseudo gate, a source region heavily doped region and a drain region heavily doped region are arranged, wherein the source region heavily doped region and the drain region heavily doped region are arranged in the semiconductor substrate on two sides of the pseudo gate, and gate sidewalls are further arranged at two sides of the pseudo gate; removing the pseudo gate to form a gate channel in each gate sidewall; forming a grid electrode on one inner side of the gate channel in close to a source region; and forming a drain region LDD (Lightly Doped Drain) region below the gate channel by taking the grid electrode as a mask. According to the MOS transistor and the manufacturing method thereof, disclosed by the invention, the grid electrode is of an asymmetric structure and is only arranged on one inner side of the gate channel in close to the source region; and during manufacturing, the asymmetric LDD region can be formed by taking the asymmetric grid electrode as the mask so that a photoetching process is saved, and the manufacturing cost can be reduced; in addition, the floor area of a device can be reduced, and the integration degree of the transistor is favorably improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of MOS transistor and preparation method thereof.
Background technology
At present, very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually, semiconductor technology is towards the even more technology node development of small-feature-size of 22nm.Be accompanied by many technical problems that MOS transistor size reduction also brings, for example short-channel effect (short channel effects, SCE) is one of most thorny issue wherein.
M.Lundstrom, IEEE Int.Electron Devices Tech.Dig., pp.789-792,2003. have proposed a kind of MOS transistor with asymmetric LDD district, are conducive to reduce short-channel effect.Fig. 1 is the structural representation with the MOS transistor in asymmetric LDD district, as shown in the figure, MOS transistor comprises source region 2 and the drain region 3 in grid 1, grid 1 both sides substrate, wherein, source region 2 extends to the below of grid curb wall 1, and do not have LDD district, 3 LDD districts 5, drain region to be positioned at grid curb wall 4 belows, and the heavily doped region in drain region 3 is positioned at the substrate in grid curb wall 1 outside.The MOS transistor in this asymmetric LDD district not only can be improved short-channel effect, drive current that also can enhance device.
United States Patent (USP) 1998/5705493 discloses a kind of manufacture method of above-mentioned MOS transistor, as shown in Figures 2 to 4, first form grid curb wall 20, then remove the side wall of position, source region, taking remaining side wall 20 and grid 16 as mask, in Semiconductor substrate 10, carry out Implantation, form heavily doped region 24, then remove remaining grid curb wall 20, carry out Implantation taking grid 16 as mask, thereby only forming LDD district, drain region.This method also needs again to form grid curb wall after forming source region and drain region.
United States Patent (USP) 1998/5828104 discloses the manufacture method of another kind of MOS transistor, as shown in Figures 5 to 7, in Semiconductor substrate 21, carry out Implantation taking grid 23 as mask, form respectively source region and LDD district, drain region 24b, 24a, utilize photoresist layer 27 to block drain region, carry out Implantation in source region, form heavily doped region 25b, then form grid curb wall 26, carry out Implantation taking grid 23 and grid curb wall 26 as mask, form the heavily doped region 25a in drain region, thereby form asymmetrical LDD district.But this manufacture method has increased photoetching process one.
Visible, the equal more complicated of manufacture method of above-mentioned MOS transistor, is unfavorable for reducing the cost of manufacture of device.
Summary of the invention
The problem that the present invention solves is to provide a kind of MOS transistor and preparation method thereof, needn't increase lithography step and can form asymmetrical LDD district, can reduce cost of manufacture.
For addressing the above problem, the invention provides a kind of MOS transistor, comprising:
Semiconductor substrate;
Before-metal medium layer in described Semiconductor substrate,
Gate groove in grid curb wall and grid curb wall in described before-metal medium layer;
Source region and drain region in the Semiconductor substrate of described gate groove both sides;
Described drain region has LDD district, and described LDD district extends to described gate groove below;
A side near source region in described gate groove has grid.
Described grid and LDD district, drain region are overlapping.
Space-filling outside the inherent grid of described gate groove has dielectric layer.
Described grid is identical with the shape of grid curb wall.
The material of described grid comprises the alloy of a kind of in Ti, Al and Cu or at least two kinds.
Accordingly, also provide a kind of manufacture method of MOS transistor to comprise the following steps:
Semiconductor substrate is provided, in described Semiconductor substrate, there is gate dielectric layer, pseudo-grid, and heavily doped region, source region and heavily doped region, drain region in the Semiconductor substrate of described pseudo-grid both sides, wherein, described pseudo-grid both sides also have grid curb wall;
Remove pseudo-grid to form gate groove in grid curb wall;
A side near source region in described gate groove forms grid;
Below gate groove, form LDD district, drain region taking described grid as mask.
In described gate groove, forming grid near a side in source region comprises the following steps:
Carry out inclined deposition, in the semiconductor substrate surface outside gate groove and the close gate groove in described source region, a side forms grid layer;
Oppositely grid layer described in etching, to form grid.
Described grid layer is metal material, and described inclined deposition adopts PVD technique.
The line of described inclined deposition and the angle of Semiconductor substrate are 45 degree.
Below gate groove, form LDD district, drain region taking described grid as mask and adopt ion implantation technology.
Compared with prior art, technique scheme has the following advantages:
In MOS transistor that the embodiment of the present invention provides and preparation method thereof, described grid is asymmetrical structure, be only positioned at gate groove near source region one side, in manufacturing process, utilize asymmetrical grid as mask, can form asymmetrical LDD district, save photoetching process one, can reduce cost of manufacture, and can reduction of device area occupied, be conducive to improve transistorized integrated level.
Brief description of the drawings
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the structural representation with the MOS transistor in asymmetric LDD district;
Fig. 2 to Fig. 4 is the manufacture method schematic diagram of the MOS transistor in a kind of asymmetric LDD district in prior art;
Fig. 5 to Fig. 7 is the manufacture method schematic diagram of the MOS transistor in another kind of asymmetric LDD district in prior art;
Fig. 8 is the structural representation of MOS transistor in embodiment mono-;
Fig. 9 is the flow chart of the manufacture method of MOS transistor in embodiment bis-;
Figure 10 to Figure 17 is the schematic diagram of the manufacture method of MOS transistor in embodiment bis-.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details are set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, in the time that the embodiment of the present invention is described in detail in detail; for ease of explanation; represent that the profile of device architecture can disobey general ratio and do local amplification, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
Embodiment mono-
Fig. 8 is the structural representation of MOS transistor in the present embodiment.As shown in the figure, described MOS transistor, comprising:
Semiconductor substrate 100;
Before-metal medium layer 101 in described Semiconductor substrate 100;
Gate groove 103 in grid curb wall 102 and grid curb wall 102 in described before-metal medium layer 101;
The bottom of described gate groove 103 has gate dielectric layer 108;
Source region 104 and drain region 105 in the Semiconductor substrate 100 of described gate groove 103 both sides;
Described drain region 105 has LDD district 106, and described LDD district 106 extends to described gate groove 103 belows;
The interior side near source region 104 of described gate groove 103 also comprises grid 107, is positioned at the top of described gate dielectric layer 108.
Wherein, Semiconductor substrate 100 can be the body material of elemental semiconductor or composition, the for example silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe, also can be the body material of compound semiconductor composition, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination.Described Semiconductor substrate 100 can also comprise buried oxide layer and soi layer, and the material of described soi layer can be Si, the materials such as Ge or III-V compounds of group (as SiC, GaAs, indium arsenide, indium phosphide etc.).
Described before-metal medium layer 101 is covered in whole Semiconductor substrate 100 surfaces, before-metal medium layer 101 can be that single layer structure can be also laminated construction, for example comprise the second medium layer (not shown) on first medium layer and first medium layer, adopting the structure of lamination is in order to obtain good gap filling ability and suitable stress in thin film.The formation method of before-metal medium layer 101 includes but not limited to HDPCVD, PECVD or traditional SACVD technique.
The material of before-metal medium layer 101 includes but not limited to unadulterated silicon dioxide (USG), phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), fluorine silex glass (FSG) or has a kind of or its combination in advanced low-k materials.
In the present embodiment, the grid structure of MOS transistor comprises: be positioned at successively the grid curb wall 102 of Semiconductor substrate 100 tops, gate groove 103 that grid curb wall 102 forms, gate dielectric layer 108 and gate groove 103 grid 107 near source region one sides.
Wherein, after gate groove 103 adopts, grid technique forms (seeing following examples), and described grid curb wall 102 comprises silica, silicon nitride or their lamination.
Described gate dielectric layer 108 is preferably high K medium layer, and the material of described high K medium layer can be HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2, LaAlO etc.The thickness range of high K medium layer 108 is about 1 nanometer to 3 nanometer.
Described grid 107 is metal gate, comprises Ti, Al, Cu or the alloy of at least two kinds wherein, and described metal gate also can be formed by stacking by the sandwich construction of aforementioned metal or alloy.
Different from traditional grid is, this grid 107 is not filled complete by gate groove 103, but only cover gate groove 103 and relied on the side in source region 104, preferably, grid 107 is identical with the shape of grid curb wall 102, can adopt PVD or the deposit of CVD technique, then oppositely etching forms (seeing following examples).
Described MOS transistor has asymmetrical LDD structure, and only source region 104 has LDD (lightly doped drain) district 106, and drain region 105 only has high-doped zone, there is no LDD district.The doping content in described LDD district 106 is lower than the high-doped zone in source region 104 and drain region 105, and the high-doped zone in source region 104 and drain region 105 all ends in the below of side wall 102.
Described LDD district 106 has overlapping with grid 107, between overlapping region, be separated with gate dielectric layer 108, the doping type in source region 104 and drain region 105 is contrary with the doping type of raceway groove 109, in the present embodiment, described raceway groove 109 is positioned at the below of grid 107, and it is p type impurity, and source region 104 and drain region 105 are N-type doping, in other embodiment of the present invention, the doping type in source region 104 and drain region 105 also can be identical with the doping type of raceway groove 107.
It should be noted that, source region 104 and drain region 105 in the present embodiment can exchange, but comparatively speaking, still more close source region 104 and away from drain region 105 of grid 107, and grid 107 and the distance in drain region 105 equal the width in LDD district substantially.
The grid 107 of the MOS transistor in the present embodiment is asymmetrical structure,, only be positioned at the side of gate groove 103 near source region 104, be not to fill full gate groove 103, in the manufacturing process of MOS transistor, can adopt grid 107 to form asymmetrical LDD district as mask, save cost thereby can save a step photoetching process.
In another embodiment of the present invention, the space-filling outside the inherent grid 107 of described gate groove 103 has dielectric layer 110.
In before-metal medium layer 101, also comprise through hole (not shown), be positioned at the top in described source region 104 and drain region 105, cut-off and metal contact layer (not shown) surface, this through hole is used to form the plug structure that connects source region 104 and drain region 105 and upper strata metal interconnecting layer (not shown).
In current ic manufacturing process, the grid of the CMOS technique of 22nm and following technology node are made and conventionally can be divided into front grid (gate first) technique and rear grid (gate last) technique.
After so-called, grid technique refers to: first deposit gate oxide, on gate oxide, form pseudo-grid, then form source region and drain region, then remove pseudo-grid, form gate groove, adopt again suitable metal filled gate groove to form metal gate, so, can make gate electrode avoid the high temperature of introducing while forming source region and drain region, thereby reduce transistorized threshold voltage vt drift, with respect to front grid technique, be conducive to improve the electric property of device.
Below in conjunction with accompanying drawing, later grid technique is the manufacture method that example describes above-mentioned MOS transistor in detail.
Embodiment bis-
Fig. 9 is the flow chart of the manufacture method of MOS transistor in the present embodiment, and Figure 10 to Figure 17 is the flow chart of the manufacture method of MOS transistor in the present embodiment.
The manufacture method of described MOS transistor comprises the following steps:
Step S1: shown in Figure 10, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, there are pseudo-grid 107 ', the gate dielectric layer 108 of pseudo-grid 107 ' below, and heavily doped region, source region 104 and heavily doped region, drain region 105 in the semiconductor substrate surface of described pseudo-grid 107 ' both sides, wherein, the Semiconductor substrate of pseudo-grid 107 ' below is raceway groove 109, and described pseudo-grid 107 ' both sides also have grid curb wall 102.
Pseudo-grid structure in this Semiconductor substrate 100, adopts the manufacture method of traditional MOS transistor, first forms pseudo-grid, then forms heavily doped region by Implantation, then forms grid curb wall.In addition, in Semiconductor substrate 100 surfaces, can utilize shallow trench processes (STI) to form shallow channel isolation area (not shown), the active area forming for isolating subsequent technique.
Described gate dielectric layer 108 at least comprises one deck gate oxide.Wherein, the material of gate oxide is silica or silicon oxynitride, and its thickness is for example 1nm～5nm.Preferably, described gate dielectric layer 108 is high K medium material.The material of described pseudo-grid 107 ' comprises polysilicon, adopts the etching technics of traditional polysilicon gate to form.
Referring to Figure 11, there are the Semiconductor substrate 100 surface deposition before-metal medium layers 101 of pseudo-grid structure, specifically can adopt the technique such as PECVD or HDPCVD, the material of described before-metal medium layer 101 is silica glass or silicon nitride, or well known to a person skilled in the art other materials, the combination of for example, in PSG, BSG, FSG or other low k dielectric materials one or more.
Then, utilize cmp (CMP) technique to carry out planarization to semiconductor substrate surface, comprise following two step planarizations: first step flatening process stops at hard mask layer (not shown), also remove protruding before-metal medium layer 101; Second step flatening process stops at pseudo-grid 107 ' surface, also removes hard mask layer, exposes pseudo-grid 107 '.
Step S2: remove pseudo-grid 107 ' with at the interior formation gate groove 103 of grid curb wall 102.
Concrete, referring to Figure 12, adopt wet method or plasma etching industrial to remove pseudo-grid 107 ', expose pseudo-grid 107 ' gate dielectric layer 108 below, thereby at the interior formation gate groove 103 of grid curb wall 102, for make asymmetrical grid at subsequent technique.In the etching technics of this step, etching solution or etching gas have larger etching selection ratio to polysilicon and silicon nitride.
Step S3: form grid in the interior side near source region 104 of described gate groove 103.
Concrete, comprise the following steps:
Shown in Figure 13, carry out inclined deposition, in the semiconductor substrate surface outside gate groove 103 and the close gate groove 103 in described source region 104, a side forms grid layer 111.
Described inclined deposition for example adopts metal PVD technique, the included angle A of deposition line and Semiconductor substrate 100 is about 45 degree, due to beam direction and gate groove 103 openings formation certain angles, the grid layer 111 of deposition can not be filled gate groove 103 completely, but substrate surface outside covering gate groove 103 and gate groove 103 be near the sidewall in source region 104, gate groove 103 near the sidewall in drain region 105 because the reason of line angle does not have metallic deposition under the blocking of grid curb wall 102.
Then,, shown in Figure 14, oppositely grid layer 111 described in etching, to form grid 107.
Described reverse etching can adopt isotropic plasma etching technics, remove the grid layer 111 on gate groove 103 outer-lining bottom surfaces, and repair the pattern of the interior grid layer 111 of gate groove 103 simultaneously, obtain grid 107, this grid 107 is not filled complete by gate groove 103, but only having covered gate groove 103 and rely on the side in source region 104, grid 107 is identical with the shape of grid curb wall 102.Grid 107 covers the raceway groove top of source, has formed opening 103a at drain terminal.
The material of grid layer 111 can be Al, can be also TiAlx alloy.In the time that the material of grid layer 111 is alloy, PVD technique (for example magnetron sputtering method) can adopt corresponding alloy target material or adopt the sputter of many metallic targets, in deposition process, directly forms alloyed metal (AM) layer at substrate surface.
The key of above-mentioned reverse etching technics is, controls the width of opening 103a and the width of grid 107.
Step S4: form LDD district, drain region 106 taking described grid 107 as mask below gate groove 103, shown in Figure 15, adopt ion implantation technology to the interior implanting impurity ion of Semiconductor substrate 100, due to blocking of grid 107, foreign ion is only injected in the substrate near drain region 105 1 sides, and in the substrate of source region 104 1 sides, there is no foreign ion, thereby form asymmetrical LDD plot structure.
Then, carry out annealing process, for example, adopt rapid thermal annealing, to repair lattice defect activator impurity ion, after annealing, LDD district 106 produces overlapping, shown in Figure 16 with grid 107.
In the present embodiment, described grid 107 is metal material, described inclined deposition is PVD technique, utilize so asymmetrical metal gate as mask, when metal gate can be formed, form asymmetrical LDD district, save photoetching process one, and can reduction of device area occupied, be conducive to improve transistorized integrated level.
In fact, described grid 107 can be also semi-conducting material, the composite grid of for example polysilicon and metal silicide, but need to adopt different materials from grid curb wall 102 and gate dielectric layer 108, there is larger etching selection ratio.
Finally, shown in Figure 17, in semiconductor substrate surface metallization medium layer 112, then carry out flatening process, stop at before-metal medium layer 101 surfaces, so that interior gate groove 103 remaining opening 103a is filled.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (10)
1. a MOS transistor, comprising:
Semiconductor substrate;
Before-metal medium layer in described Semiconductor substrate,
Gate groove in grid curb wall and grid curb wall in described before-metal medium layer;
Source region and drain region in the Semiconductor substrate of described gate groove both sides;
Described drain region has LDD district, and described LDD district extends to described gate groove below;
It is characterized in that,
A side near source region in described gate groove has grid, and described grid is not filled complete by described gate groove.
2. MOS transistor according to claim 1, is characterized in that, described grid and LDD district, drain region are overlapping.
3. MOS transistor according to claim 2, is characterized in that, the space-filling outside the inherent grid of described gate groove has dielectric layer.
4. according to the MOS transistor described in claim 1-3 any one, it is characterized in that, described grid is identical with the shape of grid curb wall.
5. according to the MOS transistor described in claim 1 any one, it is characterized in that, the material of described grid comprises the alloy of a kind of in Ti, Al and Cu or at least two kinds.
6. a manufacture method for MOS transistor, is characterized in that, comprises the following steps:
Semiconductor substrate is provided, in described Semiconductor substrate, there is gate dielectric layer, pseudo-grid, and heavily doped region, source region and heavily doped region, drain region in the Semiconductor substrate of described pseudo-grid both sides, wherein, described pseudo-grid both sides also have grid curb wall;
Remove pseudo-grid to form gate groove in grid curb wall;
A side near source region in described gate groove forms grid, and described grid is not filled complete by described gate groove;
Below gate groove, form LDD district, drain region taking described grid as mask.
7. the manufacture method of MOS transistor according to claim 6, is characterized in that, forms grid comprise the following steps in described gate groove near a side in source region:
Carry out inclined deposition, in the semiconductor substrate surface outside gate groove and the close gate groove in described source region, a side forms grid layer;
Oppositely grid layer described in etching, to form grid.
8. the manufacture method of MOS transistor according to claim 7, is characterized in that,
Described grid layer is metal material, and described inclined deposition adopts PVD technique.
9. the manufacture method of MOS transistor according to claim 8, is characterized in that, the line of described inclined deposition and the angle of Semiconductor substrate are 45 degree.
10. according to the manufacture method of the MOS transistor described in claim 6 to 9 any one, it is characterized in that, below gate groove, form LDD district, drain region taking described grid as mask and adopt ion implantation technology.
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| CN109216193B (en) | 2017-07-03 | 2021-08-20 | 无锡华润上华科技有限公司 | Semiconductor device and method for manufacturing the same |
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| US5869361A (en) * | 1997-07-25 | 1999-02-09 | Lg Semicon Co., Ltd. | Thin film transistor and method for fabricating the same |
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| CN1964072A (en) * | 2006-12-08 | 2007-05-16 | 北京大学 | An asymmetric Schottky barrier MOS transistor and its manufacture method |
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| US5828104A (en) * | 1994-09-01 | 1998-10-27 | Nec Corporation | MOS structure device having asymmetric LDD structure and fabrication method thereof |
| US5869361A (en) * | 1997-07-25 | 1999-02-09 | Lg Semicon Co., Ltd. | Thin film transistor and method for fabricating the same |
| CN1612358A (en) * | 2003-10-28 | 2005-05-04 | 统宝光电股份有限公司 | Thin film transistor and its manufacturing method |
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