CN102903623A - Method for manufacturing gate structure - Google Patents

Abstract

The invention relates to a method for manufacturing a gate structure. The method comprises the following steps of: providing a substrate; forming a gate dielectric layer on the substrate; depositing a sacrificial layer on the gate dielectric layer; etching the sacrificial layer to form a groove which is exposed out of the gate dielectric layer, and then depositing a gate conductive layer on the surface of the formed structure; etching the gate conductive layer from top to bottom through an anisotropic etching process until the sacrificial layer is exposed; and removing the sacrificial layer to obtain the gate structure. The method provided by the invention realizes the manufacturing of the gate structure by adopting a side wall forming process, and is especially suitable for being used for manufacturing gate structures of smaller sizes, particularly double-gate structures of smaller sizes.

Description

A kind of method of making the grid structure

Technical field

The invention belongs to the semiconductor integrated circuit manufacturing process technology field, be specifically related to a kind of method of making the grid structure.

Background technology

In the integrated circuit technology, the size of key graphic such as grid is to weigh the important indicator of performance of semiconductor device.The formation of grid structure generally adopts photoetching to add the method for etching, yet when grid size is contracted to 50nm when following, even adopt resolution enhance technology (Resolution Enhancement Technology, RET), traditional means of photolithography also can't satisfy process requirements.

At present, immersion (Emersion) photoetching or Dual graphing (Double Patterning) are adopted in the photoetching meeting of the key level in the following technology of 45nm generation.The equipment of these Technology Need costlinesses or special technological process, cost is high, complex process, difficulty is large.

Liquid immersion lithography for example, employing ArF(193nm) mask aligner is applied in the following technology of the 45nm product in generation, and in the situation that guarantees the depth of field (DOF), necessary working medium (for example, water) to improve numerical aperture (NA), this technology is called liquid immersion lithography.The cost ratio of ArF mask aligner is common will exceed approximately 50%, and this is a no small input to the manufacturer, and the production cost of photo-etching technological process is also higher in addition.

The Dual graphing technology is in order to remedy the deficiency of common photoetching function power, to utilize high-precision aligning, double exposes, technique; For the first time exposure, technique forming section figure, exposure, technique then form the figure of remaining part for the second time, like this, lithographic accuracy are doubled, and this technology generally is applied to the following technology of 32nm generation; Owing to carried out Twi-lithography, technique, cost increases; Technique is subjected to the impact of alignment precision simultaneously, and stability is not enough;

Therefore, invent a kind of new grid construction manufacturing method, especially go for making the method for reduced size grid structure, be that those skilled in the art want the technical problem that solves always.

Summary of the invention

The invention provides a kind of method of making the grid structure, the method comprises:

Substrate is provided; On described substrate, form gate dielectric layer; Deposition one deck sacrifice layer on described gate dielectric layer; The described sacrifice layer of etching forms the groove that exposes described gate dielectric layer, again at formed body structure surface deposition grid conductive layer; From top to bottom described grid conductive layer is carried out etching until expose described sacrifice layer by anisotropic etch process; Remove described sacrifice layer and obtain the grid structure.

The method of the present invention of technique scheme adopts side wall to form the making that technique has realized the grid structures, especially is fit to the double-gate structure of the grid structure, particularly reduced size of making reduced size.

Specifically, method of the present invention only needs to use conventional photoetching, the grid structure that the etching means just can be made reduced size.

At first, the thickness of described grid conductive layer has determined the live width of the grid structure that makes at last.Adopt method of the present invention, the size of grid structure does not directly depend on traditional gate figure photoetching process, and depends on the thickness of grid conductive layer and the control of anisotropic etch process.The thickness that reduces grid conductive layer just can be produced the grid structure of the in other words less live width of reduced size, this has great significance for 45nm technology following especially 32nm technology of generation following grid structure fabrication technique of generation, can use conventional photoetching, etching means, not purchase expensive immersed photoetching machine or adopt expensive double-exposure (Dual graphing) technique and do not need to drop into huge fund;

Secondly, described grid structure is formed at the inboard of described groove, that is to say, the determining positions of described groove the position of grid structures.Employing anisotropic etch process from top to bottom etching gets final product, and need not lithography registration, can reach self aligned effect.(the grid structure graph that does not have traditional grid structure graph, especially reduced size, lithography registration problem.）

Moreover, in the etch step of sacrifice layer, described groove live width is compared grid structure live width large (in general, much bigger), require relatively low (with respect to the graphical photoetching process of traditional grid structure) for the graphical photoetching process that forms groove, can use the comparatively lithographic equipment of low side.

In a specific embodiments, the thickness of described grid conductive layer is 10nm-200nm.Preferably, the thickness of described grid conductive layer is 10nm-100nm.Preferred, 10nm-80nm.Preferred, 10nm-60nm.Preferred, 10nm-50nm.

In a specific embodiments, the thickness of described sacrifice layer is 100nm-300nm.Preferably, the thickness of described sacrifice layer is 150nm-250nm.Preferably, the thickness of described sacrifice layer is 200nm.

In a specific embodiments, in described anisotropic etch process, when sacrifice layer comes out, stop etching, then replenish etching (overetch).

In a specific embodiments, in removing described sacrifice layer step, the ratio of the etch rate of the etch rate of described sacrifice layer and described grid conductive layer and gate dielectric layer is all greater than 200.Namely select with grid conductive layer and compare the material making sacrifice layer with higher corrosion selection ratio with gate dielectric layer.Preferably, in removing described sacrifice layer step, the ratio of the etch rate of the etch rate of described sacrifice layer and described grid conductive layer and gate dielectric layer is all greater than 200.

In a specific embodiments, described grid conductive layer adopts polycrystalline silicon material.

Described gate dielectric layer adopts silica, silicon nitride, silicon oxynitride or high dielectric constant material, and perhaps any one coats the complex that high dielectric constant material forms in silica, silicon nitride, the silicon oxynitride.

Described high dielectric constant material refers to that dielectric constant is greater than the material more than 3.9.

The thickness of described gate dielectric layer is 3 ~ 300 dusts.

In a further preferred embodiment, described sacrifice layer adopts silicon nitride material.Preferably, the etching solution that adopts of the step of described removal sacrifice layer is hot phosphoric acid solution.

The employed hot phosphoric acid etching solution of the semiconductor manufacturing that described hot phosphoric acid solution is well known to those skilled in the art.

Description of drawings

Fig. 1-Fig. 5 shows the process (cross section view) of the making grid structural approach of the embodiment of the invention 1.

Embodiment

Fig. 1-Fig. 5 shows the process (cross section view) of the making grid structural approach of the embodiment of the invention 1.

Referring to Fig. 1,

Substrate 10 is provided; On substrate 10, form gate dielectric layer 20; Deposition one deck sacrifice layer 30 on gate dielectric layer 20.

Substrate 10 is silicon substrate, has formed two device isolation layers 11,12 in the substrate 10.Two device isolation layers 11,12 general 10 nmos area and the PMOS districts of being used at the bottom of the isolation liner.Device isolation layer is to form from (STI) method by shallow trench isolation.Formed trap 13 between two device isolation layers 11,12.

Gate dielectric layer generally adopts oxide, nitride or nitrogen oxide or complex.Gate dielectric layer 20 adopts silica in the present embodiment.Gate dielectric layer 20 thickness are about 200 dusts.

Sacrifice layer 30 adopts silicon nitride material, and the thickness of sacrifice layer 30 has determined the height of grid structures, and in the present embodiment, sacrificial layer thickness is about 200nm.

Referring to Fig. 2,

Etching sacrificial layer 30 forms the groove 31 that exposes gate dielectric layer 20.

Form the technique of groove 31, specifically, at first at sacrifice layer 30 surperficial spin coating photoresists, go out the figure of groove 31 by lithographic definition, form the groove 31 that exposes gate dielectric layer 20 by etching again.

In the etch step of sacrifice layer 30, it is large (in general that described groove 31 live widths are compared grid structure live width to be formed, much bigger), require relatively low (with respect to the graphical photoetching process of traditional grid structure) for the graphical photoetching process that forms groove 31, can use comparatively photoetching, the etching apparatus of low side.

The figure of groove 31 depends on figure and the position of double-gate structure to be formed, is the figure of groove 31 after the figure between double-gate structure figure and the double grid merges.

Referring to Fig. 3,

Again at the formed body structure surface deposition of Fig. 2 grid conductive layer 40.

Grid conductive layer 40 adopts polycrystalline silicon material, the about 50nm of the thickness of grid conductive layer 40.The thickness of grid conductive layer 40 has determined the live width of the grid structure that makes at last.The size of grid structure does not directly depend on traditional gate figure photoetching process, and the thickness that reduces grid conductive layer just can be produced the grid structure of the in other words less live width of reduced size.

Referring to Fig. 4,

From top to bottom grid conductive layer 40 is carried out etching until expose sacrifice layer 30 by anisotropic etch process.

When etching into the exposure silicon nitride, then replenish etching (overetch).

As shown in Figure 4, the lateral part of grid conductive layer 40 all is etched, only kept groove 31 inboards with sacrifice layer 30 with high two longitudinal components 41,42, i.e. double-gate structure 41,42.

Referring to Fig. 5,

Adopt hot phosphoric acid solution (temperature 160C, concentration 85%) to remove sacrifice layer 30 and obtain double-gate structure 41,42.

The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.

Claims (7)

1. method of making the grid structure, the method comprises:

Substrate is provided;

On described substrate, form gate dielectric layer;

Deposition one deck sacrifice layer on described gate dielectric layer;

The described sacrifice layer of etching forms the groove that exposes described gate dielectric layer, again at formed body structure surface deposition grid conductive layer;

From top to bottom described grid conductive layer is carried out etching until expose described sacrifice layer by anisotropic etch process;

Remove described sacrifice layer and obtain the grid structure.

2. the method for claim 1 is characterized in that:

The thickness of described grid conductive layer is 10nm-200nm.

3. the method for claim 1 is characterized in that:

The thickness of described sacrifice layer is 100nm-300nm.

4. such as the described method of any one among the claim 1-3, it is characterized in that:

Described grid conductive layer adopts polycrystalline silicon material.

5. method as claimed in claim 4 is characterized in that:

Described sacrifice layer adopts silicon nitride material.

6. method as claimed in claim 5 is characterized in that:

The etching solution that the step of described removal sacrifice layer adopts is hot phosphoric acid solution.

7. method as claimed in claim 5 is characterized in that:

Described gate dielectric layer adopts silica, silicon nitride, silicon oxynitride or high dielectric constant material, and perhaps any one coats the complex that high dielectric constant material forms in silica, silicon nitride, the silicon oxynitride.

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