KR0166832B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR0166832B1
KR0166832B1 KR1019950046364A KR19950046364A KR0166832B1 KR 0166832 B1 KR0166832 B1 KR 0166832B1 KR 1019950046364 A KR1019950046364 A KR 1019950046364A KR 19950046364 A KR19950046364 A KR 19950046364A KR 0166832 B1 KR0166832 B1 KR 0166832B1
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forming
silicide
gate electrode
film
gate
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KR1019950046364A
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KR970054447A (en
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유성욱
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자에 관한 것으로, 반도체 기판의 소정영역에 필드 산화막을 형성하여 활성영역을 패터닝하는 공정과, 상기 활성영역상에 게이트 산화막과 폴리실리콘막을 적층하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극을 마스크로 저농도의 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 공정과, 상기 게이트 전극 측면에 측벽을 형성하고 고농도의 불순물 이온주입을 실시하는 공정과, 기판 전면에 실리사이드막을 형성하고, 상기 실리사이드막에 이온주입 공정으로 실리콘 이온을 도핑하는 공정과, 상기 실리사이드막상에 캡 산화막을 적층하고 게이트 전극 상측에만 남도록 캡 산화막, 실리사이드막을 선택적으로 제거하는 공정을 포함하여 이루어져 실리사이드의 들뜸현상을 방지하고 게이트 저항의 증가를 억제시킬수 있어 소자의 특성을 향상시키는 효과가 있다.The present invention relates to a semiconductor device, comprising: forming a field oxide film in a predetermined region of a semiconductor substrate to pattern an active region; forming a gate electrode by laminating a gate oxide film and a polysilicon film on the active region; Forming a source / drain region by performing a low concentration ion implantation process using a gate electrode as a mask, forming a sidewall on the side of the gate electrode and performing a high concentration of impurity ion implantation, and forming a silicide film on the entire substrate And a step of doping silicon ions into the silicide layer by an ion implantation process, and laminating a cap oxide layer on the silicide layer and selectively removing the cap oxide layer and the silicide layer so as to remain only on the upper side of the gate electrode. Prevent and suppress the increase of gate resistance It may be the effect of improving the characteristics of the element.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

제1도 (a)(b)는 종래의 반도체 소자의 공정단면도.1 (a) and (b) are process cross-sectional views of a conventional semiconductor device.

제2도 (a) 내지 (h)는 본 발명의 반도체 소자의 공정단면도.2 (a) to (h) are process cross-sectional views of a semiconductor device of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21 : 반도체 기판 22 : 필드 산화막21 semiconductor substrate 22 field oxide film

23 : 게이트 산화막 24 : 폴리 실리콘층23 gate oxide film 24 polysilicon layer

25,26 : 소오스/드레인 영역 27 : 측벽25, 26 source / drain regions 27 sidewalls

28 : 실리사이드막 29 : 캡 산화막28: silicide film 29: cap oxide film

30 : 유전체층 31 : 금속 배선30 dielectric layer 31 metal wiring

본 발명은 반도체 소자에 관한 것으로, 특히 실리사이드 형성공정시에 실리사이드 표면에 실리콘 이온을 도핑하여 실리사이드의 들뜸현상을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can prevent the lifting of silicide by doping silicon ions on the surface of the silicide during the silicide formation process.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

제1도(a)(b)는 종래의 반도체 소자의 공정단면도이다.(A) and (b) are process cross-sectional views of a conventional semiconductor device.

먼저, 제1도(a)에서와 같이, 반도체 기판(1)에 액티브 마스크를 이용하여 활성영역을 정의하고 필드영역에 필드 산화막(2)을 형성한다.First, as shown in FIG. 1A, an active region is defined in the semiconductor substrate 1 using an active mask, and a field oxide film 2 is formed in the field region.

그리고 전면에 게이트 절연을 위한 게이트 산화막(3) 및 폴리 실리콘층(4)을 형성한다.A gate oxide film 3 and a polysilicon layer 4 are formed on the entire surface for gate insulation.

이어, 상기 폴리 실리콘층(4) 및 게이트 산화막(3)을 채널영역상에만 남도록 식각하여 게이트 전극을 형성한다.Subsequently, the polysilicon layer 4 and the gate oxide layer 3 are etched to remain only in the channel region to form a gate electrode.

그리고 상기 게이트 전극상에 실리사이드(5)와 캡 산화막(6)을 형성한다.The silicide 5 and the cap oxide film 6 are formed on the gate electrode.

이어, 제1도(b)에서와 같이, 상기 게이트 전극을 마스크로 하여 저농도 불순물 이온주입 공정을 실시하여 소오스 및 드레인 영역(8)(9)을 형성한다.Subsequently, as shown in FIG. 1 (b), the source and drain regions 8 and 9 are formed by performing a low concentration impurity ion implantation process using the gate electrode as a mask.

그리고 상기 게이트 전극의 측면에 측벽(Side Wall)을 형성하고 고농도 불순물 이온주입을 실시하여 LDD 구조의 소오스/드레인 영역(8)(9)을 형성한다.Sidewalls are formed on the side surfaces of the gate electrode and high concentration impurity ion implantation is performed to form source / drain regions 8 and 9 of the LDD structure.

상기와 같이 실리사이드가 게이트로 사용되는 이유는 다음과 같다.The reason why the silicide is used as a gate as described above is as follows.

반도체 소자의 고집적화 및 고속화 추세에 따라 소자들이 소형화 되고 있다.The trend toward higher integration and higher speed of semiconductor devices has resulted in smaller devices.

상기와 같은 소자의 소형화는 결국 게이트의 폭을 좁게 형성하는 방향으로 나가고 있다.The miniaturization of such a device eventually leads to a direction in which the width of the gate is narrowly formed.

그러나 게이트 폭의 축소는 게이트 저항의 증가 등의 문제를 발생하게 되는데, 상기와 같은 게이트 저항을 줄이기 위하여 낮은 저항과 융점을 갖는 실리사이드가 게이트로 사용되는 것이다.However, the reduction of the gate width causes problems such as an increase in the gate resistance. In order to reduce the gate resistance, silicide having a low resistance and a melting point is used as the gate.

그리고 게이트 폭의 축소는 채널의 길이를 짧게 하여 핫 캐리어 현상을 유발시킨다.Reducing the gate width shortens the length of the channel, causing hot carriers.

이와 같은 핫 캐리어 현상을 방지하기 위하여 LDD 구조를 채택하게 된다.In order to prevent such hot carrier phenomenon, an LDD structure is adopted.

그러나 상기와 같은 종래의 반도체 소자에 있어서는 다음과 같은 문제점이 있었다.However, the above conventional semiconductor device has the following problems.

게이트 저항을 줄이기 위해 도입된 실리사이드층은 초기 증착시에 비정질 상태이므로 저항을 낮추기 위해 결정화를 시켜야 했다.The silicide layer introduced to reduce the gate resistance was amorphous during initial deposition and had to be crystallized to lower the resistance.

즉, 실리사이드 열처리 과정을 해야 하는데, 상기와 같은 열처리 과정에서는 원자의 이동도가 향상되어 실리사이드의 실리콘 원자가 실리사이드 표면과 실리사이드-다결정 실리콘 계면으로 확산되어 실리사이드의 실리콘 농도가 줄어들어 초기 증착시의 실리사이드 조성과 열처리 후의 조성이 차이를 갖는다.That is, the silicide heat treatment process should be performed. In the above heat treatment process, the mobility of atoms is improved, and silicon atoms of the silicide diffuse to the silicide surface and the silicide-polycrystalline silicon interface, so that the silicon concentration of the silicide is reduced, and thus the silicide composition during the initial deposition and The composition after the heat treatment has a difference.

상기와 같은 실리사이드의 조성차이는 결국 체적변화를 일으켜 실리사이드층의 들뜸 현상을 일으키게 된다.The difference in the composition of the silicide as described above eventually causes a volume change to cause the silicide layer to rise.

또한 실리사이드-다결정 실리콘 기면으로의 실리콘 원자확산은 다결정 실리콘의 두께를 증가시켜 게이트 저항을 증가시킨다.The diffusion of silicon into the silicide-polycrystalline silicon substrate also increases the gate resistance by increasing the thickness of the polycrystalline silicon.

본 발명은 상기와 같은 종래의 반도체 소자의 문제점을 해결하기 위한 것으로, 실리사이드 형성 공정시에 실리사이드 표면에 실리콘 이온을 도핑하여 실리사이드의 들뜸현상을 방지하고, 소자의 특성을 향상시킬수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the conventional semiconductor device as described above, to prevent the lifting of the silicide by doping the silicon ions on the surface of the silicide during the silicide formation process, the production of a semiconductor device that can improve the characteristics of the device The purpose is to provide a method.

상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판의 소정영역에 필드 산화막을 형성하여 활성영역을 패터닝 하는 공정과, 상기 활성영역상에 게이트 산화막과 폴리 실리콘막을 적층하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극을 마스크로 저농도의 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 공정과, 상기 게이트 전극 측면에 측벽을 형성하고 고농도의 불순물 이온주입을 실시하는 공정과, 기판 전면에 실리사이드막을 형성하고, 상기 실리사이드막에 이온주입 공정으로 실리콘 이온을 도핑하는 공정과, 상기 실리사이드막상에 캡 산화막을 적층하고 게이트 전극 상측에만 남도록 캡 산화막, 실리사이드막을 선택적으로 제거하는 공정을 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object is a step of forming a field oxide film in a predetermined region of the semiconductor substrate to pattern the active region, the gate oxide film and a polysilicon film laminated on the active region to the gate electrode Forming a source / drain region by performing a low concentration ion implantation process using the gate electrode as a mask, forming a sidewall on the side of the gate electrode, and performing a high concentration impurity ion implantation; Forming a silicide film on the entire surface of the substrate, doping silicon ions into the silicide film by an ion implantation process, and laminating a cap oxide film on the silicide film and selectively removing the cap oxide film and the silicide film so as to remain only on the upper side of the gate electrode. Characterized in that made.

이하, 첨부된 도면을 참고하여 본 발명의 반도체 소자의 제조방법에 대하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

제2도 (a) 내지 (h)는 본 발명의 반도체 소자의 공정단면도이다.2 (a) to (h) are process cross-sectional views of the semiconductor device of the present invention.

본 발명의 반도체 소자는 게이트 상측의 실리사이드막의 들뜸현상을 방지하기 위한 것으로, 먼저 제2도(a)에서와 같이, 반도체 기판(21)의 소정영역에 필드 산화막(22)을 형성하여 활성영역을 형성하고 전면에 게이트 산화막(23)과 폴리 실리콘층을 차례로 형성한 다음 채널영역상에만 남도록 식각하여 게이트 전극을 형성한다.The semiconductor device of the present invention is to prevent the floating phenomenon of the silicide film on the upper side of the gate. First, as shown in FIG. 2A, a field oxide film 22 is formed in a predetermined region of the semiconductor substrate 21 to form an active region. The gate oxide layer 23 and the polysilicon layer are sequentially formed on the entire surface, and then etched to remain only on the channel region to form a gate electrode.

이어 제2도 (b)에서와 같이, 상기 게이트 전극을 마스크로 저농도의 불순물 이온주입 공정을 실시하여 소오스/드레인 영역(25)(26)을 형성한다.Next, as shown in FIG. 2B, source / drain regions 25 and 26 are formed by performing a low concentration impurity ion implantation process using the gate electrode as a mask.

그리고 제2도 (c)에서와 같이, 상기 게이트 전극 측면에 측벽(Side Wall)을 형성한 후 고농도의 불순물 이온주입 공정을 실시하여 LDD 구조의 소오스/드레인 영역(25)(26)을 형성한다.As shown in FIG. 2 (c), a side wall is formed on the side of the gate electrode, and a high concentration of impurity ion implantation process is performed to form source / drain regions 25 and 26 having an LDD structure. .

이어 제2도 (d)에서와 같이, 전면에 화학기상 증착법에 의해 실리사이드막(28)을 형성한다.Subsequently, as shown in FIG. 2 (d), the silicide film 28 is formed on the entire surface by chemical vapor deposition.

그리고 제2도 (e)에서와 같이, 사이렌(SiH4) 가스를 이용하여 실리콘(Si) 이온을 상기 실리사이드막(28)에 도핑한다.As illustrated in FIG. 2E, silicon (Si) ions are doped into the silicide layer 28 using a siren (SiH 4) gas.

이어 제2도 (f)에서와 같이, 실리사이드막(28)상에 캡 산화막(29)을 형성하고, 게이트 전극 상측에만 남도록 제2도 (g)에서와 같이, 캡 산화막(29), 실리사이드막(28)을 차례대로 식각한다.Subsequently, as shown in FIG. 2 (f), the cap oxide film 29 is formed on the silicide film 28, and the cap oxide film 29 and the silicide film are formed as shown in FIG. Etch 28 in order.

그리고 제2도 (h)에서와 같이, 전면에 유전체층(30)을 형성하고 선택적으로 식각하여 콘택홀을 형성한다.As shown in FIG. 2 (h), the dielectric layer 30 is formed on the entire surface and selectively etched to form contact holes.

이어 상기 콘택홀상에 금속 배선(31)을 형성한다.Subsequently, a metal wiring 31 is formed on the contact hole.

상기와 같은 본 발명의 반도체 소자는 게이트 저항을 낮추기 위해서 폴리 실리콘층(24)상에 실리사이드막(28)을 형성하였다.In the semiconductor device of the present invention as described above, the silicide layer 28 is formed on the polysilicon layer 24 to lower the gate resistance.

그리고, 상기와 같이, 게이트 저항을 낮추기 위하여 적층된 실리사이드막(28)의 결정화를 위한 열처리 과정을 수행하는 동안에 실리사이드막(28)의 들뜸현상을 막기 위하여 사이렌(SiH4) 가스를 이용하여 이온화된 사이렌 가스 중에 실리콘 1가 이온(Si +)만을 포집하여 실리사이드막(28) 상부에 도핑한 것이다.As described above, the siren ionized by using a siren (SiH 4) gas to prevent lifting of the silicide layer 28 during the heat treatment process for crystallization of the stacked silicide layer 28 to lower the gate resistance. Silicon monovalent ions in the gas (Si Only +) is collected and doped over the silicide layer 28.

상기와 같은 본 발명의 반도체 소자의 제조방법에 있어서는 실리사이드의 열처리 과정에서 발생하는 실리콘 원자의 확산을 사이렌 가스를 이용하여 도핑된 실리콘 이온(Si+)이 막아 실리사이드막의 들뜸현상을 막고, 실리콘 원자 확산을 위한 폴리 실리콘막의 두께증가를 막아 게이트 저항의 증가를 억제시킬수 있으므로 소자의 특성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention as described above, silicon ions (Si + ) doped with a siren gas are prevented from diffusing silicon atoms generated during the heat treatment of the silicides, thereby preventing the silicide film from being lifted up and diffusing the silicon atoms. Since the increase in the gate resistance can be suppressed by increasing the thickness of the polysilicon film for the purpose, there is an effect of improving the characteristics of the device.

Claims (2)

반도체 기판의 소정영역에 필드 산화막을 형성하여 활성영역을 패터닝 하는 공정과, 상기 활성영역상에 게이트 산화막과 폴리 실리콘막을 적층하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극을 마스크로 저농도의 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 공정과, 상기 게이트 전극 측면에 측벽을 형성하고 고농도의 불순물 이온주입을 실시하는 공정과, 기판 전면에 실리사이드막을 형성하고, 상기 실리사이드막에 이온주입 공정으로 실리콘 이온을 도핑하는 공정과, 상기 실리사이드막상에 캡 산화막을 적층하고 게이트 전극 상측에만 남도록 캡 산화막, 실리사이드막을 선택적으로 제거하는 공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조방법.Forming an active region by forming a field oxide film in a predetermined region of the semiconductor substrate, forming a gate electrode by laminating a gate oxide film and a polysilicon film on the active region, and implanting a low concentration of ion using the gate electrode as a mask Forming a source / drain region by performing a step; forming a sidewall on the side of the gate electrode; implanting a high concentration of impurity ions; forming a silicide film on the entire surface of the substrate; and implanting an ion implantation process on the silicide film. And a step of stacking a cap oxide film on the silicide film and selectively removing the cap oxide film and the silicide film so as to remain only on the upper side of the gate electrode. 제1항에 있어서, 실리사이드막에 실리콘 이온을 도핑하는 공정은 사이렌(SiH4) 가스를 이용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the step of doping silicon ions into the silicide film uses siren (SiH 4 ) gas.
KR1019950046364A 1995-12-04 1995-12-04 Fabrication method of semiconductor device KR0166832B1 (en)

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