JPH05343426A - Field-effect semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To ensure stable operation characteristic by covering regions of insulation films consisting of a silicon oxide film or the like with an oxidation proof insulation film which does not allow contaminants and impurity to pass therethrough. CONSTITUTION:An oxidation proof insulation film 20a is formed by a silicon nitride film on a silicon oxide film 19 covering a gate electrode 16. A oxidation proof insulation film 20b is formed, in the same manner, with a silicon nitride film on an isolation silicon oxide film 13. The regions of silicon oxide films of the portion other than the gate electrode 16 are covered with the oxidation proof insulation films 20a, 20b which do not allow contaminants and impurity to pass therethrough. Accordingly, entry of these contaminants and impurities can be prevented efficiently. Thereby, long term reliability such as operation characteristics of the device structure can be improved effectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device and a method for manufacturing the same, and more particularly to an improvement in a field effect semiconductor device capable of high speed operation and a method for manufacturing the same.

[0002]

2. Description of the Related Art A schematic structure of a field effect type semiconductor device of this type according to a conventional example is schematically shown in FIG. 12, and main steps of a method for manufacturing the field effect type semiconductor device are shown in FIGS. It shows in order typically.

First, the configuration of the field effect semiconductor device in this conventional example will be described.

That is, in the structure of the conventional device shown in FIG. 12, reference numeral 31 is a p-type (first conductivity type in this case) single crystal silicon semiconductor substrate, and 32 is one of the main components of the p-type silicon substrate 31. A silicon oxide film embedded on the surface, 33 is a thick insulating film for insulating and separating the semiconductor elements (semiconductor devices), for example, a separated silicon oxide film, 3
4 is a p-type silicon substrate 3 due to the silicon oxide film 32.
1 is a p-type active region which is selectively formed by being electrically insulated from 1; 35 is a thin gate oxide film on the p-type active region 34; and 36 is a gate electrode.

Further, 37 and 38 are the p-type active regions 34.
N-type (second conductivity type in this case) low-concentration source region and high-concentration source region that are sequentially formed selectively in contact with one of the other regions, and 39 and 40 are also the other regions of the p-type active region 34. And an n-type low-concentration drain region and a high-concentration drain region which are sequentially formed in contact with the source side silicide layer 41a and a source-side silicide layer 41b formed on the high-concentration source region 38, respectively. This is a drain-side silicide layer formed on the high-concentration drain region 40.

Further, 42a and 42b are side insulating films formed on the peripheral side of the gate electrode 36, for example, side silicon oxide films, and 43 is an interlayer insulating film, 4
Reference numerals 4 and 45 denote source electrodes and drain electrodes connected to the silicide layers 41a and 41b through the contact openings of the interlayer insulating film 43.

However, in this type of field effect semiconductor device, in the usual case, the thickness of the depletion layer that can spread from the gate electrode 36 side is made thicker than the thickness ts of the p-type active region 34. In consideration of this, by setting the impurity concentration of the p-type active region 34, the entire region of the p-type active region 34 is depleted during operation of the device.

The reason why the device is constructed in this manner is that the effective electric field strength in the p-type active region 34 is reduced to lower the mobility of the inversion layer carriers immediately below the gate insulating film 37. This is because it is possible to suppress the above, and to increase the drain current accordingly, and to increase the drain current with the increase of the inversion layer carriers corresponding to the decrease of the charge amount in the depletion layer in the p-type active region 34.

In the case of the field effect semiconductor device having this structure, the p-type active region 34 is formed by the gate electric field.
Since the inside is depleted,
It is possible to suppress the entry of the drain electric field into the p-type active region 34, which makes it possible to suppress the so-called short channel effect of the threshold voltage, and as a result, in such a device structure, It is expected that both high integration of the device due to the miniaturization of the device and high-speed operation of the device can be expected, and its future potential is attracting attention in recent years.

Next, a method of manufacturing the field effect type semiconductor device of this type according to the conventional example will be described.

First, p in which the silicon oxide film 32 is embedded
The surface of the separately formed single crystal silicon layer 46 on the type single crystal silicon semiconductor substrate 31 is oxidized to form a silicon oxide film 47, on which an oxidation resistant film such as silicon nitride is formed. A film 48 is deposited (see FIG.
3) And, after the silicon nitride film 48 is selectively processed into a predetermined size by, for example, an anisotropic plasma etching method, the remaining silicon nitride film 48a is used as a mask to form the silicon oxide film. The exposed corresponding portion of 47 is selectively removed by etching to shape the silicon oxide film 47a, and similarly, the exposed silicon layer 46 is selectively removed until it reaches the silicon oxide film 32. Oxidation treatment is performed to form an isolation silicon oxide film 33 for element isolation, and the remaining silicon layer 46 is formed.
a is electrically isolated from the other silicon layers (see FIG. 1).
4).

Then, after removing the silicon nitride film 48a, a p-type impurity is introduced into the silicon layer 46a through the silicon oxide film 47a by, for example, an ion implantation method, and after this introduction, this silicon is removed. Silicon layer 4 with oxide film 47a removed and p-type impurities introduced
6a is exposed, and a new thin silicon oxide film, here, a gate oxide film 35 is formed on the p-type silicon layer 46a, and the gate oxide film 35 is formed.
A silicon layer for a gate electrode is deposited thereon, and this is processed into a predetermined size by anisotropic plasma etching or the like to form a gate electrode 36, and further, an oxidation process is performed on these, Similarly, a silicon oxide film 49 is formed, and thereafter, an n-type impurity is introduced into the p-type silicon layer 46a through the silicon oxide film 19 by, for example, an ion implantation method, and the n-type low concentration source region 3 is formed.
7 and the low concentration drain region 39 are formed in each (FIG. 15).

Next, another silicon oxide film 42 is deposited on the silicon oxide film 49 including the gate electrode 36, and then the n-type low concentration source is formed by, for example, anisotropic plasma etching. The silicon oxide films 32 and 39 are removed by etching until the region 37 and a part of the low-concentration drain region 39 side are exposed, and the silicon oxide films 49a and 4a are formed on the peripheral side portions of the gate electrode 36.
2a and 42b are selectively left, and the surfaces of the partially exposed n-type low-concentration source region 37 and low-concentration drain region 39 are slightly oxidized to form a silicon oxide film. , The n-type low-concentration source region 37 partially exposed by ion implantation or the like,
And n-type impurities are introduced into the low-concentration drain region 39 to form the n-type high-concentration source region 38 and the high-concentration drain region 40, respectively, and then the surface silicon oxide film is removed. (FIG. 16).

Subsequently, the gate electrode 36 covered with the silicon oxide films 49a and 42a, 42b, the n-type high-concentration source region 38, and the high-concentration drain region 4 are continuously formed.
0, a transition metal layer 50 such as titanium (Ti) is deposited (FIG. 17), and this is heat treated in an inert gas atmosphere and selectively etched and shaped, Source-side and drain-side silicide layers 41a and 41b are formed on the n-type high-concentration source region 38 and the high-concentration drain region 40, respectively (FIG. 18). 43 is deposited, and the source electrode 44 and the drain electrode 45 are connected to the silicide layers 41a and 41b through the contact openings of the interlayer insulating film 43 (FIG. 19). The intended field effect semiconductor device is manufactured.

[0015]

However, in the field effect semiconductor device according to the conventional example, the high concentration regions 38 and 40 of the source / drain are thinned like the active region 33 because of ease of manufacturing. Because it is configured as
There is a problem that the parasitic resistance of the high-concentration regions 38 and 40 of the source / drain increases and the performance of the device cannot be effectively obtained.

Therefore, in order to avoid such drawbacks, as one means for reducing the resistance of the high concentration regions 38, 40 of the source / drain, as described above, the high concentration regions 38, 40 of the source / drain concerned. 40 on the source side and the silicide layer 41a on the drain side,
41b is formed. In this means, as will be described in detail below, the long-term reliability of the device configuration is deteriorated, the characteristics are deteriorated due to the diffusion of impurities in the silicide source metal, and the like. Was to occur.

That is, for example, as shown in FIG. 20, at the time of impurity implantation for forming the high concentration source / drain regions 38 and 40 in the manufacturing process shown in FIG. Since the vicinity of the surface of each side silicon oxide film 42a, 42b in 36 and the isolation silicon oxide film 33 for element isolation and the like is contaminated by the implanted impurities, each side silicon oxide film 42a, 42b. Membrane 4
2a, 42b, the isolation silicon oxide film 33, etc.,
A local reaction occurs with the transition metal layer 50, and conductive foreign substances A and B are generated on the respective oxide films to cause a leak current between the source and the drain and a leak current between the elements.

Similarly, in removing the silicon oxide films 32 and 39 by the anisotropic plasma etching method in the manufacturing process shown in FIG. 16, etching plasma is applied to the high-concentration source / drain regions 38 and 40. Touching each of the high-concentration source / drain regions 3
The crystallinity of Nos. 8 and 40 deteriorates. For this reason, during the reaction of forming the silicide layers 41a and 41b on the source side and the drain side, for example, the reaction unevenness indicated by the symbols C ₁ , C ₂ , C _3, etc. It may occur, and even partially penetrates to the substrate side.

Furthermore, since most of the entire device is covered with an insulating film such as a silicon oxide film, which cannot necessarily prevent the invasion of impurities, the transition metal of the silicide raw material, moisture, etc. may invade. This impairs the long-term reliability of the operating characteristics of the device.

As described above, in the case of the field effect type semiconductor device according to the conventional example, in spite of having some great features in itself, at the same time, on the other hand, there are various disadvantages as described above. However, there was a problem in its practical application.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object of the present invention is to configure each silicide layer provided for reducing the resistance of the source / drain regions, In addition to improving the manufacturing method to stabilize the operating characteristics and ensure long-term reliability,
It is an object of the present invention to provide a field-effect semiconductor device of this type that enables high-speed operation and a method of manufacturing the same.

[0022]

In order to achieve the above-mentioned object, a field effect semiconductor device and a method of manufacturing the same according to the present invention include a method of manufacturing a semiconductor device, in which a silicide layer is not provided in each part and each region. The main feature of each is that they are insulation-coated with an oxidation-resistant insulating film that is excellent in preventing contaminants from entering.

That is, according to the present invention, a first-conductivity-type first semiconductor layer having a predetermined dimension is formed on the first insulating film embedded in a semiconductor substrate by being divided by an isolation insulating film,
A second semiconductor layer having a predetermined size and serving as a gate electrode formed on the first semiconductor layer via a second insulating film serving as a gate insulating film, and covering the second semiconductor layer. A third insulating film, a peripheral side portion of the second semiconductor layer covered with the third insulating film, and a fourth oxidation resistant insulating film provided on the isolation oxide film, respectively. In the first semiconductor layer, the second semiconductor layer, the active region of the first conductivity type left corresponding to the second insulating film, and the impurity of the second conductivity type are formed. Peripheral side portions of the second semiconductor layer covered with the third insulating film and having a fourth oxidation resistant insulating film interposed therebetween, and the second conductivity type impurity regions serving as the source / drain, A fifth insulating film respectively formed on the fourth oxidation resistant insulating film of the isolation insulating film,
A field-effect semiconductor device comprising at least each silicide formed on each of the impurity regions.

Further, according to the present invention, a step of forming a first semiconductor layer of a first conductivity type having a predetermined size divided by an isolation insulating film on a first insulating film embedded in a semiconductor substrate, A second insulating film, which will be a gate insulating film, is formed on the first semiconductor layer.
Forming an insulating film, and forming a second semiconductor layer having a predetermined size to serve as a gate electrode through the second insulating film, a first semiconductor layer including the second semiconductor layer, and A step of sequentially forming a third insulating film and a fourth oxidation resistant insulating film on the isolation insulating film, and the step of passing the first oxidation resistant insulating film and the third insulating film through the first insulating film. Second conductivity type impurities are introduced into the second semiconductor layer, and the first conductivity type active regions are left in the portions corresponding to the second semiconductor layer and the second insulating film to become the source / drain. A step of forming impurity regions of two-conductivity type respectively, and a step of forming a fifth insulating film on the fourth oxidation resistant insulating film,
The fifth insulating film portion corresponding to each of the impurity regions is selectively removed to be covered with the third insulating film, and
Leaving the fifth insulating film on the peripheral side portion of the second semiconductor layer with the oxidation resistant insulating film interposed and on the fourth oxidation resistant insulating film of the isolation insulating film, respectively. The oxidation resistant insulating film portion is selectively removed to expose the impurity regions, and a transition metal layer is formed to include the exposed impurity region portions. And a step of forming corresponding silicide layers on the impurity regions, respectively, at least.

[0025]

Therefore, according to the present invention, the interposition of the oxidation resistant insulating film can effectively prevent the invasion of contaminants into the device structure during the formation of the respective silicide layers.
It is possible to easily prevent intrusion of moisture contained in the insulating film used for insulating the wiring and the like.

[0026]

Embodiments of the field effect semiconductor device and the method of manufacturing the same according to the present invention will be described below with reference to FIGS.
It will be described in detail with reference to FIGS.

FIG. 1 is a sectional view schematically showing a schematic structure of a field effect semiconductor device to which an embodiment of the present invention is applied, in this case, an n channel type field effect semiconductor device. 2 to 11 show n according to the above-described embodiment.
FIG. 6 is a cross-sectional view for sequentially schematically showing main steps in a method for manufacturing a channel-type field effect semiconductor device.

In this case as well, the structure of the n-channel field effect semiconductor device according to this embodiment will be described first.

That is, in the configuration of the conventional device shown in FIG. 1, reference numeral 11 in this case is, for example, a p-type (here, first conductivity type) single crystal silicon semiconductor substrate, and 12 is the p-type silicon substrate. An insulating film embedded on one main surface of 11, for example, a silicon oxide film (first insulating film), 13 is a thick insulating film for insulating and separating semiconductor elements (semiconductor devices), for example, isolated silicon oxide. Shows the membrane, 1
4 is a p-type silicon substrate 1 due to the silicon oxide film 12
1 is a p-type active region (first single crystal semiconductor layer) selectively formed electrically insulated from 1, and 15 is a gate oxide film such as a thin silicon oxide film on the p-type active region 14 (second Insulating film), 16 is a gate electrode (second semiconductor layer) made of a polycrystalline silicon layer or the like.

Reference numeral 17 is an n-type (second conductivity type in this case) selectively formed in contact with one of the p-type active regions 14.
Of the n-type high-concentration drain region (the other impurity region) selectively formed in contact with the other of the p-type active region 14 in the same manner. The silicon oxide film (third insulating film) 20a covering the gate electrode 16 is an oxidation resistant insulating film (fourth insulating film) such as a silicon nitride film formed on the silicon oxide film 19 covering the gate electrode 16. Oxidation resistant insulation film),
Similarly, 20b is an oxidation resistant insulating film (fourth silicon nitride film, etc.) formed on the isolation silicon oxide film 13.
21a is the gate electrode 1
The oxidation resistant insulating film 20a is formed on the silicon oxide film 19 which covers 6
Is formed on the isolation silicon oxide film 13 via the oxidation resistant insulating film 20b. , A silicon oxide film (fifth insulating film), for example.

Further, 22a is the high-concentration source region 1
7 is a source side silicide layer, 22b is a drain side silicide layer formed on the high concentration drain region 18, 23 is an interlayer insulating film, and 24 and 25 are contact openings of the interlayer insulating film 23. A source electrode and a drain electrode connected to the respective silicide layers 22a and 22b through a portion.

In this way, in the apparatus of the embodiment having such a structure, the oxidation resistant insulating film 20 through which contaminants and impurities are hard to pass
In this case, since the regions of each silicon oxide film other than the gate electrode 16 are covered by a and 20b, the invasion of these contaminants and impurities can be effectively prevented. As a result, the device configuration It is possible to effectively improve the long-term reliability such as the operating characteristics in.

Next, a method of manufacturing an n-channel field effect semiconductor device according to this embodiment will be described.

In the method of this embodiment, first, on the silicon oxide film (first insulating film) 12 embedded in the p-type single crystal silicon semiconductor substrate 11, the single crystal silicon layer (first semiconductor layer) is formed. ) 26 is formed and the surface of the single crystal silicon layer 26 is subjected to an oxidation treatment to form a silicon oxide film
7 is formed, and a silicon nitride film 28, for example, is deposited thereon as an oxidation resistant film (FIG. 2), and the silicon nitride film 28 is formed into a predetermined size by, for example, anisotropic plasma etching. The silicon oxide film 27 is partially exposed by selectively etching away the silicon oxide film 27, and the remaining silicon nitride film 28a is used as a mask to expose the exposed portion of the silicon oxide film 27 to, for example, fluorination. The single crystal silicon layer 26 is partially exposed by selective removal by a wet etching method using a hydrogen acid solution or the like, and each of the remaining silicon nitride film 28a and silicon oxide film 27a is masked. And the exposed single crystal silicon layer 26 is used for the silicon oxide film 12
By selectively oxidizing the silicon oxide film 13 to reach the temperature of 1 to form the isolation silicon oxide film 13 for element isolation, the remaining silicon layer 26a is electrically isolated from other silicon layers (FIG. 3). ).

Then, the upper silicon nitride film 28a used as the mask is removed by etching, for example, by a wet etching method using phosphoric acid or the like,
For example, p-type impurities are introduced into the silicon layer 26a through the silicon oxide film 27a by the ion implantation method (FIG. 4), and after this introduction, the silicon oxide film 2 is formed.
7a is removed by etching, for example, by wet etching using a hydrofluoric acid solution or the like to expose the p-type impurity introduced silicon layer 26a, and the surface of the p-type silicon layer 26a is again oxidized. Process,
A new thin silicon oxide film, in this case, a gate oxide film (second insulating film) 15 is formed, and a polycrystalline silicon layer for gate electrodes (second semiconductor layer) is formed on the gate oxide film 15. Is deposited and processed into a predetermined size by, for example, an anisotropic plasma etching method to form the gate electrode 16, and then the gate oxide film 15 is left under the gate electrode 16 directly below the gate electrode 16. The oxide film portion other than the above is removed by etching, for example, by wet etching using phosphoric acid and the like, and the silicon oxide film (third oxide
Insulating film 19) is formed (FIG. 5).

Thereafter, an oxidation resistant insulating film (fourth insulating film) 20 such as a silicon nitride film is deposited and covered on the entire surface, and further, for example, by an ion implantation method or the like. Through the oxidation resistant insulating film 20 and the silicon oxide film 19 into the p-type silicon layer 26a.
By introducing an n-type impurity, the gate electrode 16,
And the n-type high-concentration source region 17 with the p-type active region 14 left in the portion corresponding to the gate oxide film 15,
And a high-concentration drain region 18 are formed in each (FIG. 6).

Next, the oxidation resistant insulating film 2 covering the entire surface is formed.
0 again on the silicon oxide film (fifth insulating film) 2
1 and a portion of the gate electrode 16 including the p-type active region 14 and each n-type high-concentration source region 1
7. Except for the high-concentration drain region 18, the resist pattern 29 is formed correspondingly on the isolation silicon oxide film 13 (FIG. 7), and the resist pattern 29 is used as a mask. , The silicon oxide film 21 is removed by etching until a part of the oxidation resistant insulating film 20 is exposed by, for example, an anisotropic plasma etching method. By forming the silicon oxide films 21a, 21a on the peripheral side portion covered with the silicon oxide film 19 and removing the resist pattern 29 used for the mask, the silicon oxide film 21b is formed on the isolated silicon oxide film 13. , 21b are left (FIG. 8).

Subsequently, the silicon oxide films 21a and 2a are formed.
The oxidation resistant insulating film 20 is selectively removed by a wet etching method using phosphoric acid or the like using the masks 1a, 21b and 21b as masks to expose the silicon oxide film 19 at each corresponding portion. In addition, each n
The high-concentration source region 17 and the high-concentration drain region 18 of the n-type are selectively removed by, for example, a wet etching method using a hydrofluoric acid solution or the like. The source region 17 and the high concentration drain region 18 are exposed (FIG. 9).

A transition metal layer 30 such as titanium (Ti) is deposited on all of these surfaces (FIG. 10), and this is placed in an inert gas atmosphere at a temperature of 700. By subjecting the metal layer 30 to a part of each of the n-type high-concentration source regions 17 and the high-concentration drain regions 18 by performing a heat treatment for about 20 ° C. for about 20 minutes, each of the n-type high-concentrations Source-side and drain-side silicide layers 22a and 22b are formed on the source region 17 and the high-concentration drain region 18, and an interlayer insulating film 23 is deposited on the silicide layers 22a and 22b. A source electrode 24 and a drain electrode 25 are connected and formed to the respective silicide layers 22a and 22b through the contact openings (see FIG. 1).
1) In this way, the intended field effect semiconductor device can be manufactured.

In the process of FIG. 10, instead of depositing the metal layer 30 on the entire surface, each exposed n-type high-concentration source region 17 and high-concentration drain region 1 is exposed.
Source side and drain side silicide layers 22a and 22b may be selectively formed on the surface portion of 8,
Further, a similar metal layer or silicide layer may be formed on the gate electrode 16.

[0041]

As described above in detail with reference to the embodiments,
According to the present invention, in the structure of the field effect semiconductor device in which the silicide layer is formed in the source / drain regions to reduce the resistance, the high-speed operation is enabled. On the other hand, the following effects can be obtained because the oxidation-resistant insulating film, which does not easily allow contaminants and impurities to pass therethrough, is covered. (1) By providing the oxidation resistant insulating film in this way, it is possible to favorably prevent the diffusion of contaminants, impurities, etc. remaining during the formation of the silicide layer into the inside of the structure, and to stabilize the operating characteristics of the device. obtain. (2) Similarly, by providing an oxidation resistant insulating film in this manner, it is possible to block moisture that permeates from various insulating films used for insulation of electrodes, wiring, etc. The operation characteristics of the device can be stabilized, and in addition, the long-term reliability of the device configuration can be secured. (3) In addition, since the formation film that leaves a trace at the time of high-dose ion implantation at the time of manufacturing is covered with this oxidation-resistant insulating film, the silicide layer is formed.・ There is no fear of leaving a residue due to abnormal reaction of the silicide raw material in each region except the drain region.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a schematic configuration of an n-channel field effect semiconductor device to which an embodiment of the present invention is applied.

FIG. 2 is a cross-sectional view schematically showing a first step in the method for manufacturing an n-channel field effect semiconductor device according to the example of the same.

FIG. 3 is a cross-sectional view schematically showing a second step in the method of the above embodiment.

FIG. 4 is a cross-sectional view schematically showing a third step in the method according to the first embodiment.

FIG. 5 is a cross sectional view schematically showing a fourth step in the method according to the first embodiment.

FIG. 6 is a cross-sectional view schematically showing a fifth step in the method of Example above.

FIG. 7 is a cross sectional view schematically showing a sixth step in the method of the above embodiment.

FIG. 8 is a cross-sectional view schematically showing a seventh step in the method according to the above embodiment.

FIG. 9 is a cross-sectional view schematically showing an eighth step in the method of Example above.

FIG. 10 is a cross-sectional view schematically showing a ninth step in the method of the above embodiment.

FIG. 11 is a cross sectional view schematically showing a tenth step in the method according to the first embodiment.

FIG. 12 is a sectional view schematically showing a schematic configuration of an n-channel field effect semiconductor device according to a conventional example.

FIG. 13 is a cross-sectional view schematically showing a first step in the method for manufacturing an n-channel field effect semiconductor device in the conventional example.

FIG. 14 is a cross-sectional view schematically showing a second step in the above conventional method.

FIG. 15 is a cross-sectional view schematically showing a third step in the above conventional example method.

FIG. 16 is a cross-sectional view schematically showing a fourth step in the above-mentioned conventional example method.

FIG. 17 is a cross-sectional view schematically showing a fifth step in the above-mentioned conventional method.

FIG. 18 is a cross-sectional view schematically showing a sixth step in the above-mentioned conventional method.

FIG. 19 is a cross-sectional view schematically showing a seventh step in the above-mentioned conventional method.

FIG. 20 is a cross-sectional explanatory view schematically showing a problem that occurs in the configuration of an n-channel type field effect semiconductor device according to a conventional example.

[Explanation of symbols]

11 p-type single crystal silicon semiconductor substrate 12 silicon oxide film 13 isolation silicon oxide film 14 p-type active region 15 gate oxide film 16 gate electrode 17 n-type high-concentration source region 18 n-type high-concentration drain region 19 silicon oxide film 20, 20a , 20b Oxidation-resistant insulating film 21 Silicon oxide films 21a, 21b Side silicon oxide films, silicon oxide films 22a, 22b Source-side and drain-side silicide layers 23 Interlayer insulating film 24 Source electrode 25 Drain electrode 26 Silicon layer 26a p Type silicon layer 27, 27a silicon oxide film 28, 28a silicon nitride film 29 resist pattern 30 transition metal layer

Claims (2)

[Claims] 1. A first-conductivity-type first semiconductor layer having a predetermined size and formed by being divided by an isolation insulating film on a first insulating film embedded in a semiconductor substrate, and the first semiconductor layer. A second semiconductor layer having a predetermined size and serving as a gate electrode, which is formed via a second insulating film serving as a gate insulating film, and a third insulating film formed so as to cover the second semiconductor layer. And a fourth side provided on the peripheral side portion of the second semiconductor layer covered with the third insulating film and on the isolation oxide film, respectively.
An oxidation-resistant insulating film, a first conductive type active region left corresponding to the second semiconductor layer and the second insulating film in the first semiconductor layer, and a second conductive type Of the second conductivity type impurity regions, which are source / drain regions and are formed by introducing the impurities of 1., and a second oxidation-resistant insulating film interposed between the second insulating type impurity regions. A fifth insulating film formed on a peripheral side portion of the semiconductor layer and a fourth oxidation resistant insulating film of the isolation insulating film, and silicides formed on the impurity regions and formed on the impurity regions. A field effect semiconductor device comprising at least: 2. A step of forming, on a first insulating film embedded in a semiconductor substrate, a first semiconductor layer of a first conductivity type divided by an isolation insulating film and having a predetermined dimension, and the first semiconductor. Forming a second insulating film to be a gate insulating film on the layer, and forming a second semiconductor layer having a predetermined size to be a gate electrode through the second insulating film; A step of sequentially forming a third insulating film and a fourth oxidation resistant insulating film on the first semiconductor layer including a semiconductor layer and the isolation insulating film, and the fourth oxidation resistant insulating film , And a third insulating film to introduce impurities of the second conductivity type into the first semiconductor layer, and active portions of the first conductivity type are introduced into portions corresponding to the second semiconductor layer and the second insulating film. The second conductivity type impurity regions serving as the source / drain are formed in the respective regions leaving the regions. And a step of forming a fifth insulating film on the fourth oxidation resistant insulating film, and selectively removing the fifth insulating film portion corresponding to each of the impurity regions. The third side of the second semiconductor layer, which is covered with the third insulating film and has the fourth oxidation resistant insulating film interposed therebetween, and the fourth oxidation resistant insulating film of the isolation insulating film, respectively. Remaining insulating film, and selectively removing the fourth oxidation resistant insulating film portion to expose the impurity regions and to form a transition metal layer including the exposed impurity region portions. After the formation, a heat treatment is performed to form each silicide layer corresponding to each of these impurity regions, respectively. At least, a method of manufacturing a field-effect semiconductor device.